TWI555169B - Driving circuit structure and manufacturing method thereof - Google Patents

Description

Drive circuit structure and manufacturing method thereof

The present invention relates to a circuit structure and a method of fabricating the same, and more particularly to a driver circuit structure and a method of fabricating the same.

In the driver circuit structure, multiple transistors are often used to achieve the desired signal transfer mode. Therefore, the operational reliability of the transistor is often an important consideration in the structure of the driver circuit. In general, in order to achieve a particular signal transfer mode, there are many transistors in the driver circuit structure, and different transistors may be driven in different or identical modes. For example, some transistors are driven in a mode that applies a positive bias for a long time and some transistors are driven in a mode that applies a negative bias for a long time. Therefore, the fabrication of all transistors using uniform specifications and conditions may result in good performance of the transistor in some drive modes but poor performance in the other drive mode. Therefore, there is still room for improvement in the structure of the drive circuit.

The invention provides a driving circuit structure with good operational reliability.

The invention provides a manufacturing method of a driving circuit structure, and produces a driving circuit structure with good operation reliability without increasing excessive cost.

The driving circuit structure of the present invention is disposed on a substrate and includes a first thin film transistor, a second thin film transistor, a first insulating layer and a second insulating layer. The first thin film transistor has a first semiconductor channel region. The second thin film transistor has a second semiconductor channel region. The first insulating layer covers the first thin film transistor and has an opening. The area of the opening exposes the area of the second semiconductor channel region of the second thin film transistor. The second insulating layer is disposed on the first insulating layer, covers the second thin film transistor, and fills an area of the opening to cover an area of the second semiconductor channel region.

A method for fabricating a driving circuit structure includes: fabricating a first thin film transistor and a second thin film transistor on a substrate, wherein the first thin film transistor has a first semiconductor channel region and the second film The transistor has a second semiconductor channel region; and a first insulating layer and a second insulating layer are sequentially formed on the substrate. The first insulating layer covers the first thin film transistor, the first insulating layer has an opening, the area of the opening exposes an area of the second semiconductor channel region of the second thin film transistor, and the second insulating layer is disposed on the first insulating layer Covering the second thin film transistor and filling the area of the opening to cover the area of the second semiconductor channel region.

Based on the above, the thin film transistor in which the driving circuit structure of the embodiment of the present invention operates in different modes can similarly have good driving reliability.

The above described features and advantages of the present invention will be more apparent from the following description.

1, 2, 3‧‧‧Lighting elements

10‧‧‧Substrate

100, 200, 300, 400, 500‧‧‧ drive circuit structure

110, 410, 510, 310‧‧‧ first film transistor

110C, 120C, 310C, 320C, 410C, 420C, 510C, 520C‧‧‧ semiconductor channel layer

110CH, 120CH, 310CH, 320CH‧‧‧ conductor channel area

110D, 120D, 410D, 420D, 510D, 520D‧‧‧汲

110G, 120G, 410G, 420G, 510G1, 510G2, 520G1, 520G2‧‧ ‧ gate

110S, 120S, 410S, 420S, 510S, 520S‧‧‧ source

120, 320, 420, 520‧‧‧ second thin film transistor

130, 430, 530‧‧‧ first insulation

130A, 430A, 530A‧‧‧ openings

140, 440, 540‧‧‧Second insulation

150, 450, 550‧‧‧ scan lines

160, 460, 560‧‧‧ data lines

170, 470, 570‧‧‧ power cord

180, 480, 580‧‧‧ capacitor structure

182, 184‧‧‧

190, 490, 590‧ ‧ organic light-emitting elements

192‧‧‧electrode

GI, GI1, GI2‧‧‧ gate insulation

IL‧‧‧ interlayer insulation

IS1, IS2‧‧‧ etching barrier pattern

S1‧‧‧ first side

S2‧‧‧ second side

TH1, TH2, V1, V2, V3‧‧‧ contact window

1A to 1C illustrate a method of fabricating a driving circuit structure in accordance with an embodiment of the present invention.

2 is a top plan view of a light emitting device to which a driving circuit structure is applied according to an embodiment of the present invention.

3 is a cross-sectional view showing the structure of a driving circuit according to another embodiment of the present invention.

4 is a cross-sectional view showing the structure of a driving circuit according to still another embodiment of the present invention.

5A to 5C illustrate a method of fabricating a driving circuit structure according to an embodiment of the present invention.

Fig. 6 is a top plan view showing a light-emitting element applied to a structure of a driving circuit according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the structure of a driving circuit according to another embodiment of the present invention.

Fig. 8 is a top plan view showing a light-emitting element applied to a structure of a driving circuit according to an embodiment of the present invention.

1A to 1C illustrate a method of fabricating a driving circuit structure in accordance with an embodiment of the present invention. In FIGS. 1A to 1C, the thickness and width of each film layer are for illustrative purposes only, and are not limited thereto. Referring to FIG. 1A, a first thin film transistor 110 and a second thin film transistor 120 are formed on a substrate 10. The first thin film transistor 110 includes a gate 110G, a semiconductor channel layer 110C, a source 110S and a gate. pole 110D, and the second thin film transistor 120 includes a gate 120G, a semiconductor channel layer 120C, a source 120S, and a drain 120D.

In this embodiment, the gate 110G and the gate 120G are disposed on the same plane of the substrate 10, and are made of the same conductive layer, but are not limited thereto. A gate insulating layer GI is disposed above the gate 110G and the gate 120G such that the gate 110G and the gate 120G are located between the substrate 10 and the gate insulating layer GI. The semiconductor channel layer 110C and the semiconductor channel layer 120C are disposed on the gate insulating layer GO. Therefore, the gate insulating layer GI is located between the gate 110G and the semiconductor channel layer 110C and between the gate 120G and the semiconductor channel layer 120C. In other words, the gate 110G and the gate 120G are located on a first side S1 of the gate insulating layer GI, and the semiconductor channel layer 110C and the semiconductor channel layer 120C are located on a second side S2 of the gate insulating layer GI, and the first side S1 and the first side The two sides S2 are opposite.

The source 110S and the drain 110D are disposed on the semiconductor channel layer 110C, and the source 120S and the drain 120D are disposed on the semiconductor channel layer 120C. In the present embodiment, the source 110S and the drain 110D cover and contact a portion of the semiconductor channel layer 110C and expose the semiconductor channel region 110CH. That is, a portion of the area of the semiconductor channel layer 110C is the semiconductor channel region 110CH. The first gate 110G of the first thin film transistor 110 is used to control the enable or disable of the semiconductor channel region 110CH, and the source 110S and the drain 110D are electrically connected to each other through the enabled semiconductor channel region 110CH. The source 120S and the drain 120D cover and contact a portion of the semiconductor channel layer 120C and expose the semiconductor channel region 120CH. That is, a portion of the area of the semiconductor channel layer 120C is the semiconductor channel region 120CH. Second thin film transistor 120 The first gate 120G is used to control the enable or disable of the semiconductor channel region 120CH, and the source 120S and the drain electrode 120D are electrically connected to each other through the enabled semiconductor channel region 120CH.

In terms of materials, the gate 110G, the gate 120G, the source 110S, the source 120S, the drain 110D, and the drain 120D may be made of a conductive material such as a metal, a metal oxide, a metal nitride, or other non- Metal conductive material. The conductive material layer used for the gate 110G, the gate 120G, the source 110S, the source 120S, the drain 110D and the drain 120D may be a single material or a composite material, and these members may be stacked with a plurality of layers of conductive materials. . The semiconductor channel layer 110C and the semiconductor channel layer 120C may be made of an oxide semiconductor material. Specifically, the oxide semiconductor material is, for example, indium gallium zinc oxide, zinc oxide, indium oxide or the like.

Next, referring to FIG. 1B, a first insulating layer 130 is formed on the substrate 10 on which the first thin film transistor 110 and the second thin film transistor 120 have been formed. The first insulating layer 130 covers the first thin film transistor and has an opening 130A, wherein the area of the opening 130A exposes at least the area of the semiconductor channel region 120CH of the second thin film transistor 120.

At this time, the first insulating layer 130 can serve as a protective layer of the first thin film transistor 110. However, the semiconductor channel region 120CH of the second thin film transistor 120 is still exposed. Therefore, referring to FIG. 1C , a second insulating layer 140 is formed on the first insulating layer 130 , wherein the second insulating layer 140 covers the second thin film transistor 120 as a protective layer of the second thin film transistor 120 . That is, the second insulating layer 140 covers the second thin film transistor 120 and fills the area of the opening 130A to cover the area of the first semiconductor channel region 110CH. In addition, as can be seen from FIG. 1C, the first thin film transistor The first insulating layer 130 is covered with a second insulating layer 140, and the second thin film transistor 120 is covered with only the second insulating layer 140 to form the driving circuit structure 100.

In this embodiment, the materials of the first insulating layer 130 and the second insulating layer 140 may be determined according to the mode in which the thin film transistors 110 and 120 are to be operated. For example, the first thin film transistor 110 is expected to be negatively biased for a long period of time during operation, and the second thin film transistor 120 is expected to be positively biased for a long period of time during operation, and the first insulating layer 130 is not included. An aluminum insulating layer, and the second insulating layer 140 is an aluminum-containing insulating layer. In addition, the first thin film transistor 110 is expected to be positively biased for a long period of time during operation, and the second thin film transistor 120 is expected to be negatively biased for a long period of time during operation, and the first insulating layer 130 is an aluminum-containing insulating layer. And the second insulating layer 130 is a non-aluminum insulating layer. In general, the non-aluminum-containing insulating layer may be composed of a hafnium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer or a stack thereof, and the aluminum-containing insulating layer is, for example, an aluminum oxide layer, a hafnium aluminum oxide layer or a stack thereof. Come to form.

In this embodiment, in response to the manner in which the first thin film transistor 110 and the second thin film transistor 120 are to be operated, an opening 130A is disposed in the first insulating layer 130 to allow the first thin film transistor 110 and the second thin film transistor 120 to be disposed. The protective layer is made of different insulating materials. As a result, both the first thin film transistor 110 and the second thin film transistor 120 can have ideal operational reliability. For example, in an experimental example, an aluminum-containing insulating layer was used as a protective layer of a thin film transistor. If the thin film transistor is operated for a long time by applying a positive bias for 8.5 hours, the feedthrough voltage of the thin film transistor is shifted by about 0.29 Ford, and the film is operated by applying a negative bias for a long period of time. The transistor has a feed-through voltage offset of approximately 1.41 Ford for up to 8.5 hours. Therefore, when the aluminum-containing insulating layer is used as a protective layer of the thin film transistor, the thin film transistor is relatively stable under a positive bias. In another experimental example, a non-aluminum-containing insulating layer was used as a protective layer of the thin film transistor. If the thin film transistor is operated for a long period of time by applying a positive bias for 8.5 hours, the feedthrough voltage of the thin film transistor is shifted by about 0.9 Ford, and the thin film transistor is operated if a negative bias is applied for a long period of time. For 8.5 hours, the feedthrough voltage of this thin film transistor was shifted by approximately 0.22 Ford. Therefore, the non-aluminum-containing insulating layer acts as a protective layer for the thin film transistor, and the thin film transistor operates stably under a negative bias voltage. Therefore, the structural design of the first insulating layer 130 and the second insulating layer 140 in the present embodiment enables both the first thin film transistor 110 and the second thin film transistor 120 to have good operational reliability.

The drive circuit structure 100 can be applied in various fields. Hereinafter, the driving circuit structure 100 is applied to a driving circuit of an organic light emitting element as an example, but is not limited thereto. 2 is a top plan view of a light emitting device to which a driving circuit structure is applied according to an embodiment of the present invention. Referring to FIG. 2 , the light-emitting element 1 includes a first thin film transistor 110 , a second thin film transistor 120 , a first insulating layer 130 , a second insulating layer 140 , a scan line 150 , a data line 160 , a power line 170 , and A capacitor structure 180 drives an organic light emitting element 190. The first thin film transistor 110 is connected to the scan line 150 and the data line 160. The second thin film transistor 120 is connected to the power line 170 and the organic light emitting element 190. The scan line 150 is used to enable the first thin film transistor 110 to enable the data line 160. The transmitted one switching signal is transmitted to the second thin film transistor 120 by the enabled first thin film transistor 110; and the second thin film transistor 120 is passed through the data line 160 The switching signal is enabled to cause a power signal of the power line 170 to be transmitted to the organic light emitting element 190 via the enabled second thin film transistor 120. One end 182 of the capacitor structure 180 is connected between the first thin film transistor 110 and the second thin film transistor 120, and the other end 184 of the capacitor structure 180 is connected between the second thin film transistor 120 and the organic light emitting element 190. The light-emitting element 1 is here a double-crystal-capacitor (2T1C) structure, but the driving circuit of the organic light-emitting element 190 is not limited thereto.

Specifically, in the first thin film transistor 110, the gate 110G is connected to the scan line 150, the source 110S is connected to the data line 160, and the drain 110D is connected to the gate 120G of the second thin film transistor 120 and the capacitor structure 180. One end 182, wherein the drain 110D of the first thin film transistor 110 can be connected to the gate 120G of the second thin film transistor 120 through the contact window V1. The source 120S of the second thin film transistor 120 is connected to the power line 170, and the drain 120D is connected to the electrode 192 of the organic light emitting element 190 and the other end 184 of the capacitor structure 180. The organic light emitting element 190 is an organic light emitting diode. In time, the electrode 192 can be a cathode or an anode.

In the present embodiment, the electrode 192 of the organic light emitting device 190 is composed of a gate 110G, a gate 120G, a source 110S, a source 120S, a drain 110D and another conductor layer other than the drain 120D, wherein the electrode 192 It can be fabricated on the second insulating layer 140 of FIG. 1C. Therefore, the electrode 1920 is connected to the drain 120D through the contact window V2. In addition, one end 182 of the capacitor structure 180 can be made of the same film layer as the source 110S, 120S and the drain electrodes 110D, 120D, and the other end 184 of the capacitor structure 180 can be made of the same film layer as the gate electrodes 110G, 120G. Thus, the ends 182 and 184 can be separated by the gate insulating layer GI in FIG. 1C. At the same time, terminal 184 can borrow It is connected to the drain 110D by the contact window V3.

As shown in FIG. 1C and FIG. 2, the opening 130A exposes the structure of the semiconductor channel region 120CH such that the first thin film transistor 110 and the second thin film transistor 120 are covered by the first insulating layer 130 and the second insulating layer 140 of different materials. Therefore, when the first thin film transistor 110 and the second thin film transistor 120 drive the organic light emitting element 190, the operation reliability can be achieved by using different modes of operation. However, in other embodiments, the thin film transistor exposed by the opening 130A of the first insulating layer 130 may also be selected as a transistor connected to the scan line and the data line, but the invention is not limited thereto.

3 is a cross-sectional view showing the structure of a driving circuit according to another embodiment of the present invention. Referring to FIG. 3, the driving circuit structure 200 is substantially similar to the driving circuit 100 of FIG. 1C, wherein the same components are denoted by the same reference numerals in the two embodiments, and the same components will not be described again. Specifically, the driving circuit structure 200 includes etch barrier patterns IS1 and IS2 in addition to all the components of the driving circuit structure 100, wherein the etch barrier pattern IS1 is located between the semiconductor channel region 110C and the first insulating layer 130, and the etch barrier pattern IS2 Located between the semiconductor channel region 120CH and the second insulating layer 140. Materials for etching the barrier patterns IS1 and IS2 include hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof.

In the present embodiment, during the process of fabricating the source electrodes 110S, 120S, the drain electrodes 110D, 120D, the first insulating layer 130 and the second insulating layer 140, the semiconductor channel regions 110CH and 120CH can be well protected. In the fabrication of the first insulating layer 130, the method of forming the first insulating layer 130 includes first forming an insulating material layer. (not shown) on the substrate 10 to cover the first thin film transistor 110, the second thin film transistor 120, the etching stopper pattern IS1 and the etching stopper pattern IS2. Next, a layer of insulating material (not shown) is patterned to form a first insulating layer 130 having openings 130A. Since the etch barrier pattern IS2 covers the semiconductor via region 120CH, neither the insulating material layer nor the etchant used for the patterned insulating material layer contact or affect the semiconductor channel regions 110CH and 120CH. Therefore, the semiconductor channel regions 110CH and 120CH can maintain the original quality without being damaged.

4 is a cross-sectional view showing the structure of a driving circuit according to still another embodiment of the present invention. Referring to FIG. 4, the driving circuit structure 300 is substantially similar to the driving circuit 100 of FIG. 1C, wherein the same components are denoted by the same reference numerals in the two embodiments, and the same components will not be described again. Specifically, the driving circuit structure 300 has the same components as the driving circuit structure 100, but in the first thin film transistor 310 and the second thin film transistor 320 of the driving circuit structure 300, the semiconductor channel layer 310C is disposed at the source Above the 110S and the drain 110D, and the semiconductor channel layer 320C is disposed above the source 120S and the drain 120D. The upper surface of the semiconductor channel layer 310C defines a semiconductor channel region 310CH and the upper surface of the semiconductor channel layer 320C defines a semiconductor channel region 320CH. That is, in this embodiment, a portion of the source 110S and a portion of the drain 110D are located between the gate insulating layer GI and the semiconductor channel layer 310C, and a portion of the source 120S and the drain 120D A portion of it is located between the gate insulating layer GI and the semiconductor channel layer 320C. In addition, the opening 130A exposes the entire upper surface of the semiconductor channel layer 320C, that is, the semiconductor channel region 320CH.

In the above embodiments, each of the transistors is a bottom gate type structure, that is, a gate position. Between the semiconductor island layer and the substrate, but not limited thereto. For example, FIG. 5A to FIG. 5C illustrate a method of fabricating a driving circuit structure according to an embodiment of the present invention. In FIGS. 5A to 5C, the thickness and width of each film layer are for illustrative purposes only, and are not limited thereto. Referring to FIG. 5A first, the semiconductor channel layers 410C and 420C, the gate insulating layers GI1 and GI2, and the gate electrodes 410G and 420G are sequentially formed on the substrate 10. The semiconductor channel layer 410C, the gate insulating layer GI1, and the gate 410G are sequentially stacked on the substrate 10, and the gate insulating layer GI1 is located between the gate 410G and the semiconductor channel layer 410C. Similarly, the semiconductor channel layer 420C, the gate insulating layer GI2, and the gate 420G are sequentially stacked on the substrate 10, and the gate insulating layer GI2 is located between the gate 420G and the semiconductor channel layer 420C. The gate electrodes 410G and 420G are made of a conductive material, the gate insulating layers GI1 and GI2 are made of an insulating material, and the semiconductor channel layers 410C and 420C are made of an oxide semiconductor material.

Next, referring to FIG. 5B, a first insulating layer 430 is formed on the substrate 10, and the first insulating layer 430 has an opening 430A to expose the semiconductor channel layer 420C. At this time, the gate 420G is also exposed by the opening 430A. Then, referring to FIG. 5C, a second insulating layer 440, source 410S, 420S and drains 410D, 420D are formed on the first insulating layer 430 to constitute the driving circuit structure 400. Here, the gate 420G contacts the second insulating layer 440 and is completely covered by the second insulating layer 440. A first insulating layer 430 is sandwiched between the gate 410G and the second insulating layer 440. The source 410S and the drain 410D both penetrate the first insulating layer 430 and the second insulating layer 440 to be connected to the semiconductor channel layer 410C. The source 420S and the drain 420D extend through the second insulating layer 440 to be connected to the semiconductor channel layer 420C.

In this embodiment, the gate 410G, the semiconductor channel layer 410C, the source 410S and the drain 410D constitute a first thin film transistor 410, and the gate 420G, the semiconductor channel layer 420C, the source 420S and the drain 420D constitute a second Thin film transistor 420. The first insulating layer 430 serves as a protective layer of the first thin film transistor 410 and the second insulating layer 440 serves as a protective layer of the second thin film transistor 420. The materials of the first insulating layer 410 and the second insulating layer 420 may be The mode of operation of the first thin film transistor 410 and the second thin film transistor 420 is determined.

Specifically, the first thin film transistor 410 is expected to be negatively biased for a long period of time during operation, and the second thin film transistor 420 is expected to be positively biased for a long period of time during operation, and the first insulating layer 430 is not included. An aluminum insulating layer, and the second insulating layer 430 is an aluminum-containing insulating layer. In addition, the first thin film transistor 410 is expected to be positively biased for a long period of time during operation, and the second thin film transistor 420 is expected to be negatively biased for a long period of time during operation, and the first insulating layer 430 is an aluminum-containing insulating layer. And the second insulating layer 430 is a non-aluminum insulating layer. In general, the non-aluminum-containing insulating layer may be composed of a hafnium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer or a stack thereof, and the aluminum-containing insulating layer is, for example, an aluminum oxide layer, a hafnium aluminum oxide layer or a stack thereof. Come to form. As a result, both the first thin film transistor 410 and the second thin film transistor 420 can have ideal operational reliability.

The drive circuit structure 400 can be applied in various fields. Hereinafter, the driving circuit structure 400 is applied to the driving circuit of the organic light emitting element as an example, but is not limited thereto. Fig. 6 is a top plan view showing a light-emitting element applied to a structure of a driving circuit according to an embodiment of the present invention. 5C and FIG. 6, the light-emitting element 2 includes the first a thin film transistor 410, a second thin film transistor 420, a first insulating layer 430, a second insulating layer 440, a scan line 450, a data line 460, a power line 470, and a capacitor structure 480 to drive an organic light emitting element. 490. The first thin film transistor 410 is connected to the scan line 450 and the data line 460. The second thin film transistor 420 is connected to the power line 470 and the organic light emitting element 490. The scan line 450 is used to enable the first thin film transistor 410 to enable the data line 460. The transmitted switching signal is transmitted to the second thin film transistor 420 by the enabled first thin film transistor 410; and the second thin film transistor 420 is enabled by the switching signal of the data line 460 to enable the power supply line 470 The power signal is transmitted to the organic light emitting element 490 through the enabled second thin film transistor 420. The light-emitting element 2 is here a double-crystal-capacitor (2T1C) structure, but the driving circuit of the organic light-emitting element 490 is not limited thereto. In other embodiments, the thin film transistor exposed by the opening 430A of the first insulating layer 430 may also be selected as a transistor connected to the scan line and the data line, but the invention is not limited thereto.

The above embodiments are all described by a single-gate thin film transistor, but the invention is not limited thereto. FIG. 7 is a cross-sectional view showing the structure of a driving circuit according to another embodiment of the present invention. Referring to FIG. 7 , the driving circuit 500 includes a first thin film transistor 510 , a second thin film transistor 520 , an interlayer insulating layer IL , an etch barrier pattern IS1 , an etch barrier pattern IS2 , a first insulating layer 530 , and a second insulating layer 540 . The first thin film transistor 510 and the second thin film transistor 520 are both double gate thin film transistors.

Specifically, the first thin film transistor 510 includes a gate 510G1, a gate 510G2, a semiconductor channel layer 510C, a source 510S, and a drain 510D. The gate 510G1 is disposed on the substrate 10 and the gate 510G1 is covered by the gate insulating layer GI. Semiconductor communication The via layer 510C is disposed on the gate insulating layer GI such that the gate electrode 510G and the semiconductor channel layer 510C are located on opposite sides of the gate insulating layer GI. The etch barrier pattern IS1 is disposed on the semiconductor channel layer 510C, and the source 510S and the drain 510D are disposed on the semiconductor channel layer 510C, wherein a portion of the etch barrier pattern IS1 is located between the source 510S and the semiconductor channel layer 510C. A portion is located between the drain 510D and the semiconductor channel layer 510C to protect the semiconductor channel layer 510C from damage during the patterning process of the source 510S and the drain 510D. The interlayer insulating layer IL covers the semiconductor channel layer 510C, the source 510S and the drain 510D, and the gate 510G2 is disposed on the interlayer insulating layer IL. Here, the gate 510G2 is connected to the gate 510G1 through the contact window TH1, and the contact window TH1 penetrates the interlayer insulating layer IL and the gate insulating layer GI.

Similarly, the second thin film transistor 520 includes a gate 520G1, a gate 520G2, a semiconductor channel layer 520C, a source 520S, and a drain 520D. The gate 520G1 is disposed on the substrate 10 and the gate 520G1 is covered by the gate insulating layer GI. The semiconductor channel layer 520C is disposed on the gate insulating layer GI such that the gate 520G and the semiconductor channel layer 520C are located on opposite sides of the gate insulating layer GI. The etch barrier pattern IS2 is disposed on the semiconductor channel layer 520C, and the source 520S and the drain 520D are disposed on the semiconductor channel layer 520C, wherein a portion of the etch barrier pattern IS2 is located between the source 520S and the semiconductor channel layer 520C. A portion is located between the drain 520D and the semiconductor channel layer 520C to protect the semiconductor channel layer 520C from damage during the patterning process of the source 520S and the drain 520D. The interlayer insulating layer IL covers the semiconductor channel layer 520C, the source 520S and the drain 520D, and the gate 520G2 is disposed on the interlayer insulating layer IL. Here, the gate 520G2 is connected to the gate 520G1 through the contact window TH2, and The contact window TH2 penetrates the interlayer insulating layer IL and the gate insulating layer GI.

In addition, the first insulating layer 530 covers the first thin film transistor 510 as a protective layer of the first thin film transistor 510 and has an opening 530A, wherein the opening 530A exposes at least the area of the semiconductor channel layer 520C in the second thin film transistor 520. . The second insulating layer 540 is disposed on the first insulating layer 530 to fill the area of the opening 530A. Therefore, the second insulating layer 540 serves as a protective layer of the second thin film transistor 520.

The first thin film transistor 510 and the second thin film transistor 520 are protected by the first thin film transistor 510 and the second thin film transistor 520 in the driving circuit structure 500. It can be operated in different modes to maintain the ideal operational reliability. The first thin film transistor 510 is expected to be negatively biased for a long period of time during operation, and the second thin film transistor 520 is expected to be positively biased for a long period of time during operation, and the first insulating layer 530 is a non-aluminum insulating layer. And the second insulating layer 530 is an aluminum-containing insulating layer. In addition, the first thin film transistor 510 is expected to be positively biased for a long period of time during operation, and the second thin film transistor 520 is expected to be negatively biased for a long period of time during operation, and the first insulating layer 530 is an aluminum-containing insulating layer. And the second insulating layer 430 is a non-aluminum insulating layer. In general, the non-aluminum-containing insulating layer may be composed of a hafnium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer or a stack thereof, and the aluminum-containing insulating layer is, for example, an aluminum oxide layer, a hafnium aluminum oxide layer or a stack thereof. Come to form.

The drive circuit structure 500 can be applied in various fields. Hereinafter, the driving circuit structure 500 is applied to the driving circuit of the organic light emitting element as an example, but is not limited thereto. FIG. 8 is a schematic diagram of a driving circuit structure according to an embodiment of the present invention; A schematic top view of a light emitting element. Referring to FIG. 7 and FIG. 8 , the light-emitting element 3 includes a first thin film transistor 510 , a second thin film transistor 520 , a first insulating layer 530 , a second insulating layer 540 , a scan line 550 , a data line 560 , and a power source . Line 570 and a capacitor structure 580 drive an organic light emitting element 590. The first thin film transistor 510 is connected to the scan line 550 and the data line 560. The second thin film transistor 520 is connected to the power line 570 and the organic light emitting element 590. The scan line 550 is used to enable the first thin film transistor 510 to enable the data line 560. The transmitted switching signal is transmitted to the second thin film transistor 520 via the enabled first thin film transistor 510; and the second thin film transistor 520 is enabled by the switching signal of the data line 560 to enable the power supply line 570 The power signal is transmitted to the organic light emitting element 590 via the enabled second thin film transistor 520. The light-emitting element 3 is here a double-crystal-capacitor (2T1C) structure, but the driving circuit of the organic light-emitting element 590 is not limited thereto. As can be seen from FIG. 7 and FIG. 8 , the opening 530A of the first insulating layer 530 exposes the area of the second thin film transistor 520 to make the second insulating layer 540 serve as a protective layer of the second thin film transistor 520. In this way, when the first thin film transistor 510 and the second thin film transistor 520 are to be operated in different modes, the first insulating layer 530 and the second insulating layer 540 may be made of different materials to allow the first thin film transistor 510 to The second thin film transistor 520 has good operational reliability. However, in other embodiments, the thin film transistor exposed by the opening 530A of the first insulating layer 530 may also be selected as a transistor connected to the scan line and the data line, but the invention is not limited thereto.

In summary, in the driving circuit structure of the embodiment of the invention, the thin film transistors of different operation modes are protected by a protective layer of different materials. Therefore, drive The circuit structure can have ideal operational reliability.

10‧‧‧Substrate

100‧‧‧Drive circuit structure

110‧‧‧First film transistor

110C, 120C‧‧‧ semiconductor channel layer

110CH, 120CH‧‧‧Semiconductor channel area

110D, 120D‧‧‧汲

110G, 120G‧‧‧ gate

110S, 120S‧‧‧ source

120‧‧‧Second thin film transistor

130‧‧‧First insulation

130A‧‧‧ openings

140‧‧‧Second insulation

GI‧‧‧ brake insulation

S1‧‧‧ first side

S2‧‧‧ second side

Claims (10)

A driving circuit structure is disposed on a substrate and includes: a first thin film transistor having a first semiconductor channel region; a second thin film transistor having a second semiconductor channel region; and a first insulating layer, Covering the first thin film transistor and having an opening, an area of the opening exposing an area of the second semiconductor channel region of the second thin film transistor; and a second insulating layer disposed on the first insulating layer Covering the second thin film transistor and filling the area of the opening to cover the area of the second semiconductor via region. The driving circuit structure of claim 1, wherein the second insulating layer covers the first thin film transistor and the second thin film transistor. The driving circuit structure of claim 1, wherein one of the first insulating layer and the second insulating layer is an aluminum-containing insulating layer, and the other is not. The driving circuit structure of claim 3, wherein the first insulating layer is the aluminum-containing insulating layer and the first thin film transistor is used to apply a positive bias, and the second thin film transistor is used to apply Negative bias. The driving circuit structure of claim 3, wherein the second insulating layer is the aluminum-containing insulating layer and the first thin film transistor is used to apply a negative bias, and the second thin film transistor is used to apply Positive bias. The driving circuit structure of claim 1, further comprising a first etch barrier pattern and a second etch barrier pattern, the first etch barrier pattern being located in the first semiconductor via region and the first insulating layer And the second etch barrier A pattern is between the second semiconductor channel region and the second insulating layer. The driving circuit structure of claim 1, wherein the first thin film transistor comprises a first gate, a first source, a first drain and a first semiconductor channel layer, the first a portion of the semiconductor channel layer is the first semiconductor channel region, the first gate is used to control the enabling of the first semiconductor channel region, and the first source and the first drain are enabled. The first semiconductor channel region is electrically connected to each other; and the second thin film transistor includes a second gate, a second source, a second drain, and a second semiconductor channel layer, the second semiconductor channel layer a portion of the area is the second semiconductor channel region, the second gate is for controlling the enabling of the second semiconductor channel region, and the second source and the second drain are enabled by the second semiconductor The channel areas are electrically connected to each other. The driving circuit structure of claim 7, further comprising a gate insulating layer, the first gate and the second gate being located on a first side of the gate insulating layer, and the first semiconductor channel layer And the second semiconductor channel layer is located on a second side of the gate insulating layer, and the first side is opposite to the second side. A method for fabricating a driving circuit structure includes: fabricating a first thin film transistor and a second thin film transistor on a substrate, wherein the first thin film transistor has a first semiconductor channel region, and the second thin film is electrically The crystal has a second semiconductor channel region; and a first insulating layer and a second insulating layer are sequentially formed on the substrate, the first insulating layer covers the first thin film transistor and has an opening, the opening An area exposing an area of the second semiconductor channel region of the second thin film transistor, and the The second insulating layer is disposed on the first insulating layer to cover the second thin film transistor and fill the area of the opening to cover the area of the second semiconductor channel region. The method for fabricating the driving circuit structure of claim 9, further comprising forming a first etch barrier pattern and a second etch barrier pattern before forming the first insulating layer and the second insulating layer. The first semiconductor channel region and the second semiconductor channel region.