TWI553858B - Multi-gate field effect transistor and its process - Google Patents

Description

Multi-gate field effect transistor and its process

The present invention relates to a multi-gate field effect transistor and a process thereof, and more particularly to a fin structure and a fin structure which are formed on a sidewall of a partial fin structure and are not covered by a liner layer. A multi-gate field effect transistor with a substrate oxidation between it and its process.

As the size of semiconductor components shrinks, maintaining the performance of small-sized semiconductor components is currently the main goal of the industry. In order to improve the performance of semiconductor components, various multi-gate MOSFETs have been developed. Multi-gate field effect transistor components include the following advantages. First, the process of the multi-gate field-effect transistor component can be integrated with the conventional logic component process, so it has considerable process compatibility. Secondly, since the three-dimensional structure increases the contact area between the gate and the substrate, the gate can be increased. Controlling the charge of the channel region, thereby reducing the Drain Induced Barrier Lowering (DIBL) effect and the short channel effect caused by the small-sized components; in addition, since the same length of the gate has The larger the channel width, the more the current between the source and the drain can be increased.

In current semiconductor processes, localized oxidation isolation (LOCOS) or shallow trench isolation (STI) methods are generally used to isolate components to avoid short-circuit phenomena caused by mutual interference between components. As the design and manufacturing line width of semiconductor wafers become more and more fine, in the LOCOS process The disadvantages of pits, crystal defects, and bird's beak length are greatly affected, and the characteristics of the semiconductor wafer are greatly affected, and the field oxide layer produced by the LOCOS method occupies a large area. The volume affects the integration of the entire semiconductor wafer. Therefore, in the submicron multi-gate field effect transistor process, the small size and the semiconductor chip accumulation can be improved. The shallow trench isolation (STI) process has become a widely used isolation. A technique for isolating each of the plurality of gate field effect transistor elements, and in particular, forming shallow trench isolation between the fin structures to electrically insulate each other.

In addition, in the current process of multi-gate field-effect transistor components, the ion implantation process and the annealing process are directly performed under the respective fin structures and between the fin structures, in each fin shape. An opposite electrical channel stop is formed in the underside of the structure and in the substrate between the fin structures for electrically isolating the transistors on each fin structure. However, this isolation technique often suffers from insufficient doping amount during ion implantation, and the transistor on each fin structure cannot be completely electrically insulated and leaks.

The invention provides a multi-gate field effect transistor and a process thereof, which first form a liner layer on a sidewall of a partial fin structure, and then a fin structure not covered by the liner layer and a substrate between the fin structures Oxidation can solve the above problems.

The invention provides a multi-gate field effect transistor comprising a substrate, a dielectric layer and at least one fin structure. The substrate has a first zone and a second zone. Dielectric layer only In the base in the first zone. At least one fin structure is on the dielectric layer.

The invention provides a multi-gate field effect transistor process comprising the following steps. First, at least one fin structure is formed in a substrate and a liner layer is formed on the sidewall of an upper half of the fin structure and exposes the lower half of the fin structure. Next, an oxidation process is performed to oxidize the exposed lower half.

Based on the above, the present invention provides a multi-gate field effect transistor and a process thereof, which first form a liner layer on a sidewall of a partial fin structure, and then a fin structure and a fin structure not covered by the liner layer. The substrate is oxidized to form an oxide layer underneath or in the lower half of each fin structure and between the fin structures. Therefore, the fin structures can be electrically insulated from each other and the fin structures can be electrically connected to the substrate by locally completely oxidizing the lower or lower half of each fin structure and the substrate between the fin structures. For the purpose of insulation, the transistors formed on each of the fin structures are electrically insulated from each other, and the respective transistors are prevented from leaking downward to the substrate.

1-7 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a first embodiment of the present invention. First, as shown in FIG. 1, a substrate 110 is provided to include a first region A and at least a second region B. In a preferred embodiment, the substrate 110 may comprise a bulk substrate, the first region A may comprise a non-planar field effect transistor region, and the second region B may comprise a planar field effect transistor region or used to form other regions. The peripheral circuit area of the semiconductor component, but the invention is not limited thereto. Next, an upper half 112a of at least one fin structure 112 is formed. In the substrate 110 in the first zone A. In detail, a piece of substrate (not shown) may be first provided as the substrate 110, and a patterned hard mask layer 20 is formed thereon to define a corresponding block-shaped substrate to be correspondingly The location of the fin structure 112 is formed. The hard mask layer 20 may include a pad oxide layer 22 and a pad nitride layer 24, but the invention is not limited thereto. Next, an etching process is performed to form the upper half 112a of the fin structure 112 in a bulk substrate (not shown). Thus, the fabrication of the upper half 112a of the fin structure 112 in the substrate 110 is completed.

As shown in FIGS. 2-3, a liner layer 120 is formed on the sidewall of the upper half 112a of the fin structure 112 and exposes the lower half 112b of the fin structure 112. In detail, as shown in Fig. 2, a liner layer material 120' is completely covered first in the upper half portion 112a of the fin structure 112, the substrate 110, and the hard mask layer 20. In this embodiment, the pad layer material 120' may be a nitride layer, but in other embodiments, the pad layer material 120' may also be a single anti-oxidation single material layer or a composite layer. The fin structure 112 covered by the fin structure 112 is prevented from being oxidized in the subsequent oxidation process. The material of the oxidation resistant single material layer or composite layer may be bismuth oxynitride, amorphous carbon or lanthanum carbide. As shown in FIG. 3, an etching process P1 is performed to remove a portion of the liner layer material 120' to form a liner layer 120 on the sidewall of the upper half 112a of the fin structure 112 and expose the fin structure. The lower half 112b of 112. In the present embodiment, the etching process P1 is a dry etching process, which can perform an anisotropic etching, thereby etching the fin structure 112 having vertical sidewalls, but the invention is not limited thereto. In another embodiment, a dry etching process may be performed first, followed by a wet etching process or the like. In the present embodiment, the liner layer 120 and the lower half 112b of the fin structure 112 can be simultaneously formed by performing only one etching process P1. But in other In an embodiment, multiple etching processes may be performed, such as etching only the liner layer material 120' to form the liner layer 120 on the sidewall of the upper half 112a, and then etching only the exposed substrate between the upper halves 112a. 110 to form the lower half 112b of the fin structure 112. In the present embodiment, the material of the pad layer 120 is the same as that of the pad nitride layer 24, but the thickness of the pad nitride layer 24 is greater than the thickness of the pad layer 120, so that the subsequent removal of the pad layer 120 is not completely consumed. The pad nitride layer 24 is dropped and the fin structure 112 under the pad nitride layer 24 is over-etched, but the invention is not limited thereto. In other embodiments, the pad layer 120 may be made of a different material than the pad nitride layer 24, so that the two may have different etch rates relative to a particular etching gas/gas combination. With such a relative thickness of the design, it is also possible to achieve the remaining pad nitride layer 24 remaining after the full liner layer 120, and which is sufficient to avoid damage to the fin structure 112.

As shown in FIG. 4, an oxidation process P2 is performed to oxidize the exposed lower portion 112b of the fin structure 112 and the substrate 110 between the fin structures 112 to form the lower half 112b of the fin structure 112 and A dielectric layer 130 is formed in the substrate 110 between the fin structures 112. In this embodiment, the dielectric layer 130 is formed by performing the oxidation process P2, so the dielectric layer 130 is an oxide layer, and the oxidation process P2 can be, for example, a hot process or a dry oxidation heat process in which water vapor is introduced, but The invention is not limited thereto; in other embodiments, other isolation processes such as a nitridation process may be performed to form a dielectric layer 130 having other insulating materials such as a nitride layer.

Furthermore, in the non-planar field effect transistor region (first region A) of the bulk substrate of the present invention, the fin structure 112 (or when the lower half 112b of the fin structure 112 is also oxidized) For the dielectric layer 130, the upper half 112a) of the fin structure 112 and the substrate 110 are respectively sandwiched from the upper and lower dielectric layers 130, and the non-planar field effect transistor region (the first region A) remains the whole. A bulk substrate with no dielectric layer and no fin structure. In the present embodiment, the oxidation process P2 not only oxidizes the substrate 110 between the fin structures 112, but also oxidizes the lower half 112b of the fin structure 112. As such, the upper portion 112a of the fin structure 112 is a enamel structure, and the lower portion 112b is a dielectric structure that is part of the dielectric layer 130. Furthermore, the upper half 112a of the plurality of fin structures 112 are located on the dielectric layer 130, and the dielectric layer 130 is located directly below the upper half 112a of each fin structure 112 and the upper half of each fin structure 112. On the substrate 110 between the portions 112a. Therefore, the present invention can electrically insulate the fin structures 112 from the substrate 110 and electrically insulate the fin structures 112 from each other, and electrically insulate the transistor structures formed on the subsequent fin structures 112. Moreover, the dielectric layer 130 is only located in the first region A, and the substrate 110 surrounds the dielectric layer 130. Therefore, the dielectric layer 130 of the present invention is only partially formed in the first region A as the components in the first region A are electrically insulated from each other, but does not affect the components of the other regions such as the second region B.

Additionally, the liner layer 120 is located on a portion of the sidewall of the fin structure 112. In the present embodiment, the pad layer 120 is located on the upper portion 112a of the fin structure 112, so that the lower portion 112b of the fin structure 112 can be oxidized to form a portion of the dielectric layer 130 to make the fin structure 112 The formed transistor is insulated from the underlying substrate 110 to prevent leakage downward, but the invention is not limited thereto. According to the invention, the portion of the fin structure 112 that does not need to be oxidized is covered and exposed to the portion to be oxidized, and the oxidation process P2 can be combined to achieve the local oxidation effect. Furthermore, due to the fin structure of the portion not covered by the liner layer 120 112 (in the present embodiment, the lower half 112b of the fin structure 112) is oxidized, so that the bottom surface S1 of the liner layer 120 is substantially aligned with the top surface S2 of the dielectric layer 130, but the present invention does not This is limited.

Subsequently, as shown in FIG. 5, an insulating structure 140 is formed on the oxide layer 130 between (or around) the fin structures 112. In this embodiment, the insulating structure 140 is a shallow trench isolation (STI) structure, which may be formed, for example, by a shallow trench isolation (STI) process, but the invention is not limited thereto. In detail, an insulating material (not shown) may be formed on the substrate 110 to completely cover the fin structures 112 and the oxide layer 130. Then, the insulating material (not shown) is planarized to be aligned with the hard mask layer 20. Thereafter, the insulating structure 140 is formed by etching back an insulating material (not shown) to a predetermined depth d1 by, for example, a wet etching or a dry etching process. The predetermined depth d1 is set by the depth d2 of the fin structure 112 to be protruded from the insulating structure 140. The depth d2 of the fin structure 112 is such that the subsequent gate structure is spanned thereon, and a top surface S3 and two side surfaces S4 will serve as gate channels. It is noted that although the dielectric layer 130 of the present embodiment is an oxide layer, and the insulating structure 140 is a shallow trench isolation (STI) structure and is also an oxide layer, the formation methods of the two are different. Therefore, there is an interface C between the two.

Next, the exposed pad layer 120 and the pad nitride layer 24 in the hard mask 20 are removed, and as shown in FIG. 6, a portion of the pad layer 120a in the insulating structure 140 is left. Next, after the pad oxide layer 22 is removed, as shown in FIG. 7, a gate structure 150 is formed to span the fin structure 112, and a source and drain 160 (direction toward the paper surface) are further formed at the gate. The fins 112 are formed on both sides of the structure 150. Of course, an epitaxial structure (not shown) may be selectively formed on the fin structure 112, and then the source and the drain 160 may be formed on an epitaxial structure (not shown) or the like.

The gate structure 150 includes a stacked structure (not shown) having a gate dielectric layer and a gate conductive layer. For example, a metal gate process may include a buffer layer, a dielectric layer, a sacrificial gate layer, and a cap layer, and a pad structure 112 and a substrate 110 on the side of the stack structure. After that, the subsequent multi-gate field effect transistor process is performed. For example, a metal telluride process is performed to form a metal telluride (not shown) on the source and drain 160; a contact etch stop layer (CESL) is fully covered; and the interlayer is fully covered and planarized. Electrical layer (not shown); application of a high-k dielectric layer after gate (Gate-Last for High-K First) process, or a post-high dielectric constant dielectric layer gate (Gate -Last for High-K Last) process, performing a metal gate replacement process to replace the sacrificial gate layer with a metal gate; forming a metal plug in the interlayer dielectric layer (not shown) Wait. Such multi-gate field effect transistor processes are well known in the art and will not be described again.

In the present embodiment, the hard mask layer 120 is completely removed, so that a three-gate tri-gate MOSFET can be formed in a subsequent process. In detail, since the fin structure 112 has three direct contact faces (including two contact sides and a contact top surface) between the subsequently formed gate dielectric layers, it is called a three-gate field effect transistor (tri) -gate MOSFET). Compared to a planar field effect transistor, a three-gate field effect transistor can be used by The three direct contact surfaces serve as channels for the carrier to circulate, and have a wider carrier channel width at the same gate length, so that a doubled drain drive current can be obtained at the same driving voltage.

However, in another embodiment, the hard mask layer 120 may also be retained, and another multi-gate MOSFET-fin field effect transistor having a fin structure is formed in a subsequent process. (fin field effect transistor, Fin FET). In the fin field effect transistor, since the hard mask layer 120 is left, there are only two contact sides between the fin structure 112 and the gate dielectric layer to be formed later.

FIG. 8 is a schematic cross-sectional view showing a process of a multi-gate field effect transistor according to a second embodiment of the present invention. The process before the second embodiment is the same as the first to fourth embodiments of the first embodiment. In other words, the second embodiment to the method of forming the dielectric layer 130 are the same as the first embodiment. Then, the second embodiment completely removes the liner layer 120, as shown in Fig. 8, directly exposing the fin structure 112. Then, an insulating structure (not shown) such as shallow trench isolation (STI) can be selectively formed. Since the dielectric layer 130 has completely electrically insulated the fin structures 112, it is determined whether the insulating structure needs to be formed across the thickness of the gate structure disposed on the fin structure 112 (not shown). The depth of the dielectric layer 130 between the fin structures 112 and the insulating structure (not shown) to be formed. Thereafter, another multi-gate field effect transistor process such as forming a gate structure is performed, which is similar to the first embodiment, and therefore will not be described again.

Figure 9 is a cross-sectional view showing the process of a multi-gate field effect transistor according to a third embodiment of the present invention. Schematic diagram. The process before the third embodiment is the same as that of the first embodiment 1-3. In other words, the third embodiment to the formation of the liner layer 120 and the method of etching down to expose the lower half 112b of the fin structure 112 are the same as in the first embodiment. Then, as shown in FIG. 9, an oxidation process P3 is performed, and a dielectric layer 230 is formed in the lower portion 112b of the fin structure 112 and the substrate 110 between the fin structures 112. It is emphasized herein that the dielectric layer 230 in the lower half 112b of the fin structure 112 and the dielectric layer 230 in the substrate 110 between the fin structures 112 of the present embodiment have been merged to form a Bulk dielectric layer. When the depth of the lower half 112b of the fin structure 112 is short, the thickness of the pad layer 120 (as shown in FIG. 3) is thicker, or the oxygen content of the oxidation process P3 is high, etc., it may be located. The dielectric layer 230 of the lower half 112b of the fin structure 112 and the dielectric layer 230 in the substrate 110 between the fin structures 112 are combined to form a bulk dielectric layer which is more prominent than the first embodiment. On the substrate 110 between the fin structures 112. At this time, the bulk dielectric layer may have a phenomenon of the recess D between the fin structures 112.

Then, the liner layer 120 can be completely removed to directly expose the fin structure 112; and then, an insulating structure (not shown) is selectively formed. Alternatively, an insulating structure (not shown) is first formed and then the liner layer 120 exposing the insulating structure (not shown) is removed. Or, it is not necessary to form an additional insulating structure, but the dielectric layer 230 serves as insulation between the fin structure 112 and the substrate and between the fin structure 112 and the fin structure 112. Because the dielectric layer 230 has completely electrically insulated the fin structures 112, it is possible to determine whether or not to form an insulating structure (not shown) by using the depth of the gate structure that is actually intended to be spanned over the fin structure 112. On the dielectric layer 230 between the fin structures 112, and the desired shape The depth of the insulating structure (not shown). Thereafter, another multi-gate field effect transistor process such as forming a gate structure is performed, which is similar to the first embodiment, and therefore will not be described again.

10-11 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a fourth embodiment of the present invention. The process before the fourth embodiment is the same as that of the first embodiment 1-2. In other words, the fourth embodiment to the method of forming the spacer layer material 120' to completely cover the upper half 112a of the fin structure 112, the substrate 110, and the hard mask layer 20 are the same as those of the first embodiment. Next, the portion of the liner layer material 120' on the hard mask layer 20 and the portion on the substrate 110 between the fin structures 112 are removed by, for example, etching or the like, as shown in FIG. Patterned liner layer material 120b. Then, as shown in FIG. 11, an oxidation process P4 is performed to form a dielectric layer 330 under the fin structure 112 and in the substrate 110 between the fin structures 112. Although the patterned liner layer material 120b of this embodiment covers only the sidewalls of the fin structure 112, the oxidation may extend laterally from the exposed substrate 110 below the fin structure 112. In this way, the function of insulating the fin structures 112 can also be achieved.

Then, the patterned liner layer material 120b can be completely removed to directly expose the fin structure 112; and then, an insulating structure (not shown) is selectively formed. Alternatively, an insulating structure (not shown) is first formed and then the patterned liner layer material 120b exposing the insulating structure (not shown) is removed. Since the dielectric layer 330 has completely electrically insulated the fin structures 112, it is possible to determine whether an insulating structure (not shown) needs to be formed by the depth of the gate structure actually disposed on the fin structure 112. The depth of the dielectric layer 330 between the fin structures 112 and the insulating structure (not shown) to be formed. After that, then Other multi-gate field effect transistor processes, such as forming a gate structure, are performed, which are similar to the first embodiment and will not be described again.

In addition, in the first embodiment, the second embodiment, and the third embodiment, a secondary etching process is required to form the liner layer 120 and expose the lower half 112b of the fin structure 112. That is, in the above method, the upper half 112a of the fin structure 112 is formed by an etching process (as shown in FIG. 1); the pad layer material 120' is entirely covered (as shown in FIG. 2); an etching process is performed. P1, the spacer layer 120 is formed on the sidewall of the upper half 112a of each fin structure 112 and simultaneously exposes the lower half 112b of the fin structure 112 (as shown in FIG. 3). Another embodiment is presented below to form the liner layer 120 and expose the lower half 112b of the fin structure 112.

12-14 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to another embodiment of the present invention. First, as shown in Fig. 12, etching is performed once to form the fin structure 112, which includes an upper half 112a and a lower half 112b. Then, as shown in FIG. 13, a filler material 10 such as an ultraviolet light absorbing oxide (DUO) material, an advanced patterning film (APF) or a photoresist is filled and exposed. The upper half 112a of the fin structure 112 is taken out. Then, as shown in Fig. 14, the spacer layer 120 is formed to cover the upper half 112a of the fin structure 112. In a preferred embodiment, the liner layer 120 is formed by a chemical vapor deposition (CVD) process, and the process temperature of the chemical vapor deposition process is below 300 ° C to avoid ultraviolet light absorption. Ultraviolet light absorbing oxide (DUO) material, advanced patterned film layer (Advanced Patterning) Film, APF) or organic matter contamination process machines such as photoresist. Then, the filling material 10 is removed to obtain the structure as shown in Fig. 3, and then the subsequent process steps of the present invention can be continued.

In summary, the present invention provides a multi-gate field effect transistor and a process thereof, which first form a liner layer on a sidewall of a partial fin structure, and then a fin structure and fins not covered by the liner layer. The substrate between the structures is oxidized to form an oxide layer beneath or in the lower half of each fin structure and between the fin structures. The present invention provides four embodiments, which may respectively form an oxide layer having a slight difference, or a bulk oxide layer, etc., but the invention is not limited thereto, and may be applied in combination with actual needs. In this way, the fin structures can be electrically insulated from each other and the fin structures can be electrically insulated from each other by partially completely oxidizing the lower or lower half of each fin structure and the substrate between the fin structures. The purpose of electrical insulation further electrically insulates the transistors formed on the fin structures from each other and prevents each of the transistors from leaking down to the substrate.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Filling materials

20‧‧‧hard mask layer

22‧‧‧Mat oxide layer

24‧‧‧Material Nitride

110‧‧‧Base

112‧‧‧Fin structure

112a‧‧‧ upper half

112b‧‧‧ lower half

120, 120a‧‧‧ liner

120b‧‧‧ patterned cushioning material

120'‧‧‧ liner material

130, 230, 330‧‧‧ dielectric layer

140‧‧‧Insulation structure

150‧‧‧ gate structure

160‧‧‧Source and bungee

A‧‧‧First District

B‧‧‧Second District

C‧‧ interface

D‧‧‧ dent

D1‧‧‧depth

D2‧‧ depth

P1‧‧‧ etching process

P2, P3, P4‧‧‧ oxidation process

S1‧‧‧ bottom

S2, S3‧‧‧ top surface

S4‧‧‧ side

1-7 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a first embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a process of a multi-gate field effect transistor according to a second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a process of a multi-gate field effect transistor according to a third embodiment of the present invention.

10-11 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to a fourth embodiment of the present invention.

12-14 are schematic cross-sectional views showing a process of a multi-gate field effect transistor according to another embodiment of the present invention.

20‧‧‧hard mask layer

22‧‧‧Mat oxide layer

24‧‧‧Material Nitride

110‧‧‧Base

112‧‧‧Fin structure

112a‧‧‧ upper half

112b‧‧‧ lower half

120‧‧‧ liner

130‧‧‧Dielectric layer

A‧‧‧First District

B‧‧‧Second District

P2‧‧‧ oxidation process

S1‧‧‧ bottom

S2‧‧‧ top surface

Claims (18)

A multi-gate field effect transistor comprising: a substrate having a first region and a second region; a dielectric layer located only in the substrate in the first region; and at least one fin structure is located in the substrate The electrical layer, wherein the fin structure has an upper half and a lower half, the upper half comprising a enamel structure, the lower half comprising a dielectric structure. The multi-gate field effect transistor according to claim 1, wherein the dielectric layer is located between the fin structure and the substrate, and the fin structure and the substrate are respectively sandwiched from the upper and lower sides. Electrical layer. The multi-gate field effect transistor according to claim 1, further comprising a plurality of the fin structures on the dielectric layer, wherein the dielectric layer is directly under the fin structure and the fin In the base between the structures. The multi-gate field effect transistor of claim 1, wherein the substrate surrounds the dielectric layer. The multi-gate field effect transistor of claim 1, further comprising a liner layer on a portion of the sidewall of the fin structure. The multi-gate field effect transistor according to claim 5, wherein the liner layer The bottom surface is substantially aligned with the top surface of the dielectric layer. The multi-gate field effect transistor according to claim 1, further comprising an insulating structure on the dielectric layer around the fin structure. The multi-gate field effect transistor of claim 7, wherein the insulating structure has an interface with the oxide layer. The multi-gate field effect transistor according to claim 1, further comprising a gate structure spanning the fin structure, and dividing the fin structure into a source and a drain are located at the gate Both sides of the pole structure. A multi-gate field effect transistor process includes: forming at least one fin structure in a substrate and a liner layer on a sidewall of an upper half of the fin structure and exposing the lower half of the fin structure And performing an oxidation process, oxidizing the exposed lower half and a portion of the substrate around the fin structure to form a dielectric layer, wherein the dielectric layer comprises a dielectric oxidized by the lower half The structure protrudes from the dielectric layer around the fin structure. The multi-gate field-effect transistor process of claim 10, wherein the step of forming the fin structure and forming the liner layer comprises: forming a patterned hard mask layer on the substrate; Performing an etching process to form the upper half of the fin structure; Fully covering a spacer layer material on the upper half of the fin structure and the substrate; and performing at least one etching process to remove a portion of the liner layer material and a portion of the substrate to form the liner layer and form the fin The lower half of the structure. The multi-gate field effect transistor process of claim 11, wherein the liner layer and the patterned hard mask layer comprise a nitride layer, and the patterned hard mask nitrogen The thickness of the layer is greater than the thickness of the liner layer. The multi-gate field effect transistor process of claim 10, wherein after performing the oxidation process, further comprising: removing at least a portion of the liner layer. The multi-gate field effect transistor process of claim 10, wherein the oxidation process comprises a thermal process of introducing water vapor. The multi-gate field effect transistor process of claim 10, wherein the oxidizing process comprises oxidizing the exposed lower half to the lower half of each fin structure and oxidizing The substrate between the fin structures forms a piece of dielectric layer. The multi-gate field effect transistor process as described in claim 10 of the patent application, after forming the oxide layer, further comprises: An insulating structure is formed on the oxide layer around the fin structure. The multi-gate field-effect transistor process of claim 16, wherein the step of forming the insulating structure comprises: forming an insulating material over the fin structure and the oxide layer; planarizing the insulating material; And etching back the insulating material. The multi-gate field-effect transistor process of claim 10, wherein after performing the oxidation process, further comprising: forming a gate structure, spanning the fin structure; and forming a source and a The drain is located in the fin structure on both sides of the gate structure.