TWI551041B - An operational amplifier circuit with DC offset cancellation technique - Google Patents

Description

Operational amplifier circuit with DC offset cancellation technology

The present invention relates to an operational amplifier circuit, and more particularly to an operational amplifier circuit having a DC offset cancellation technique.

Conventional operational amplifiers have a mismatch between the transistors of the differential input stage due to process variations in the production process, so that each operational amplifier after mass production has a different DC offset. This DC offset will be detrimental to the application of the op amp in high precision or high specification applications. A conventional DC offset is eliminated by adjusting an external component (such as a variable resistor) to compensate for the offset of each operational amplifier. However, such an approach requires not only increasing the external pin of the operational amplifier. Therefore, the cost of the package is increased, and the use is also lacking in convenience.

Accordingly, it is an object of the present invention to provide an operational amplifier circuit having a DC offset cancellation technique that compensates for and eliminates the DC offset by control of an internal circuit.

Therefore, the operational amplifier circuit of the present invention having the DC offset cancellation technique includes an operational amplifier and an offset voltage compensator. The operational amplifier includes an inverting input, a first non-inverting input receiving a first input voltage, and an output current associated with the first input voltage The output of the voltage, when the inverting input terminal and the first non-inverting input terminal do not match, the common mode voltage between the inverting input terminal and the first non-inverting input terminal will have an offset voltage . The offset voltage compensator is electrically connected between the inverting input terminal of the operational amplifier, the first non-inverting input terminal and the output terminal, and copies the offset voltage to obtain a same offset voltage The voltage is pre-stored and the output voltage is compensated based on the pre-stored voltage.

The effect of the invention is that the offset voltage is copied by the offset voltage compensator to obtain a pre-stored voltage identical to the offset voltage, and the output voltage is compensated according to the pre-stored voltage, thereby eliminating the DC of the operational amplifier Offset voltage.

1‧‧‧Operational Amplifier

2‧‧‧Offset voltage compensator

21‧‧‧ Energy storage unit

211‧‧‧ first end

212‧‧‧ second end

213‧‧‧ third end

22‧‧‧Switch unit

23‧‧‧Control unit

C1‧‧‧first capacitor

C2‧‧‧second capacitor

M1‧‧‧first transistor

M2‧‧‧second transistor

IS1‧‧‧ first current source

IS2‧‧‧second current source

Vin1‧‧‧ first input voltage

Vin2‧‧‧ second input voltage

Vout‧‧‧ output voltage

VDD‧‧‧First bias source

VSS‧‧‧second bias source

S1‧‧‧ first switch

S2‧‧‧ second switch

S3‧‧‧ third switch

S4‧‧‧fourth switch

S5‧‧‧ fifth switch

Other features and effects of the present invention will be apparent from the following description of the drawings. FIG. 1 is a circuit diagram illustrating a first embodiment of an operational amplifier circuit having a DC offset cancellation technique of the present invention. 2 is a circuit diagram illustrating the first embodiment operating in a buffer mode; FIG. 3 is a circuit diagram illustrating the first embodiment operating in a storage mode; FIG. 4 is a circuit diagram illustrating the first The embodiment is operated in an elimination mode; FIG. 5 is a circuit diagram illustrating a second embodiment of the operational amplification circuit with DC offset cancellation technology of the present invention; FIG. 6 is a circuit diagram illustrating one of the second embodiments Change implementation FIG. 7 is a circuit diagram illustrating the second embodiment operating in a storage mode; FIG. 8 is a circuit diagram illustrating the second embodiment operating in a cancellation mode; FIG. 9 is a circuit diagram illustrating the present invention. A third embodiment of an operational amplifier circuit having a DC offset cancellation technique; and FIG. 10 is a circuit diagram illustrating a variant embodiment of the third embodiment.

Referring to FIG. 1, a first embodiment of an operational amplifier circuit having a DC offset cancellation technique of the present invention includes an operational amplifier 1 and an offset voltage compensator 2.

The operational amplifier 1 includes an inverting input terminal (-), a first non-inverting input terminal (+) receiving a first input voltage Vin1, and a second non-inverting input terminal receiving a second input voltage Vin2. (+), and an output terminal for output voltage Vout associated with the first and second input voltages Vin1, Vin2. The operational amplifier 1 used in the first embodiment has the first and second input voltages by designing the aspect ratio of the transistors corresponding to the first and second non-inverting input terminals of the input stage. Vin1 and Vin2 are added according to their respective weighting values to obtain an input voltage Vin, which is described by a weighting value of 1:3 (but not limited thereto), and Vin is as shown in the formula (1):

When the inverting input terminal does not match the first and second non-inverting input terminals, there is an offset between the inverting input terminal and the common mode voltage between the first and second non-inverting input terminals. Dc offset voltage.

The offset voltage compensator 2 is electrically connected to the inverting input terminal of the operational amplifier 1, the first non-inverting input terminal, the second non-inverting input terminal, and the output terminal, and copies the offset The voltage is shifted to obtain a pre-stored voltage identical to the offset voltage, and the output voltage Vout is compensated according to the pre-stored voltage.

The offset voltage compensator 2 includes an energy storage unit 21, a switching unit 22, and a control unit 23.

The energy storage unit 21 has a first end 211 electrically connected to the inverting input end of the operational amplifier 1, a second end 212, and a third end 213 for storing the pre-stored voltage. The energy storage unit 21 further has a first capacitor C1 electrically connected between the first end 211 and the second end 212, and a second capacitor electrically connected between the first end 211 and the third end 213. C2. The capacitance of the second capacitor C2 of the first embodiment is three times the capacitance of the first capacitor C1. However, the ratio of these capacitance values is not limited to this.

The switching unit 22 is electrically connected to the energy storage unit 21 and controlled by the control unit 23, so that the second end 212 of the energy storage unit 21 is floatingly and electrically connected to the first non-inverting input terminal or the output terminal, and The third end 213 of the energy storage unit 21 is floated and electrically connected to the second non-inverting input terminal or the output terminal. The switching unit 22 has an electrical connection between the first end 211 of the energy storage unit 21 and the output end and is controlled to switch between conduction and non-conduction. The first switch S1 is electrically connected to the second switch 213 of the energy storage unit 21 and the second non-inverting input terminal and is electrically connected to the second switch S2 controlled to switch between conduction and non-conduction. a third switch S3 between the second end 212 of the energy storage unit 21 and the first non-inverting input terminal and controlled by switching between conduction and non-conduction, and a third electrically connected to the energy storage unit 21 a fourth switch S4 between the terminal 213 and the output terminal and controlled between the conduction and the non-conduction, and an electrical connection between the second end 212 of the energy storage unit 21 and the output terminal and controlled to be conductive The fifth switch S5 is switched between non-conductions.

The control unit 23 is electrically connected to the first to fifth switches S1 to S5 of the switching unit 22, and operates in a buffer mode, a storage mode, and a cancellation mode.

Referring to FIG. 2, when the control unit 23 operates in the buffer mode, the control unit 23 controls the first switch S1 to be conductive, the second switch S2 to be non-conductive, and the third switch S3 to be non-conductive, the fourth The switch S4 is non-conductive, and the fifth switch S5 is non-conductive. Therefore, the output voltage Vout is as shown in the formula (2), wherein the parameter Voff is the value of the offset voltage.

Vout=Vin+Voff...(2)

Referring to FIG. 3, when the control unit 23 is operated in the storage mode, the control unit 23 controls the first switch S1 to be turned on, the second switch S2 to be turned on, the third switch S3 to be turned on, and the fourth switch S4. It is non-conductive, and the fifth switch S5 is non-conductive. Therefore, the charge Q1 stored in the first capacitor C1 and the charge Q2 stored in the second capacitor C2 are respectively represented by the formulas (3) and (4): Q1=C1×[(Vin+Voff)-Vin1]...(3)

Q2=C2×[(Vin+Voff)-Vin2]...(4)

Referring to FIG. 4, when the control unit 23 operates in the cancellation mode, the control unit 23 controls the first switch S1 to be non-conductive, the second switch S2 to be non-conductive, and the third switch S3 to be non-conductive. The four switches S4 are turned on, and the fifth switch S5 is turned on. Therefore, the first capacitor C1 and the second capacitor C2 are in a parallel electrical connection state and the corresponding one-end voltage Vtotal is as shown in the formula (5): Then, the output terminal generates a new output voltage Vout_new as shown in the formula (6): Vout_new=Vin+Voff-Vtotal...(6) combined with the equations (3)~(5), Combining formula (1), formula (6) and formula (7), That is to say, after the cancellation mode is completed, the output voltage Vout_new of the output terminal is the same as the input voltage Vin without being affected by the offset voltage Voff.

Referring to FIG. 5, a second embodiment of an operational amplifier circuit having a DC offset cancellation technique of the present invention is substantially the same as the first embodiment, and is not The energy storage unit 21 of the second embodiment further has a first transistor M1, a first current source IS1, a second transistor M2, and a second current source IS2. The control unit 23 of the second embodiment is electrically connected to the first to fifth switches S1 S S5 of the switching unit 22 and operates in a storage mode and an elimination mode.

The first transistor M1 has a first end electrically connected to a first bias source VDD, a second end, and a control end electrically connected to the third switch S3. The first current source IS1 is electrically connected between the second end of the first transistor M1 and a second bias source VSS, and the potential of the second bias source VSS is lower than the potential of the first bias source VDD. The second transistor M2 has a first end electrically connected to the first bias source VDD, a second end, and a control end electrically connected to the second switch S2. The second current source IS2 is electrically connected between the second end of the second transistor M2 and the second bias source VSS.

In the second embodiment, the first transistor M1 and the second transistor M2 are respectively an N-type metal oxide semi-transistor (NMOS), and the first end thereof is a drain and the second end thereof is a source. The pole, and its control end is the gate. The first and second transistors M1 and M2 form a first and second source followers with the first and second current sources IS1 and IS2, respectively. In the second embodiment, the first and second transistors M1 and M2 are respectively an N-type metal oxide semi-transistor (NMOS). The first and second transistors M1 are required to be noted. M2 can also be a P-type metal oxide semiconductor (PMOS) as shown in FIG.

Referring to FIG. 7, when the control unit 23 operates in the storage mode, the control unit 23 controls the first switch S1 to be turned on, and the second switch is turned on. The off S2 is turned on, the third switch S3 is turned on, the fourth switch S4 is turned off, and the fifth switch S5 is turned off. Therefore, the output voltage Vout is as shown in the formula (9): Vout=Vin+Voff...(9)

Referring to FIG. 8, when the control unit 23 is operated in the cancellation mode, the control unit 23 controls the first switch S1 to be non-conductive, the second switch S2 to be non-conductive, and the third switch S3 to be non-conductive. The four switches S4 are turned on, and the fifth switch S5 is turned on. Defining the voltage increments generated by the gate voltages of the first and second transistors M1 and M2 from the storage mode to the cancellation mode is ΔVg1, -ΔVg2, respectively, and the new output voltage corresponding to the output terminal Vout_new is as shown in the formula (10): Vout_new=Vin1+ΔVg1=Vin2-ΔVg2 (10) and the source voltage increments of the first and second transistors M1 and M2 are as shown in equations (11) and (12, respectively. ): △Vs1=△Vg1×Gsf1...(11)

ΔVs2=−ΔVg2×Gsf2 (12) where Gsf1 and Gsf2 are voltage gains between the source and the gate of the first and second source followers, respectively. Since the inverting input terminal of the operational amplifier 1 has no charge and discharge path in the cancellation mode, it is conserved in charge as shown in the equation (13): C1 × ΔVg1 × Gsf1 - C2 × ΔVg2 × Gsf2 = 0... (13) Furthermore, since the voltage gain between the source and the gate of the source follower is approximately equal to 1, Equation (13) can be approximated as shown in Equation (14): C1 × ΔVg1 = C2 ×ΔVg2 (14) can be obtained by combining formula (1), formula (10) and formula (14). That is to say, after the cancellation mode is completed, the output voltage Vout_new of the output terminal is the same as the input voltage Vin without being affected by the offset voltage Voff.

It is to be noted that, in comparison with the first embodiment, the second embodiment is electrically connected to the first and second capacitors C1 and C2 and the third and second switches S3 and S2, respectively. a second source follower, such that the terminal voltages of the first and second capacitors C1 and C2 are increased by Vgs1 and Vgs2, respectively, when the second embodiment operates in the storage mode, wherein Vgs1 and Vgs2 are gate and source voltages of the first and second transistors M1 and M2, respectively. The terminal voltage increments Vgs1 and Vgs2 of the capacitors are particularly suitable for the first input voltage Vin1 to be close to the second input voltage Vin2, and the first and second capacitors C1 and C2 are MOS-cap capacitors. Operating conditions. It is claimed that when the first and second input voltages Vin1 and Vin2 are close, the terminal voltages of the first and second capacitors C1 and C2 are respectively expressed by equations (16) and (17): VC1=(Vin+ Voff)-(Vin1-Vgs1) Voff+Vgs1...(16)

VC2=(Vin+Voff)-(Vin2-Vgs2) Voff+Vgs2 (17) thus enables the gold-oxide half-capacitors to have a sufficient terminal voltage to operate normally, and utilizes a gold-oxide half-capacitor having a large capacitance per unit area to reduce the wafer area.

Referring to FIG. 9 and FIG. 10, a third embodiment of the operational amplifier circuit having the DC offset cancellation technique of the present invention is substantially identical in operation to the second embodiment, except that the operation of the third embodiment is The amplifier 1 includes a first non-inverting input terminal, the energy storage unit 21 has a first capacitor C1, a first transistor M1, and a first current source IS1, and the switching unit 22 has a first switch S1. a third switch S3 and a fifth switch S5. The control unit 23 is electrically connected to the first, third and fifth switches S1, S3, S5 of the switching unit 22 and operates in a storage mode and an elimination mode.

Through the above description, the above embodiment has the following advantages:

1. The offset voltage compensator 2 copies the offset voltage to obtain a pre-stored voltage identical to the offset voltage, and compensates the output voltage Vout according to the pre-stored voltage, thereby eliminating the DC offset of the operational amplifier 1. Shift voltage.

2. The switches of the switching unit 22 are controlled by the control unit 23, so that the energy storage unit 21 utilizes its capacitance in the storage mode to store the pre-stored voltage, and compensates the output voltage in the cancellation mode. Vout also eliminates the DC offset voltage of the operational amplifier 1.

3. The voltage value of the output voltage Vout is determined by the ratio of the capacitance values of the first and second capacitors C1 and C2 of the energy storage unit 21, and the stability of the voltage value can be improved. Further, since the capacitors are passive components, the process variability is superior to the active components, and since the two capacitors in the same wafer have a dynamic relationship in process or temperature change, The proportion between people is less susceptible The effect of process or temperature changes. Therefore, the output voltage Vout determined by the ratio of the capacitance values of the first and second capacitors C1 and C2 is likewise less affected by the process or temperature change.

4. The output voltage Vout is determined by the ratio of the capacitance values of the first and second capacitors C1 and C2 so as not to be affected by the conductance (gm) variation of the input stage of the operational amplifier 1, so that even if it is operated Under the condition that the first and second input voltages Vin1 and Vin2 have a large voltage difference, the output voltage Vout can be stably maintained at the design value without being affected by the output voltage Vout.

5. The first and second source followers formed by the first and second transistors M1 and M2 and the first and second current sources IS1 and IS2 are the first and second capacitors C1, respectively. The terminal voltage increments Vgs1 and Vgs2 provided by C2 enable the first and second capacitors C1 and C2 to be implemented by a gold oxide half capacitor having a large capacitance per unit area, thereby reducing the wafer area.

In summary, the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.

1‧‧‧Operational Amplifier

2‧‧‧Offset voltage compensator

21‧‧‧ Energy storage unit

211‧‧‧ first end

212‧‧‧ second end

213‧‧‧ third end

22‧‧‧Switch unit

23‧‧‧Control unit

C1‧‧‧first capacitor

C2‧‧‧second capacitor

Vin1‧‧‧ first input voltage

Vin2‧‧‧ second input voltage

Vout‧‧‧ output voltage

S1‧‧‧ first switch

S2‧‧‧ second switch

S3‧‧‧ third switch

S4‧‧‧fourth switch

S5‧‧‧ fifth switch

Claims (6)

An operational amplifier circuit with DC offset cancellation technology, comprising: an operational amplifier comprising an inverting input, a first non-inverting input receiving a first input voltage, and a receiving second input voltage a non-inverting input terminal, and an output terminal for providing an output voltage associated with the first and second input voltages, when the inverting input terminal does not match the first and second non-inverting input terminals An offset voltage exists between the inverting input terminal and the common mode voltage between the first and second non-inverting input terminals; and an offset voltage compensator electrically connected to the inverting input terminal of the operational amplifier Between the first non-inverting input terminal, the second non-inverting input terminal and the output terminal, and copying the offset voltage to obtain a pre-stored voltage identical to the offset voltage, and compensating according to the pre-stored voltage The output voltage, the offset voltage compensator includes an energy storage unit and a switching unit, the energy storage unit is configured to store the pre-stored voltage, and has a first end electrically connected to the inverting input end of the operational amplifier Second end, one a first capacitor electrically connected between the first end and the second end, and a second capacitor electrically connected between the first end and the third end, the switching unit electrically connecting the energy storage unit And controlling, the second end of the energy storage unit is floated, electrically connected to the first non-inverting input terminal or the output end, and the third end of the energy storage unit is floated and electrically connected to the second non- The switching unit has: a first switch electrically connected between the first end and the output end of the energy storage unit, and controlled to switch between conduction and non-conduction, a second switch electrically connected between the third end of the energy storage unit and the second non-inverting input terminal, and controlled to switch between conduction and non-conduction, and a third switch electrically connected to the energy storage The second end of the unit and the first non-inverting input end are controlled to switch between conduction and non-conduction, and a fourth switch is electrically connected between the third end of the energy storage unit and the output end And being controlled to switch between conduction and non-conduction, and a fifth switch electrically connected between the second end of the energy storage unit and the output end, and controlled to switch between conduction and non-conduction. The operational amplifier circuit of claim 1, wherein the offset voltage compensator further comprises: a control unit electrically connected to the first to fifth switches of the switching unit, and operating on the first a buffer mode, a storage mode, and an erasing mode, when the control unit operates in the buffer mode, the control unit controls the first switch to be conductive, the second switch to be non-conductive, and the third switch to be non-conductive, The fourth switch is non-conducting, and the fifth switch is non-conducting; when the control unit is operated in the storage mode, the control unit controls the first switch to be conductive, the second switch to be conductive, and the third switch is Turning on, the fourth switch is non-conducting, and the fifth switch is non-conducting; and when the control unit is operated in the cancel mode, the control unit controls the first switch to be non-conducting, and the second switch is non-conducting The third The switch is non-conductive, the fourth switch is conductive, and the fifth switch is conductive. The operational amplifier circuit of claim 1, wherein the energy storage unit further comprises: a first transistor having a first end electrically connected to a first bias source, and a first a second end, and an electrical connection to the control end of the third switch; a first current source electrically connected between the second end of the first transistor and a second bias source, the potential of the second bias source a second transistor having a first end, a second end electrically connected to the first bias source, and a control end electrically connected to the second switch; and a second current source electrically connected between the second end of the second transistor and the second bias source. The operational amplifier circuit of claim 3, wherein the offset voltage compensator further comprises: a control unit electrically connected to the first to fifth switches of the switching unit, and operating on the first a storage mode and a cancellation mode, when the control unit is operated in the storage mode, the control unit controls the first switch to be conductive, the second switch to be conductive, the third switch to be conductive, and the fourth switch to be non-conductive And the fifth switch is non-conducting; and when the control unit is operated in the cancellation mode, the control unit controls the first switch to be non-conducting, the second switch to be non-conducting, and the third switch to be non-conducting, The fourth switch is conductive, and the fifth switch is conductive through. An operational amplifier circuit having a DC offset cancellation technique, comprising: an operational amplifier comprising an inverting input terminal, a first non-inverting input terminal receiving a first input voltage, and a first one associated with the first An output terminal of the output voltage of the input voltage, when the inverting input terminal and the first non-inverting input terminal do not match, a common mode voltage between the inverting input terminal and the first non-inverting input terminal will exist An offset voltage compensator electrically connected between the inverting input terminal of the operational amplifier, the first non-inverting input terminal and the output terminal, and replicating the offset voltage to obtain a The pre-stored voltage is the same as the offset voltage, and the output voltage is compensated according to the pre-stored voltage. The offset voltage compensator includes an energy storage unit and a switching unit, and the energy storage unit is configured to store the pre-stored voltage and has a Electrically connecting the first end and the second end of the inverting input end of the operational amplifier, the switching unit is electrically connected to the energy storage unit, and is controlled to float and electrically connect the second end of the energy storage unit Non-inverting And the output end, and the switching unit has: a first switch electrically connected between the first end and the output end of the energy storage unit, and controlled to switch between conduction and non-conduction, a third switch Electrically connected between the second end of the energy storage unit and the first non-inverting input terminal, and controlled to switch between conduction and non-conduction, and a fifth switch electrically connected to the energy storage unit The second end is connected to the output end, and is controlled to switch between conduction and non-conduction; and the energy storage unit further has: a first transistor having a first end electrically connected to a first bias source, a second end, and a control end electrically connected to the third switch, a first current source electrically connected to the first Between the second end of the transistor and a second bias source, the potential of the second bias source is less than the potential of the first bias source, and a first capacitor is electrically connected to the first end and the first The second end of the transistor. The operational amplifier circuit of claim 5, wherein the offset voltage compensator further comprises: a control unit electrically connecting the first switch, the third switch and the fifth switch of the switching unit And operating in a storage mode and an elimination mode, when the control unit operates in the storage mode, the control unit controls the first switch to be conductive, the third switch to be conductive, and the fifth switch to be non-conductive; And when the control unit is operated in the cancellation mode, the control unit controls the first switch to be non-conductive, the third switch to be non-conductive, and the fifth switch to be conductive.