TWI550804B - Chip package structuer - Google Patents

Description

Chip package structure

The present invention relates to a package structure, and more particularly to a chip package structure.

At present, in order to meet the characteristics of different package structures, a variety of different packaging technologies have been developed. One of the well-developed packaging technologies is chip scale package (CSP) technology. This wafer-level packaging technology reduces the size of the package structure to a size slightly larger than the original wafer size.

For example, the package structure of the image sensing chip is disposed on the image sensing wafer, and the image sensing wafer and the transparent substrate are usually joined to each other through a bonding layer. In addition, the pads or other circuit layers in the image sensing chip are usually guided to the back side of the image sensing chip through the reconfiguration circuit layer to facilitate signal reading of the image sensing chip. The pads or other circuit layers in the sensing wafer will simultaneously withstand the stress from the reconfigured wiring layer underneath and the bonding layer above it, so that pads or other wiring layers in the image sensing wafer may appear due to stress. The bumping and damage (causing an open circuit) causes the signal of the image sensing chip to be unreadable, and the package yield of the image sensing chip cannot be effectively improved.

The present invention provides a wafer package structure that reduces the chance of damage to the wafer from stress.

A chip package structure of the present invention includes a wafer, a light transmissive substrate and a bonding layer. The wafer has an opposite active surface and a back surface and includes a plurality of pads. The active surface includes a sensing area and a peripheral area surrounding the sensing area, and the pad is located in the peripheral area. The light transmissive substrate is disposed on the active surface of the wafer. The bonding layer is located between the peripheral region of the wafer and the transparent substrate, and includes a plurality of coverage regions and a plurality of stress relief holes, wherein the coverage region covers the pads, and at least a portion of the stress relief holes surround at least three of the corresponding coverage regions side.

In an embodiment of the invention, each of the stress relief holes has a rectangular shape with a guide angle.

In an embodiment of the invention, the length of one side of each of the pads is A, the length of one long side of the stress relief hole beside the projection pad is B, and the length of the long side of the stress relief hole is B. The ratio to the length A of the sides of the pads is between 0.5 and 0.9.

In an embodiment of the invention, the length of the other side of each of the pads is A2, and the length of a short side of the stress relief hole projected to the side of the pad is B2, and the short side of the stress relief hole The ratio of the length B2 to the length A2 of this other side of the pad is between 0.2 and 0.5.

In an embodiment of the invention, a short side of each of the stress relief holes The length is not less than 20 μm.

In an embodiment of the invention, the ratio of the total area of the stress relief holes located adjacent to each of the coverage areas to the area of the corresponding coverage area is not more than 0.3.

In an embodiment of the invention, the stress relief holes are distributed throughout the bonding layer.

In an embodiment of the invention, in the opposite sides of the bonding layer, the stress relief holes extend in the same direction.

In an embodiment of the invention, the bonding layer includes a separated first region and a second region, and the first region surrounds the second region.

In an embodiment of the invention, in the second region of the bonding layer, the stress relief holes on each side extend in the same direction.

In an embodiment of the invention, the bonding layer has an extending portion extending in a direction toward each other and staggered in one side of the first region corresponding to the second region.

Based on the above, the bonding layer of the wafer package structure of the present invention includes a cover portion covering the pad, the bonding layer further having a stress relief hole beside the cover portion, at least a portion of the stress relief hole surrounding at least three sides of the corresponding cover portion, The stress between the bonding layer and the peripheral region of the wafer is released, thereby reducing the probability of the pad being damaged by the tensile stress. In addition, since the size of the stress relief hole relative to the cover is within a certain range, the bonding layer of the chip package structure can still maintain a sufficient bonding effect.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

A1, A2, B1, B2, C1, C2‧‧‧ length

100‧‧‧ Chip package structure

120‧‧‧ wafer

121‧‧‧Re-distribution layer

122‧‧‧Active surface

123‧‧‧through through crystal perforation

124, 224, 324‧‧ Sensing area

125‧‧‧Interconnection layer

125a‧‧‧ dielectric layer

125b‧‧‧ circuit layer

126‧‧‧ surrounding area

128‧‧‧Back

129‧‧‧ pads

130‧‧‧Transparent substrate

140, 240, 340, 440‧‧‧ joint layers

141, 241‧‧ Coverage area

142, 242, 342, 442‧‧‧ stress relief holes

142a‧‧‧Longside

142b‧‧‧ Short side

150‧‧‧ solder balls

344, 444‧‧‧ first district

346, 446‧‧‧ second district

444a, 446a‧‧‧ extensions

1 is a cross-sectional view of a wafer package structure in accordance with an embodiment of the present invention.

2 is a schematic view of a bonding layer of the wafer package structure of FIG. 1.

Fig. 3 is a partially enlarged schematic view of Fig. 2;

4 is a schematic diagram of a bonding layer of a wafer package structure in accordance with another embodiment of the present invention.

FIG. 5 is a schematic diagram of a bonding layer of a chip package structure in accordance with another embodiment of the present invention.

6 is a schematic diagram of a bonding layer of a wafer package structure in accordance with another embodiment of the present invention.

1 is a cross-sectional view of a wafer package structure in accordance with an embodiment of the present invention. Referring to FIG. 1 , the chip package structure 100 of the present embodiment includes a wafer 120 , a transparent substrate 130 , a bonding layer 140 , and a plurality of solder balls 150 . In the present embodiment, the wafer 120 is an image sensing wafer, but the form and type of the wafer 120 are not limited thereto.

In this embodiment, the wafer 120 has an opposite active surface 122 and a Back 128. The active surface 122 includes a sensing region 124 at the center and a peripheral region 126 surrounding the sensing region 124. The wafer 120 includes a plurality of Through-Silicon Via (TSV) 123, an interconnection layer 125 connected to the through-silicon vias 123, and a plurality of pads connected to the interconnect layer 125. 129 and a plurality of reconfiguration line layers (RDL) 121 connected to the through-silicon vias 123 and located on the back side 128.

As shown in FIG. 1, the interconnect layer 125 includes a stacked plurality of dielectric layers 125a and a plurality of wiring layers 125b. The pad 129 is connected to one of the wiring layers 125b and exposed to the peripheral region 126. In the present embodiment, the material of the pad 129 is, for example, aluminum, but other suitable metals or alloys may also be used. Solder balls 150 are attached to reconfigured wiring layer 121 on back side 128 of wafer 120.

The transparent substrate 130 is disposed on the active surface 122 of the wafer 120. In the embodiment, the transparent substrate 130 may be a glass substrate, but the type of the transparent substrate 130 is not limited thereto.

The bonding layer 140 is located between the peripheral region 126 of the wafer 120 and the transparent substrate 130 to bond the wafer 120 and the transparent substrate 130. In the present embodiment, the bonding layer 140 is cured by liquid optical transparent adhesive (DAM), but the material and formation of the bonding layer 140 are not limited thereto. The bonding layer 140 includes a plurality of footprints 141. In this embodiment, the cover regions 141 are respectively covered on the pads 129 of the wafer 120, and the shape of each of the cover regions 141 is similar to the shape of the pads 129, and the size of each of the cover regions 141 may be slightly larger than that covered by the pads 141. The size of the pad 129.

2 is a schematic view of a bonding layer of the wafer package structure of FIG. 1. Figure 2 As shown, the bonding layer 140 of the present embodiment further includes a plurality of stress relief holes 142 that surround at least three sides of the footprint 141. More specifically, each of the cover regions 141 has at least three sides surrounded by the stress relief holes 142. In FIG. 2, three sides of each of the cover regions 141 are surrounded by a single elongated stress relief hole 142, but in other embodiments, in each of the three sides of each of the coverage regions 141, each side may also The shape and the number of the stress relief holes 142 on each side are not limited by the plurality of stress relief holes 142. In addition, this embodiment does not limit that each of the coverage areas 141 must have three sides surrounded by the stress relief holes 142. Specifically, when only the three sides of the partial coverage area 141 are surrounded by the stress relief holes 142, the present invention is also The scope to be covered.

Since the wafer 120 will respectively withstand the tensile stress of the re-distribution wiring layer 121 of the upper bonding layer 140 and the back surface 128, the probability of breaking the wiring inside the wafer 120 in order to reduce the stress pull of the upper and lower sides. In the present embodiment, the bonding layer 140 of the chip package structure 100 includes a cover region 141 covering the pad 129, and a plurality of stress relief holes 142 are formed in the bonding layer 140, and the stress relief holes 142 are respectively adjacent to each other. And surrounding at least three sides of the footprint 141 to relieve stress between the bonding layer 140 and the peripheral region 126 of the wafer 120. In this way, the probability that the wafer 120 is stressed by the upper bonding layer 140 and the pad 129 of the wafer 120 is raised can be reduced. It is worth mentioning that this structure is particularly suitable for wafers fabricated in a low dielectric (Low K) process with a gap between pads 129 of less than 100 μm.

It should be noted that, in general, due to the distance between the pad 129 and the edge of the wafer 120 (that is, in FIG. 2, the pad 129 on the right and the right of the wafer 120) The distance between the edges is relatively close (between about 10 μm and 20 μm), and therefore, the bonding layer 140 does not have enough space in the region corresponding to the pad 129 between the edge of the wafer 120 to configure the stress relief hole 142, stress release The holes 142 are only disposed on the other three sides of the pads 129. However, in other embodiments, if there is sufficient distance and space between the pad 129 and the edge of the wafer 120, the bonding layer 140 may also be provided with a stress relief hole 142 in a region corresponding to the pad 129 between the edge of the wafer 120, so that The projection of the stress relief holes 142 on the back side 128 of the wafer 120 can surround the periphery of the pads 129.

Fig. 3 is a partially enlarged schematic view of Fig. 2; As shown in FIG. 3, in the present embodiment, each of the stress relief holes 142 has a rectangular shape with a guide angle to have a better effect of reducing stress concentration. Of course, in other embodiments, the shape of the stress relief hole 142 may also be other suitable shapes such as a circular shape, an elliptical shape, and the like, and is not limited thereto.

In actual manufacture, the size of the stress relief hole 142 can be limited to a certain range. In detail, if the size of the stress relief hole 142 is too small, it may be difficult in the process (for example, poor development of yellow light), or the bonding layer 140 may be squeezed during the bonding of the transparent substrate 130 and the wafer 120. The stress relief hole 142 disappears or a significant stress release effect does not occur. Therefore, in the present embodiment, the length of one short side 142b of each stress relief hole 142 is not less than 20 μm. On the other hand, if the size of the stress relief hole 142 is too large, it is compressed to the space actually occupied by the bonding layer 140, and the bonding strength between the wafer 120 and the light-transmitting substrate 130 is lowered. Therefore, the total area occupied by the stress relief holes 142 beside each of the pads 129 The ratio of the area to the bonding layer 140 is preferably not more than 0.3 (i.e., 30%).

Further, as shown in FIG. 3, in the present embodiment, if one of the sides of each of the coverage areas 141 has a length of A1 and the other side has a length of A2. For the stress relief hole 142 located beside the cover region 141, in FIG. 3, the length of the long side 142a of the stress relief hole 142 located above is B1, and the length of the short side 142b of the stress relief hole 142 is B2. Then, the ratio of the length B1 of the long side 142a of the stress relief hole 142 above the drawing surface to the length A1 of the corresponding side of the cover area 141 is between 0.5 and 0.9, and the length B2 of the short side 142b of the stress relief hole 142 The ratio to the length A2 of the other side of the footprint 141 is between 0.2 and 0.5.

Similarly, the length of the long side 142a of the left stress relief hole 142 is C1, and the length of the short side 142b of the stress relief hole 142 is C2, and the long side 142a of the left stress relief hole 142 of the drawing. The ratio of the length C1 to the length A2 of the corresponding side on the cover 141 is between 0.5 and 0.9, and the ratio of the length C2 of the short side 142b of the stress relief hole 142 to the length A1 of the other side of the cover 141 is 0.2. Between 0.5 and 0.5.

In the present embodiment, by defining the size of the stress relief hole 142 to be within a certain range, the bonding layer 140 can provide both a sufficient bonding effect and an effect of releasing stress between the wafer 120 and the wafer 120.

4 is a schematic diagram of a bonding layer of a wafer package structure in accordance with another embodiment of the present invention. Referring to FIG. 4, likewise, the projection of the sensing region 224 on the plane in which the bonding layer 240 is located is surrounded by the bonding layer 240. The main difference between the bonding layer 240 of the present embodiment and the bonding layer 140 of the previous embodiment is that, in the previous embodiment, The stress relief holes 142 of the bonding layer 140 are located only on three sides of the cover region 141. In the present embodiment, the stress relief holes 242 are distributed at other positions of the bonding layer 240 in addition to the position corresponding to the area surrounding the cover region 241, that is, the stress relief holes 242 are spread over the entire circumference of the bonding layer. 240. Further, in the present embodiment, the long sides of the stress relief holes 242 in the opposite sides of the bonding layer 240 (in the upper and lower sides of the bonding layer 240 in FIG. 4) extend in the same direction.

FIG. 5 is a schematic diagram of a bonding layer of a chip package structure in accordance with another embodiment of the present invention. Referring to FIG. 5, the main difference between the bonding layer 340 of the present embodiment and the bonding layer 240 of the previous embodiment is that the bonding layer 340 of FIG. 5 includes a separated first region 344 and a second region 346, the first region. The 344 surrounds the second region 346, and the projection of the sensing region 324 on the plane in which the bonding layer 340 is located is surrounded by the first region 344 and the second region 346, respectively.

In the present embodiment, the stress relief holes 342 are elongated, and in the second region 346 of the bonding layer 340, the long sides of the stress relief holes 342 located on the respective sides extend in the same direction. The long sides of the stress relief holes 342 on the opposite sides of the second region 346 of the bonding layer 340 all extend in the same direction. Also, in the adjacent two sides of the second region 346 of the bonding layer 340, the extending direction of the long sides of the stress relief holes 342 is perpendicular. More specifically, the long sides of the stress relief holes 342 on the upper and lower sides of the second region 346 of the bonding layer 340 of FIG. 5 are extended in the up and down direction, and the stress release on the left and right sides of the second region 346 of the bonding layer 340 of FIG. The long side of the hole 342 extends in the left-right direction.

6 is a schematic diagram of a bonding layer of a wafer package structure in accordance with another embodiment of the present invention. Referring to FIG. 6 , the stress relief hole 442 is spread over the bonding layer 440 . The first zone 444 is in the second zone 446. The main difference between the bonding layer 440 of the present embodiment and the bonding layer 340 of the previous embodiment is that the bonding layer 440 has a direction toward each other in one side of the first region 444 corresponding to the second region 446, respectively. Staggered extensions 444a, 446a.

In detail, the bonding layer 440 has an upwardly extending portion 444a on the side below the plane of the first region 444, and the bonding layer 440 has a downwardly extending portion 446a on the side below the plane of the second region 446. The extension 444a of the first zone 444 and the extension 446a of the second zone 446 are arranged in an intersecting and staggered manner.

In summary, the bonding layer of the chip package structure of the present invention comprises a covering portion covering the pads, the shape and size of each of the covering regions is substantially equal to the shape and size of the covered pads, and the bonding layer also has a beside the covering portion. The stress relief holes, at least a portion of the stress relief holes surround at least three sides of the corresponding cover portions to relieve stress between the bonding layer and the peripheral region of the wafer, and reduce the probability of the pads being damaged by the tensile stress ridges. In addition, since the size of the stress relief hole relative to the cover is within a certain range, the bonding layer of the chip package structure can still maintain a sufficient bonding effect.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ Chip package structure

120‧‧‧ wafer

121‧‧‧Re-distribution layer

122‧‧‧Active surface

123‧‧‧Through through silicon perforation (TSV)

124‧‧‧Sensing area

125‧‧‧Interconnection layer

125a‧‧‧ dielectric layer

125b‧‧‧ circuit layer

126‧‧‧ surrounding area

128‧‧‧Back

129‧‧‧ pads

130‧‧‧Transparent substrate

140‧‧‧Connection layer

141‧‧ Coverage area

142‧‧‧ stress relief hole

150‧‧‧ solder balls

Claims (9)

A chip package structure includes: a wafer having an opposite active surface and a back surface, and including a plurality of pads, wherein the active surface includes a sensing area and a peripheral area surrounding the sensing area, and the connections a pad is disposed in the peripheral region; a transparent substrate disposed on the active surface of the wafer; and a bonding layer between the peripheral region of the wafer and the transparent substrate, and including a plurality of coverage regions and a plurality of a stress relief hole, wherein the coverage areas respectively cover the pads, and at least a portion of the stress relief holes surround at least three sides of the corresponding coverage areas, wherein each of the stress relief holes has a shape with a lead angle rectangle. The chip package structure of claim 1, wherein a length of one side of each of the pads is A1, and a length of a long side of the stress relief hole projected to the side of the pad is B1. The ratio of the length B1 of the long side of the stress relief hole to the length A1 of the side of the pad is between 0.5 and 0.9. The chip package structure of claim 2, wherein the other side of each of the pads has a length A2, and a short side of the stress relief hole projected to the side of the pad has a length B2. The ratio of the length B2 of the short side of the stress relief hole to the length A2 of the other side of the pad is between 0.2 and 0.5. The wafer package structure according to claim 1, wherein a length of each short side of each of the stress relief holes is not less than 20 μm. The chip package structure of claim 1, wherein a total area of the stress relief holes located adjacent to each of the coverage areas and a corresponding face of the coverage area The ratio of the product is not more than 0.3. The wafer package structure of claim 1, wherein the stress relief holes are distributed throughout the bonding layer, and the stress relief holes extend in the same direction in opposite sides of the bonding layer. The wafer package structure of claim 1, wherein the bonding layer comprises a separated first region and a second region, and the first region surrounds the second region. The wafer package structure of claim 7, wherein in the second region of the bonding layer, the stress relief holes on each side extend in the same direction. The wafer package structure according to claim 7, wherein the bonding layer has an extending portion extending in a direction toward each other and staggered in a side of one side of the first region corresponding to the second region.