TWI550783B - Fabrication method of electronic package and electronic package structure - Google Patents
Fabrication method of electronic package and electronic package structure Download PDFInfo
- Publication number
- TWI550783B TWI550783B TW104113206A TW104113206A TWI550783B TW I550783 B TWI550783 B TW I550783B TW 104113206 A TW104113206 A TW 104113206A TW 104113206 A TW104113206 A TW 104113206A TW I550783 B TWI550783 B TW I550783B
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- Prior art keywords
- layer
- electronic component
- electronic package
- electronic
- bonding layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims description 29
- 238000005538 encapsulation Methods 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 107
- 239000004065 semiconductor Substances 0.000 description 19
- 238000006073 displacement reaction Methods 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- JHJNPOSPVGRIAN-SFHVURJKSA-N n-[3-[(1s)-1-[[6-(3,4-dimethoxyphenyl)pyrazin-2-yl]amino]ethyl]phenyl]-5-methylpyridine-3-carboxamide Chemical compound C1=C(OC)C(OC)=CC=C1C1=CN=CC(N[C@@H](C)C=2C=C(NC(=O)C=3C=C(C)C=NC=3)C=CC=2)=N1 JHJNPOSPVGRIAN-SFHVURJKSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係有關一種電子封裝件，尤指一種可防止電子元件偏移的電子封裝件及其製法。 The present invention relates to an electronic package, and more particularly to an electronic package capable of preventing offset of electronic components and a method of manufacturing the same.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements for semiconductor package miniaturization, Wafer Level Packaging (WLP) technology was developed.
如第1A至1D圖，係為習知晶圓級半導體封裝件1之製法之剖面示意圖。 1A to 1D are schematic cross-sectional views showing the fabrication of a conventional wafer level semiconductor package 1.
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載件10上。 As shown in FIG. 1A, a thermal release tape 11 is formed on a carrier 10.
接著，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之作用面12a與非作用面12b，各該作用面12a上均具有複數電極墊120，且各該作用面12a黏著於該熱化離型膠層11上。 Next, a plurality of semiconductor elements 12 are disposed on the thermal release layer 11, the semiconductor elements 12 having opposite active and non-active surfaces 12a, each of which has a plurality of electrode pads 120, and Each of the active surfaces 12a is adhered to the thermal release adhesive layer 11.
如第1B圖所示，以模壓(molding)方式形成一封裝膠體13於該熱化離型膠層11上，以包覆該半導體元件12。 As shown in FIG. 1B, an encapsulant 13 is formed on the thermal release adhesive layer 11 by a molding method to coat the semiconductor element 12.
如第1C圖所示，進行烘烤製程以硬化該封裝膠體13，而同時該熱化離型膠層11因受熱後會失去黏性，故可一併移除該熱化離型膠層11與該承載件10，以外露該半導體元件12之作用面12a。 As shown in FIG. 1C, the baking process is performed to harden the encapsulant 13, and at the same time, the thermal release adhesive layer 11 loses viscosity after being heated, so the thermal release adhesive layer 11 can be removed together. With the carrier 10, the active surface 12a of the semiconductor element 12 is exposed.
如第1D圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，係形成一線路重佈結構14於該封裝膠體13與該半導體元件12之作用面12a上，令該線路重佈結構14電性連接該半導體元件12之電極墊120。 As shown in FIG. 1D, a redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the encapsulating body 13 and the active surface 12a of the semiconductor component 12, so that the line is redistributed. The structure 14 is electrically connected to the electrode pad 120 of the semiconductor component 12.
接著，形成一絕緣保護層15於該線路重佈結構14上，且該絕緣保護層15外露該線路重佈結構14之部分表面，以供結合如銲球之導電元件16。 Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder balls.
惟，習知半導體封裝件1之製法中，該熱化離型膠層11具有撓性，且因其熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)之影響，故當溫度產生變化時，使設置於該承載件10上之該熱化離型膠層11多處發生伸縮現象而彼此之間互相推擠，致使位移量累積，而影響該半導體元件12固定之精度，亦即容易使半導體元件12產生偏移，致使該半導體元件12未置於該熱化離型膠層11之預定位置上，且當該承載件10移除後會造成該封裝膠體13翹曲(warpage)過大。 However, in the manufacturing method of the conventional semiconductor package 1, the thermal release adhesive layer 11 has flexibility, and due to the influence of its coefficient of thermal expansion (CTE), when the temperature changes, the setting is made. The plurality of thermalizing release layers 11 on the carrier 10 are stretched and protruded from each other, causing the displacement amount to accumulate, thereby affecting the accuracy of fixing the semiconductor element 12, that is, the semiconductor element 12 is easily formed. An offset is generated such that the semiconductor component 12 is not placed at a predetermined position of the thermal release adhesive layer 11, and when the carrier 10 is removed, the package colloid 13 is excessively warpaged.
故而，該線路重佈結構14與該半導體元件12之電極墊120間的對位將產生偏移，當該承載件10之尺寸越大時，各該半導體元件12間之位置公差亦隨之加大，而當偏移公差過大時，將使該線路重佈結構14無法與該電極墊 120連接，亦即對該線路重佈結構14與該半導體元件12間之電性連接造成極大影響，因而造成良率過低及產品可靠度不佳等問題。 Therefore, the alignment between the line redistribution structure 14 and the electrode pads 120 of the semiconductor component 12 will be offset. When the size of the carrier 10 is larger, the positional tolerance between the semiconductor components 12 is also increased. Large, and when the offset tolerance is too large, the line redistribution structure 14 will not be able to interact with the electrode pad The 120 connection, that is, the electrical connection between the line redistribution structure 14 and the semiconductor component 12 is greatly affected, thereby causing problems such as low yield and poor product reliability.
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝結構，係包括：一承載件，其包含有一基板、形成於該基板上並具有至少一開口之定位層、及覆蓋該基板與定位層之結合層，以令該開口與該基板形成凹部；至少一電子元件，係設於該凹部中；封裝層，係包覆該電子元件；以及線路重佈層，係形成於該封裝層上並電性連接該電子元件。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electronic package structure comprising: a carrier comprising a substrate, a positioning layer formed on the substrate and having at least one opening, and covering the substrate and positioning a bonding layer of the layer such that the opening forms a recess with the substrate; at least one electronic component is disposed in the recess; the encapsulation layer encapsulates the electronic component; and a circuit redistribution layer is formed on the encapsulation layer And electrically connecting the electronic component.
前述之電子封裝結構中，該電子元件係凸伸出該凹部。 In the aforementioned electronic package structure, the electronic component protrudes from the recess.
前述之電子封裝結構中，該封裝層係具有相對之第一表面及第二表面，且該電子元件外露於該第一表面。 In the above electronic package structure, the encapsulation layer has opposite first and second surfaces, and the electronic component is exposed on the first surface.
前述之電子封裝結構中，該線路重佈層係由複數線路層及介電層依序相疊而成，且該些線路層係電性連接該電子元件。 In the above electronic package structure, the circuit redistribution layer is formed by sequentially stacking a plurality of circuit layers and a dielectric layer, and the circuit layers are electrically connected to the electronic component.
前述之電子封裝結構中，復包括導電元件，係電性連接該線路重佈層。 In the foregoing electronic package structure, the conductive element is further included to electrically connect the circuit redistribution layer.
本發明復提供一種電子封裝件之製法，係包括：提供一承載件，其中，該承載件係包括有一基板、形成於該基板上並具有開口之定位層、及覆蓋該基板與定位層之結合 層，以令該開口與該基板形成凹部；置放至少一電子元件於該凹部中之結合層上；形成封裝層於該結合層上，以令該封裝層包覆該電子元件；形成線路重佈層於該封裝層上，並與該電子元件電性連接；以及移除該承載件。 The invention provides a method for manufacturing an electronic package, comprising: providing a carrier, wherein the carrier comprises a substrate, a positioning layer formed on the substrate and having an opening, and a combination of the substrate and the positioning layer a layer such that the opening forms a recess with the substrate; placing at least one electronic component on the bonding layer in the recess; forming an encapsulation layer on the bonding layer to encapsulate the electronic component; forming a line weight The layer is layered on the encapsulation layer and electrically connected to the electronic component; and the carrier is removed.
前述之製法中，該定位層係先形成於該基板上，再以圖案化製程形成該開口。 In the above method, the positioning layer is first formed on the substrate, and the opening is formed by a patterning process.
前述之製法中，該定位層係為一具有該開口之架體，以架設於該基板上。 In the above method, the positioning layer is a frame having the opening to be mounted on the substrate.
前述之製法中，該電子元件凸伸出該凹部。 In the above method, the electronic component protrudes from the recess.
前述之製法中，該封裝層具有相對之第一表面及第二表面，且該電子元件外露於該第一表面。 In the above method, the encapsulation layer has opposite first and second surfaces, and the electronic component is exposed on the first surface.
前述之製法中，以蝕刻或剝除方式移除該基板。 In the above method, the substrate is removed by etching or stripping.
前述之製法中，藉由研磨或切除製程，移除該定位層與該結合層，且一併移除該封裝層之部分材質及該電子元件之部分材質。 In the above method, the positioning layer and the bonding layer are removed by a grinding or cutting process, and part of the material of the encapsulating layer and a part of the material of the electronic component are removed.
前述之結構及製法中，該承載件復包括有形成於該基板上之另一結合層，且該定位層及該結合層係形成於該另一結合層上。 In the foregoing structure and method, the carrier further includes another bonding layer formed on the substrate, and the positioning layer and the bonding layer are formed on the other bonding layer.
前述之結構及製法中，該電子元件為多晶片模組。 In the foregoing structure and method, the electronic component is a multi-chip module.
由上可知，本發明之電子封裝件之製法及電子封裝結構中，係藉由多種不同材質形成具有凹部之承載件，使每一凹部中具有各自的位移空間，故於製程中，當該結合層發生形變時，每一凹部中的結合層可各自形變，而不會影響周圍之凹部中的結合層，因而能降低形變位移量之累 積，以減少該電子元件的位移量。因此，於後續RDL製程與切單製程中，可提升該電子元件的定位精準度，以提升產品良率及可靠度。 It can be seen from the above that in the manufacturing method and the electronic package structure of the electronic package of the present invention, the carrier having the concave portion is formed by a plurality of different materials, so that each recess has a respective displacement space, so in the process, when the combination When the layer is deformed, the bonding layers in each concave portion can be deformed individually without affecting the bonding layer in the surrounding concave portion, thereby reducing the deformation displacement amount. Product to reduce the amount of displacement of the electronic component. Therefore, in the subsequent RDL process and the singulation process, the positioning accuracy of the electronic component can be improved to improve product yield and reliability.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10、20‧‧‧承載件 10, 20‧‧‧ Carrying parts
11‧‧‧熱化離型膠層 11‧‧‧heating release layer
12‧‧‧半導體元件 12‧‧‧Semiconductor components
12a、21a‧‧‧作用面 12a, 21a‧‧‧ action surface
12b、21b‧‧‧非作用面 12b, 21b‧‧‧ non-active surface
120、210‧‧‧電極墊 120, 210‧‧‧ electrode pads
13‧‧‧封裝膠體 13‧‧‧Package colloid
14、23‧‧‧線路重佈結構 14, 23 ‧ ‧ line redistribution structure
15、232‧‧‧絕緣保護層 15, 232‧‧‧Insulating protective layer
16、24‧‧‧導電元件 16, 24‧‧‧ conductive components
2、2’‧‧‧電子封裝件 2, 2'‧‧‧ electronic package
2a‧‧‧電子封裝結構 2a‧‧‧Electronic package structure
200‧‧‧凹部 200‧‧‧ recess
201‧‧‧基板 201‧‧‧Substrate
202‧‧‧第一結合層 202‧‧‧First bonding layer
203‧‧‧定位層 203‧‧‧Positioning layer
2030‧‧‧開口 2030‧‧‧ openings
204‧‧‧第二結合層 204‧‧‧Second bonding layer
21、21’‧‧‧電子元件 21, 21'‧‧‧ Electronic components
212‧‧‧結合材 212‧‧‧Combined materials
212a、212b‧‧‧晶片 212a, 212b‧‧‧ wafer
22‧‧‧封裝層 22‧‧‧Encapsulation layer
22a‧‧‧第一表面 22a‧‧‧ first surface
22b‧‧‧第二表面 22b‧‧‧ second surface
230‧‧‧介電層 230‧‧‧ dielectric layer
231‧‧‧線路層 231‧‧‧Line layer
2320‧‧‧開孔 2320‧‧‧Opening
W1、W2‧‧‧寬度 W1, W2‧‧‧ width
S‧‧‧切割路徑 S‧‧‧ cutting path
第1A至1D圖係為習知半導體封裝件之剖面示意圖；以及第2A至2H圖係本發明之電子封裝件之製法之剖面示意圖；其中，第2B’圖係第2B圖之另一實施例，第2H’圖係第2H圖之另一實施例。 1A to 1D are schematic cross-sectional views of a conventional semiconductor package; and 2A to 2H are schematic cross-sectional views showing a method of manufacturing the electronic package of the present invention; wherein, 2B' is another embodiment of FIG. 2B The 2H' diagram is another embodiment of the 2Hth diagram.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“一”、“第一”及“第二”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "one", "first" and "second" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.
第2A至2H圖係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。 2A to 2H are schematic cross-sectional views showing a first embodiment of the manufacturing method of the electronic package 2 of the present invention.
如第2A圖所示，提供一具有複數凹部200之承載件20。 As shown in FIG. 2A, a carrier 20 having a plurality of recesses 200 is provided.
於本實施例中，該承載件20係包括一基板201、形成於該基板201上之第一結合層202、形成於該第一結合層202上之定位層203、及覆蓋該第一結合層202與定位層203之第二結合層204。 In this embodiment, the carrier 20 includes a substrate 201, a first bonding layer 202 formed on the substrate 201, a positioning layer 203 formed on the first bonding layer 202, and a first bonding layer. 202 and a second bonding layer 204 of the alignment layer 203.
具體地，該基板201係為絕緣材、矽、玻璃或金屬，且該第一結合層202之材質可為氧化矽(SiO2)或氮化矽(SixNy)，而該定位層203之材質可為聚苯並噁唑(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、苯基環丁烯(benzocyclobutane，簡稱BCB)、或感光型光阻等感光材料。 Specifically, the substrate 201 is made of an insulating material, germanium, glass or metal, and the material of the first bonding layer 202 may be cerium oxide (SiO 2 ) or tantalum nitride (Si x N y ), and the positioning layer 203 The material may be a polybenzoxazole (PBO), a polyimide (PI), a benzocyclobutane (BCB), or a photosensitive photoresist.
該定位層203可透過例如塗佈(coating)之方式先形成於該第一結合層202上，再圖案化該定位層203以形成複數開口2030；或者，該定位層203為預先形成有複數開口2030之架體(Frame)，再設於該第一結合層202上，之後塗佈該第二結合層204，其中，該架體之材質可例如為金屬或塑膠，並無特別限制。 The positioning layer 203 can be formed on the first bonding layer 202 by, for example, coating, and then the positioning layer 203 is patterned to form a plurality of openings 2030. Alternatively, the positioning layer 203 is formed with a plurality of openings in advance. The frame of the 2030 is further disposed on the first bonding layer 202, and then the second bonding layer 204 is coated. The material of the frame may be metal or plastic, for example, and is not particularly limited.
又，該第二結合層204係如晶片絕緣膜(die attach film，簡稱DAF)；或者，該第二結合層204亦可以塗膠方式形成。具體地，該第二結合層204係形成於該些開口2030中以覆蓋該第一結合層202，使該第二結合層204對應該 些開口2030而形成該些凹部200，其中，該些凹部200截面寬度W1係小於該些開口2030之截面寬度W2。 Moreover, the second bonding layer 204 is, for example, a die attach film (DAF); or the second bonding layer 204 may be formed by a glue coating method. Specifically, the second bonding layer 204 is formed in the openings 2030 to cover the first bonding layer 202, so that the second bonding layer 204 corresponds to The recesses 200 are formed by the openings 2030, wherein the cross-sectional width W1 of the recesses 200 is smaller than the cross-sectional width W2 of the openings 2030.
如第2B圖所示，置放複數電子元件21於該些凹部200中。 As shown in FIG. 2B, a plurality of electronic components 21 are placed in the recesses 200.
於本實施例中，各該電子元件21係具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊210，且各該電子元件21藉由該非作用面21b而結合至該第二結合層204上，並使各該電子元件21凸伸出該些凹部200。 In this embodiment, each of the electronic components 21 has an opposite active surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads 210, and each of the electronic components 21 is coupled to the non-active surface 21b. The second bonding layer 204 is disposed on the electronic component 21 and protrudes from the recesses 200.
另外，該開口2030或該凹部200與該電子元件21之數量亦可為一個。 In addition, the number of the opening 2030 or the recess 200 and the electronic component 21 may also be one.
再者，該些電子元件21係可為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於此，該些電子元件21係為如單一晶片結構之主動元件，且得於其中一凹部200中係置放至少一之電子元件21。於本實施例中係以單一凹部200中置放數量為二之電子元件21為例，但不限於此。 Furthermore, the electronic components 21 can be active components, passive components or a combination thereof, and the active components are, for example, semiconductor wafers, and the passive components are, for example, resistors, capacitors, and inductors. Herein, the electronic components 21 are active components such as a single wafer structure, and at least one of the electronic components 21 is disposed in one of the recesses 200. In the present embodiment, the number of the electronic components 21 disposed in the single recess 200 is exemplified, but is not limited thereto.
於其它實施例中，如第2B’圖所示，該電子元件21’亦可為如多晶片模組之主動元件，例如，先將兩晶片212a,212b以結合材212(如環氧樹脂)相結合成一模組，再將該模組置放於該凹部200中。 In other embodiments, as shown in FIG. 2B′, the electronic component 21 ′ may also be an active component such as a multi-wafer module. For example, the two wafers 212 a , 212 b are first combined with a material 212 (eg, epoxy resin). The modules are combined into a module, and the module is placed in the recess 200.
如第2C圖所示，接續第2B圖之製程，形成一封裝層22於該承載件20與該些電子元件21上。 As shown in FIG. 2C, following the process of FIG. 2B, an encapsulation layer 22 is formed on the carrier 20 and the electronic components 21.
於本實施例中，該封裝層22係填入該些凹部200中，以令該封裝層22包覆該電子元件21。 In the embodiment, the encapsulation layer 22 is filled in the recesses 200 to encapsulate the encapsulation layer 22 with the electronic component 21.
如第2D圖所示，執行研磨製程，薄化該封裝層22之厚度以定義出該封裝層22之第一表面22a，並使該些電子元件21之該些電極墊210外露於該第一表面22a，且該些電子元件21之作用面21a係齊平於該封裝層22之該第一表面22a。 As shown in FIG. 2D, the polishing process is performed, the thickness of the encapsulation layer 22 is thinned to define the first surface 22a of the encapsulation layer 22, and the electrode pads 210 of the electronic components 21 are exposed to the first surface. The surface 22a and the active surface 21a of the electronic components 21 are flush with the first surface 22a of the encapsulation layer 22.
於本實施例中，該封裝層22定義有相對該第一表面22a之第二表面22b，以結合於該第二結合層204上。 In this embodiment, the encapsulation layer 22 defines a second surface 22b opposite to the first surface 22a for bonding to the second bonding layer 204.
如第2E圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，即形成一線路重佈結構23於該封裝層22上，且該線路重佈結構23係電性連接該些電子元件21之該些電極墊210。 As shown in FIG. 2E, a Redistribution Layer (RDL) process is performed to form a line redistribution structure 23 on the package layer 22, and the line redistribution structure 23 electrically connects the electrons. The electrode pads 210 of the component 21.
於本實施例中，該線路重佈結構23係包含相疊之介電層230、線路層231及絕緣保護層232，且該絕緣保護層232形成複數開孔2320，令最外側之該線路層231之部分表面外露於各該開孔2320，以供結合如銲球之導電元件24。 In this embodiment, the circuit redistribution structure 23 includes a plurality of dielectric layers 230, a circuit layer 231, and an insulating protective layer 232, and the insulating protective layer 232 forms a plurality of openings 2320, so that the outermost layer Portions of the surface of 231 are exposed to each of the openings 2320 for bonding conductive elements 24 such as solder balls.
如第2F圖所示，以蝕刻或剝除方式，移除該基板201與該第一結合層202。 As shown in FIG. 2F, the substrate 201 and the first bonding layer 202 are removed by etching or stripping.
如第2G圖所示，執行研磨或切除製程，移除該定位層203、第二結合層204、該封裝層22之第二表面22b之部分材質及該電子元件21之非作用面21b之部分材質，以薄化該封裝層22之第二表面22b及該些電子元件21之非作用面21b。 As shown in FIG. 2G, a grinding or cutting process is performed to remove portions of the positioning layer 203, the second bonding layer 204, the second surface 22b of the encapsulation layer 22, and portions of the non-active surface 21b of the electronic component 21. The material is used to thin the second surface 22b of the encapsulation layer 22 and the non-active surface 21b of the electronic components 21.
於本實施例中，於薄化後，該封裝層22之第二表面 22b係齊平該電子元件21之非作用面21b。 In this embodiment, after thinning, the second surface of the encapsulation layer 22 22b is flushed with the non-active surface 21b of the electronic component 21.
如第2H圖所示，沿如第2G圖所示之切割路徑S進行切單製程，以形成本發明之電子封裝件2。 As shown in Fig. 2H, a singulation process is performed along the dicing path S as shown in Fig. 2G to form the electronic package 2 of the present invention.
於其它實施例中，若接續第2B’圖之製程，將得到如第2H’圖所示之電子封裝件2’。 In other embodiments, if the process of Fig. 2B' is continued, the electronic package 2' as shown in Fig. 2H' will be obtained.
本發明之製法中，藉由在該基板201上形成該具有開口2030之定位層203，以令該承載件20形成凹部200，再將該些電子元件21設於該凹部200中，故於製程中，當溫度變化而使該第二結合層204發生形變時，每一凹部200可自行提供向上延伸之空間，即該些凹部200中的第二結合層204可各自形變，而不會影響周圍之凹部200中的第二結合層204，因而能降低形變位移量之累積，以減少該電子元件21的位移量。 In the manufacturing method of the present invention, the positioning layer 203 having the opening 2030 is formed on the substrate 201, so that the carrier 20 is formed into the concave portion 200, and the electronic components 21 are disposed in the concave portion 200. When the temperature changes to change the second bonding layer 204, each recess 200 can provide an upwardly extending space, that is, the second bonding layer 204 in the recesses 200 can be deformed independently without affecting the surrounding area. The second bonding layer 204 in the recess 200 can thereby reduce the accumulation of the deformation displacement amount to reduce the displacement amount of the electronic component 21.
因此，於後續RDL製程與切單製程中，可提升該電子元件21的定位精準度，以提升產品良率及可靠度。 Therefore, in the subsequent RDL process and the singulation process, the positioning accuracy of the electronic component 21 can be improved to improve product yield and reliability.
本發明係提供一種電子封裝結構2a，如第2E圖所示，係包括：一具有複數凹部200之承載件20、設於該些凹部200中之複數電子元件21,21’、包覆該些電子元件21,21’之封裝層22、電性連接該電子元件21,21’之線路重佈結構23、以及電性連接該線路重佈結構23之導電元件24。 The present invention provides an electronic package structure 2a, as shown in FIG. 2E, comprising: a carrier 20 having a plurality of recesses 200, a plurality of electronic components 21, 21' disposed in the recesses 200, and covering the plurality of recesses 200 The encapsulation layer 22 of the electronic component 21, 21', the circuit redistribution structure 23 electrically connecting the electronic component 21, 21', and the conductive component 24 electrically connected to the circuit redistribution structure 23.
所述之承載件20係包括一基板201、形成於該基板201上之第一結合層202、形成於該第一結合層202上並具有複數開口2030之定位層203、及覆蓋該第一結合層202與定位層203之第二結合層204。 The carrier 20 includes a substrate 201, a first bonding layer 202 formed on the substrate 201, a positioning layer 203 formed on the first bonding layer 202 and having a plurality of openings 2030, and covering the first bonding Layer 202 and second bonding layer 204 of positioning layer 203.
所述之電子元件21,21’係具有相對之作用面21a及非作用面21b，該作用面21a具有複數電極墊210，且該電子元件21,21’以其非作用面21b結合於該第二結合層204上。 The electronic component 21, 21' has an opposite active surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads 210, and the electronic components 21, 21' are bonded to the first surface by the non-active surface 21b. The second bonding layer 204 is on.
所述之封裝層22係具有相對之第一表面22a及第二表面22b，該些電極墊210係外露於該第一表面22a，例如，該作用面21a係齊平於該第一表面22a。 The encapsulation layer 22 has an opposite first surface 22a and a second surface 22b. The electrode pads 210 are exposed on the first surface 22a. For example, the active surface 21a is flush with the first surface 22a.
所述之線路重佈結構23係包含相疊之介電層230、線路層231及一設於最外側之絕緣保護層232，且該絕緣保護層232形成有複數開孔2320，使最外側之部分線路層231外露於各該開孔2320，以供結合該些導電元件24。 The circuit redistribution structure 23 includes a stacked dielectric layer 230, a circuit layer 231 and an outermost insulating protective layer 232, and the insulating protective layer 232 is formed with a plurality of openings 2320, so that the outermost side A portion of the wiring layer 231 is exposed to each of the openings 2320 for bonding the conductive elements 24.
於一實施例中，各該電子元件21,21’係凸伸出該些凹部200。 In one embodiment, each of the electronic components 21, 21' protrudes from the recesses 200.
綜上所述，本發明之電子封裝件之製法及電子封裝結構中，主要藉由多種不同材質形成具有凹部之承載件，使每一凹部中具有各自的位移空間，故於製程中，當該第二結合層發生形變時，每一凹部中的第二結合層可各自形變，而不會影響周圍之凹部中的第二結合層，因而能降低形變位移量之累積，以減少該電子元件的位移量。因此，於後續RDL製程與切單製程中，可提升該電子元件的定位精準度，以提升產品良率及可靠度。 In summary, in the manufacturing method and the electronic package structure of the electronic package of the present invention, the carrier having the concave portion is formed by a plurality of different materials, so that each recess has a respective displacement space, so in the process, when When the second bonding layer is deformed, the second bonding layer in each of the concave portions may be deformed independently without affecting the second bonding layer in the surrounding concave portion, thereby reducing the accumulation of the deformation displacement amount to reduce the electronic component. The amount of displacement. Therefore, in the subsequent RDL process and the singulation process, the positioning accuracy of the electronic component can be improved to improve product yield and reliability.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. change. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2a‧‧‧電子封裝結構 2a‧‧‧Electronic package structure
20‧‧‧承載件 20‧‧‧Carrier
200‧‧‧凹部 200‧‧‧ recess
201‧‧‧基板 201‧‧‧Substrate
202‧‧‧第一結合層 202‧‧‧First bonding layer
203‧‧‧定位層 203‧‧‧Positioning layer
204‧‧‧第二結合層 204‧‧‧Second bonding layer
21‧‧‧電子元件 21‧‧‧Electronic components
210‧‧‧電極墊 210‧‧‧electrode pads
22‧‧‧封裝層 22‧‧‧Encapsulation layer
23‧‧‧線路重佈結構 23‧‧‧Line redistribution structure
230‧‧‧介電層 230‧‧‧ dielectric layer
231‧‧‧線路層 231‧‧‧Line layer
232‧‧‧絕緣保護層 232‧‧‧Insulating protective layer
2320‧‧‧開孔 2320‧‧‧Opening
24‧‧‧導電元件 24‧‧‧Conducting components
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| CN109979890A (en) * | 2017-12-28 | 2019-07-05 | 凤凰先驱股份有限公司 | Electronic packing piece and its preparation method |
| CN108922853A (en) * | 2018-07-09 | 2018-11-30 | 中国电子科技集团公司第五十八研究所 | A kind of three-dimensional structure production method based on Fan-out technique |
| TWI700796B (en) * | 2019-05-23 | 2020-08-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| TWI712135B (en) * | 2019-09-16 | 2020-12-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
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| TWI237885B (en) * | 2004-10-22 | 2005-08-11 | Phoenix Prec Technology Corp | Semiconductor device having carrier embedded with chip and method for fabricating the same |
| JP2012109297A (en) * | 2010-11-15 | 2012-06-07 | Shinko Electric Ind Co Ltd | Semiconductor package and method for manufacturing the same |
| TW201332071A (en) * | 2012-01-20 | 2013-08-01 | 矽品精密工業股份有限公司 | Carrier board, semiconductor package and method of forming same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206463B (en) | 2019-09-06 |
| CN106206463A (en) | 2016-12-07 |
| TW201639085A (en) | 2016-11-01 |
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