TWI541810B - Data writing method, and memory controller and memory storage apparatus using the same - Google Patents

Description

Data writing method, memory control circuit unit and memory storage device

The present invention relates to a data writing method for a rewritable non-volatile memory module and a memory control circuit unit and a memory storage device using the same.

Digital cameras, mobile phones and MP3s have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Because rewritable non-volatile memory has the characteristics of non-volatile data, power saving, small size, no mechanical structure, fast reading and writing speed, etc., it is most suitable for portable electronic products, such as notebook type. computer. A solid state hard disk is a storage device that uses flash memory as a storage medium. Therefore, in recent years, the flash memory industry has become a very popular part of the electronics industry.

1 is a schematic illustration of a flash memory component as depicted in the prior art.

Referring to FIG. 1, the flash memory component 1 includes a charge traping layer for storing electrons, and a control gate for applying a bias voltage (Control). Gate) 3, through the oxide layer (Tunnel Oxide) 4 and polycrystalline dielectric layer (Interpoly Dielectric) 5. When data is to be written to the flash memory device 1, the threshold voltage of the flash memory device 1 can be changed by injecting electrons into the charge trapping layer 2, thereby defining the digital high and low states of the flash memory device 1. And realize the function of storing data. Here, the process of injecting electrons into the charge trapping layer 2 is called stylization. On the other hand, when the stored data is to be removed, the flashed memory element 1 can be returned to the state before being unprogrammed by removing the injected electrons from the charge trapping layer 2.

During the writing and erasing process, the flash memory element 1 is abraded with multiple injections and removals of electrons, resulting in an increase in the electronic writing speed and a broadening of the threshold voltage distribution. Therefore, after the flash memory element 1 is programmed, its storage state cannot be correctly recognized, and an erroneous bit is generated. In particular, when the flash memory element 1 is at a high temperature, the data preserving power of the flash memory element 1 is lowered, and thus more erroneous bits are generated.

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can effectively prevent over-stylization and reduce the occurrence of erroneous bits.

An exemplary embodiment of the present invention provides a data writing method for writing data into a memory cell of a rewritable non-volatile memory module of a memory storage device. The method for writing data includes: detecting an operating temperature of the memory storage device; and determining whether the operating temperature of the memory storage device is greater than a predefined temperature. This capital The material writing method further includes adjusting at least one predefined operational parameter corresponding to the rewritable non-volatile memory module to generate a corresponding rewritable non-volatile if the operating temperature of the memory storage device is greater than a predefined temperature At least one adjusted operational parameter of the memory module and the data is written into the memory cell based on the at least one adjusted operational parameter.

In an exemplary embodiment of the present invention, the at least one predefined operational parameter of the responsive upper rewritable non-volatile memory module is configured to generate at least one adjusted operational parameter of the corresponding rewritable non-volatile memory module. And the step of writing the data into the memory cell according to the at least one adjusted operating parameter comprises: recording a wear level value of the memory cell; adjusting an initial write voltage corresponding to the memory cell according to the wear level value of the memory cell, and writing Entering at least one of a voltage pulse time and a compensation value; and programming the memory cell to write data to the memory cell using an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell.

In an exemplary embodiment of the present invention, the step of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell according to the wear level value of the memory cell includes: along with the memory cell The wear level value is increased to lower the initial write voltage of the corresponding memory cell.

In an exemplary embodiment of the present invention, the step of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell according to the wear level value of the memory cell includes: along with the memory cell The wear level value is increased to reduce the write voltage pulse time corresponding to the memory cell.

In an exemplary embodiment of the present invention, the use of the corresponding memory cell is The step of writing the write voltage, the write voltage pulse time and the compensation value to program the memory cell to write the data to the memory cell includes: using the initial write voltage, the reduced write voltage pulse time, and the above compensation value Performing at least one repetitive stylization of the memory cell; and performing other repetitive stylization of the memory cell using the initial write voltage, the write voltage pulse time, and the compensation value.

In an exemplary embodiment of the present invention, the wear level value of the memory cell is based on at least one of the number of erasures, the number of writes, the number of error bits, the proportion of error bits, and the number of readings of the memory cell. Decide.

In an exemplary embodiment of the present invention, the step of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell according to the wear level value of the memory cell includes: following the memory The value of the degree of wear of the cell is increased, and the compensation value corresponding to the memory cell is reduced.

In an exemplary embodiment of the present invention, the step of using the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell to program the memory cell to write data to the memory cell includes: using the initial Writing a voltage, a reduced write voltage pulse time, and a reduced compensation value to perform at least one reprogramming of the memory cell; and using the initial write voltage, the write voltage pulse time, and the compensation The value is used to perform other repetitive stylizations of the memory cell.

An exemplary embodiment of the present invention provides a memory control circuit unit for writing data to a memory cell of a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, a memory management circuit, and a temperature sensor. The host interface is coupled to the host system. Memory interface for coupling Connect to a rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The temperature sensor is used to detect the operating temperature of the memory storage device. The memory management circuit is configured to determine whether the operating temperature of the memory storage device is greater than a predefined temperature. If the operating temperature of the memory storage device is greater than a predefined temperature, the memory management circuit is further configured to adjust at least one predefined operational parameter corresponding to the rewritable non-volatile memory module to generate a corresponding rewritable non-volatile At least one adjusted operational parameter of the memory module and the instruction sequence is issued to the rewritable non-volatile memory module according to the at least one adjusted operational parameter to write data into the memory cell.

In an exemplary embodiment of the present invention, at least one predefined operational parameter corresponding to the rewritable non-volatile memory module is adjusted to generate at least one adjusted operation of the corresponding rewritable non-volatile memory module. And the memory management circuit records the wear level value of the memory cell according to the parameter and the instruction sequence of the at least one adjusted operation parameter is sent to the rewritable non-volatile memory module to write data into the memory cell. Adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell according to the wear level value of the memory cell, and using an initial write voltage, a write voltage pulse time corresponding to the memory cell The memory cell is programmed with a compensation value to write data to the memory cell.

In an exemplary embodiment of the present invention, in the operation of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value of the corresponding memory cell according to the wear level value of the memory cell, the memory management circuit The initial write voltage corresponding to the memory cell is decreased as the value of the wear level of the memory cell increases.

In an exemplary embodiment of the present invention, in the operation of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell according to the wear level value of the memory cell, the memory management The circuit is configured to reduce the write voltage pulse time corresponding to the memory cell as the value of the wear level of the memory cell increases.

In an exemplary embodiment of the present invention, the memory cell is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell to write data into the operation of the memory cell. The memory management circuit performs at least one repetitive programming of the memory cell using the initial write voltage, the reduced write voltage pulse time, and the compensation value, and uses the initial write voltage and the write voltage pulse The time and the above compensation value are used to perform other repetitive stylization of the memory cell.

In an exemplary embodiment of the present invention, in the operation of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value of the corresponding memory cell according to the wear level value of the memory cell, the memory management circuit It is used to reduce the compensation value of the corresponding memory cell as the value of the wear level of the memory cell increases.

In an exemplary embodiment of the present invention, the memory cell is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell to write data into the operation of the memory cell. The memory management circuit performs at least one repetitive programming of the memory cell using the initial write voltage, the write voltage pulse time, and the reduced compensation value, and uses the initial write voltage and the write voltage pulse time Other repetitive stylization of the memory cells is performed with the above compensation values.

An exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is coupled to the host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to detect an operating temperature of the memory storage device and determine whether the operating temperature of the memory storage device is greater than a predefined temperature. If the operating temperature of the memory storage device is greater than a predefined temperature, the memory control circuit unit is further configured to adjust at least one predefined operational parameter corresponding to the rewritable non-volatile memory module to generate a corresponding rewritable non-volatile At least one adjusted operational parameter of the memory module and the instruction sequence is issued to the rewritable non-volatile memory module to write data into the memory cell according to the at least one adjusted operational parameter.

In an exemplary embodiment of the present invention, the at least one predefined operational parameter corresponding to the rewritable non-volatile memory module is adjusted to generate at least one adjusted corresponding to the rewritable non-volatile memory module. Operating parameters and recording the memory state of the memory cell by the memory control circuit unit according to the at least one adjusted operating parameter issuing instruction sequence to the rewritable non-volatile memory module for writing data into the memory cell And adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value of the corresponding memory cell according to a wear level value of the memory cell, and by using an initial write voltage, a write voltage pulse time of the corresponding memory cell The memory cells are programmed with compensation values to write data to the memory cells.

In an exemplary embodiment of the present invention, the initial write voltage, the write voltage pulse time, and the complement of the corresponding memory cell are adjusted according to the wear level value of the memory cell. In operation of at least one of the compensation values, the memory control circuit unit is configured to decrease the initial write voltage of the corresponding memory cell as the value of the wear level of the memory cell increases.

In an exemplary embodiment of the present invention, in the operation of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value of the corresponding memory cell according to the wear level value of the memory cell, the memory control circuit The unit is configured to reduce the write voltage pulse time of the corresponding memory cell as the value of the wear level of the memory cell increases.

In an exemplary embodiment of the present invention, the memory cell is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell to write data into the memory cell, and the memory The body control circuit unit performs at least one repetitive programming of the memory cell using the initial write voltage, the reduced write voltage pulse time, and the compensation value, and uses the initial write voltage, the write voltage pulse time, and the above The compensation value is used to perform other repetitive stylization of the memory cell.

In an exemplary embodiment of the present invention, in the operation of adjusting at least one of an initial write voltage, a write voltage pulse time, and a compensation value of the corresponding memory cell according to the wear level value of the memory cell, the memory control circuit The unit is used to reduce the compensation value of the corresponding memory cell as the value of the wear level of the memory cell increases.

In an exemplary embodiment of the present invention, the memory cell is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell to write data into the memory cell, and the memory The body control circuit unit performs at least one repetitive programming of the memory cell using the initial write voltage, the write voltage pulse time, and the reduced compensation value, and uses the initial write voltage, The write voltage pulse time and the above compensation value are used to perform other repetitive stylization of the memory cell.

Based on the above, the data writing method, the memory control circuit unit, and the memory storage device according to the exemplary embodiments of the present invention can adjust the electrons injected into the memory cells according to the wear of the memory cells, thereby correctly writing the data to the memory cells. in.

The above described features and advantages of the invention will be apparent from the following description.

1‧‧‧Flash memory components

2‧‧‧Charging layer

3‧‧‧Control gate

4‧‧‧through oxide layer

5‧‧‧Polysilicon dielectric layer

S1001, S1003, S1005, S1007‧‧‧ steps of data writing method

1000‧‧‧Host system

1100‧‧‧ computer

1102‧‧‧Microprocessor

1104‧‧‧ Random access memory

1106‧‧‧Input/output devices

1108‧‧‧System Bus

1110‧‧‧Data transmission interface

1202‧‧‧ Mouse

1204‧‧‧ keyboard

1206‧‧‧ display

1208‧‧‧Printer

1212‧‧‧USB flash drive

1214‧‧‧ memory card

1216‧‧‧ Solid State Drive

1310‧‧‧ digital camera

1312‧‧‧SD card

1314‧‧‧MMC card

1316‧‧‧ Memory Stick

1318‧‧‧CF card

1320‧‧‧Embedded storage device

100‧‧‧ memory storage device

102‧‧‧Connecting interface unit

104‧‧‧Memory Control Circuit Unit

106‧‧‧Reusable non-volatile memory module

2202‧‧‧ memory cell array

2204‧‧‧Word line control circuit

2206‧‧‧ bit line control circuit

2208‧‧‧ row decoder

2210‧‧‧Data input/output buffer

2212‧‧‧Control circuit

VA‧‧‧first threshold voltage

VB‧‧‧second threshold voltage

VC‧‧‧ third threshold voltage

VD‧‧‧fourth threshold voltage

VE‧‧‧ fifth threshold voltage

VF‧‧‧ sixth threshold voltage

VG‧‧‧ seventh threshold voltage

202‧‧‧Memory Management Circuit

204‧‧‧Host interface

206‧‧‧ memory interface

208‧‧‧temperature sensor

252‧‧‧ Buffer memory

254‧‧‧Power Management Circuit

256‧‧‧Error checking and correction circuit

S1201, S1203, S1205, S1207, S1209, S1211‧‧‧ steps of data writing method

S1301, S1303, S1305, S1307, S1309‧‧‧ steps to adjust the initial write voltage

Steps of S1701, S1703, S1705, S1707, S1709, S1711‧‧‧ data writing method

S1801, S1803, S1805, S1807, S1809‧‧‧ Adjust the write voltage pulse Time step

Steps of S1901, S1903, S1905, S1907, S1909, S1911‧‧‧ data writing method

S2101, S2103, S2105, S2107, S2109, S2111‧‧‧ steps of data writing method

S2201, S2203, S2205, S2207, S2209‧‧‧ steps to adjust the compensation value

1 is a schematic illustration of a flash memory component as depicted in the prior art.

2 is a flow chart of a method for writing data according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram of a host system and a memory storage device according to a first exemplary embodiment.

4 is a schematic diagram of a computer, an input/output device, and a memory storage device according to an exemplary embodiment.

FIG. 5 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment.

FIG. 6 is a schematic block diagram of a memory storage device according to a first exemplary embodiment.

FIG. 7 is a rewritable non-volatile memory according to a first exemplary embodiment. A schematic block diagram of the body module.

FIG. 8 is a statistical distribution diagram of gate voltages corresponding to write data stored in a memory cell array according to a first exemplary embodiment.

FIG. 9 is a schematic diagram of a stylized memory cell according to a first exemplary embodiment.

FIG. 10 is a schematic diagram of verifying a storage state of a memory cell according to the first exemplary embodiment.

FIG. 11 is a schematic diagram of verifying a storage state of a memory cell according to another exemplary embodiment.

FIG. 12 is a schematic block diagram of a memory control circuit unit according to a first exemplary embodiment.

FIG. 13 is a flowchart of a data writing method according to a first exemplary embodiment of the present invention.

FIG. 14 is a flow chart of adjusting an initial write voltage of a corresponding memory cell according to the first exemplary embodiment.

15-17 are schematic diagrams of stylized memory cells according to a second exemplary embodiment.

FIG. 18 is a schematic diagram of a stylized memory cell according to another exemplary embodiment.

FIG. 19 is a flowchart of a data writing method according to a second exemplary embodiment of the present invention.

FIG. 20 is a diagram of adjusting the corresponding memory cell according to the second exemplary embodiment. Flow chart of the incoming voltage pulse time.

FIG. 21 is a flowchart of a data writing method according to a third exemplary embodiment of the present invention.

FIG. 22 is a schematic diagram of a stylized memory cell according to a fourth exemplary embodiment.

FIG. 23 is a schematic diagram of a stylized memory cell according to another exemplary embodiment.

FIG. 24 is a flowchart of a data writing method according to a fourth exemplary embodiment of the present invention.

FIG. 25 is a flowchart of adjusting a compensation value of a corresponding memory cell according to the fourth exemplary embodiment.

In order to correctly write data to the rewritable non-volatile memory module and reduce the temperature of the memory storage device, as shown in FIG. 2, in an exemplary embodiment, the temperature of the memory storage device is detected ( S1001); whether the temperature of the memory storage device is greater than a predefined temperature is determined (S1003); if the temperature of the memory storage device is greater than a predefined temperature, at least one predefined corresponding to the rewritable non-volatile memory module The operating parameters are adjusted to generate at least one adjusted operating parameter of the corresponding rewritable non-volatile memory module and the data is written to the memory cell according to the at least one adjusted operating parameter (S1005); and if memory When the temperature of the body storage device is not greater than a predefined temperature, the data will be based on at least one of the The predefined operational parameters are written into the memory cells (S1007). For example, this predefined temperature will be set to 40oC, 45oC, 50oC, 55oC, 60oC, 65oC, 70oC, and so on. It must be understood that the present invention is not limited thereto, and the predefined temperature may be set according to the type of the rewritable non-volatile memory module. In order that the present invention can be more clearly understood, the following detailed description will be described by way of example embodiments.

[First Exemplary Embodiment]

In general, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and controller (also referred to as a control circuit). Typically, the memory storage device is used with a host system to enable the host system to write data to or read data from the memory storage device.

FIG. 3 is a diagram of a host system and a memory storage device according to a first exemplary embodiment.

Referring to FIG. 3, the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106. The computer 1100 includes a microprocessor 1102, a random access memory (RAM) 1104, a system bus 1108, and a data transmission interface 1110. The input/output device 1106 includes a mouse 1202, a keyboard 1204, a display 1206, and a printer 1208 as shown in FIG. It must be understood that the device shown in FIG. 4 is not limited to the input/output device 1106, and the input/output device 1106 may further include other devices.

In the embodiment of the present invention, the memory storage device 100 is coupled to other components of the host system 1000 through the data transmission interface 1110. The operation can be performed by the microprocessor 1102, the random access memory 1104, and the input/output device 1106. The material is written to or read from the memory storage device 100. For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a flash drive 1212, a memory card 1214, or a solid state drive (SSD) 1216 as shown in FIG.

In general, host system 1000 is any system that can substantially cooperate with memory storage device 100 to store data. Although in the present exemplary embodiment, the host system 1000 is illustrated by a computer system, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, a video camera, a communication device, an audio player, or a video player. And other systems. For example, when the host system is a digital camera (camera) 1310, the rewritable non-volatile memory storage device uses the SD card 1312, the MMC card 1314, the memory stick 1316, the CF card 1318 or Embedded storage device 1320 (shown in Figure 5). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system.

FIG. 6 is a schematic block diagram of a memory storage device according to a first exemplary embodiment.

Referring to FIG. 6 , the memory storage device 100 includes a connection interface unit 102 , a memory control circuit unit 104 , and a rewritable non-volatile memory module 106 .

In the present exemplary embodiment, the connection interface unit 102 is compatible with the Universal Serial Bus (USB) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 102 may also be a parallel advanced accessory. (Parallel Advanced Technology Attachment, PATA) Standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express) standard, Secure Digital (Secure Digital, SD) interface standard, Serial Advanced Technology Attachment (SATA) standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) Interface standard, Memory Stick (MS) interface standard, Multi Media Card (MMC) interface standard, Embedded Multimedia Card (eMMC) interface standard, Universal flash memory (Universal) Flash Storage, UFS) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard or other suitable standards.

The memory control circuit unit 104 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type, and perform data in the rewritable non-volatile memory module 106 according to an instruction of the host system 1000. Write, read, and erase operations.

The rewritable non-volatile memory module 106 is coupled to the memory control circuit unit 104 and is used to store data written by the host system 1000. In the present exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (MLC) NAND-type flash memory module (ie, two bits can be stored in one memory cell). Metadata flash memory module). However, the invention is not limited to The rewritable non-volatile memory module 106 can also be a single-level memory cell (SLC) NAND flash memory module (ie, one memory cell can store one bit of data). Flash memory module), Trinary Level Cell (TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits of data in a memory cell), other A flash memory module or other memory module with the same characteristics.

FIG. 7 is a schematic block diagram of a rewritable non-volatile memory module according to a first exemplary embodiment.

Referring to FIG. 7, the rewritable non-volatile memory module 106 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, and a data input/output buffer. The device 2210 and the control circuit 2212.

The memory cell array 2202 includes a plurality of memory cells for storing data (as shown in FIG. 1), a plurality of bit lines (not shown) connecting the memory cells, a plurality of word lines and a common source line ( The figure is not shown). The memory cells are arranged in an array at the intersection of the bit line and the word line. When receiving a write command or reading data from the memory control circuit unit 130, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208, and the data input/output buffer 2210. To write data to or read from the memory array 202, wherein the word line control circuit 2204 is used to control the word line voltage applied to the word line, and the bit line control circuit 2206 is used to Controlling the bit line, the row decoder 2208 selects the corresponding bit line according to the decoded column address in the instruction, and the data input/output buffer 2210 is used. Temporary data.

In the present exemplary embodiment, the rewritable non-volatile memory module 106 is an MLC NAND type flash memory module that uses a plurality of gate voltages to represent multi-bit data. Specifically, each memory cell of the memory cell array 2202 has a plurality of storage states, and the storage states are distinguished by a plurality of threshold voltages.

FIG. 8 is a statistical distribution diagram of gate voltages corresponding to write data stored in a memory cell array according to a first exemplary embodiment.

Referring to FIG. 8 , taking the MLC NAND type flash memory as an example, the gate voltage in each memory cell can be divided into four types according to the first threshold voltage VA, the second threshold voltage VB and the third threshold voltage VC. Status, and these storage states represent "11", "10", "00", and "01", respectively. In other words, each storage state includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). In the present exemplary embodiment, the value of the first bit from the left side in the storage state (ie, "11", "10", "00", and "01") is the LSB, and is counted from the left side. The value of the second bit is the MSB. Therefore, in the first exemplary embodiment, each memory cell can store 2 bit data. It must be understood that the correspondence between the gate voltage and its storage state illustrated in FIG. 8 is only an example. In another exemplary embodiment of the present invention, the correspondence between the gate voltage and the storage state may also be arranged in "11", "10", "01", and "00" as the gate voltage is larger. Alternatively, the storage state corresponding to the gate voltage may be a value that maps or reverses the actual stored value. In addition, in another example, the first bit from the left side may also be defined. The value is MSB, and the value of the second bit from the left is the LSB.

In this exemplary embodiment, each memory cell can store 2 bit data, so the memory cells on the same word line constitute a storage space of two physical pages (ie, the lower physical page and the upper physical page). That is to say, the LSB of each memory cell corresponds to the lower physical page, and the MSB of each memory cell corresponds to the upper physical page. In addition, several physical pages in the memory cell array 2202 form a physical block, and the physical block is the smallest unit that performs the erase operation. That is, each physical block contains one of the smallest number of erased memory cells.

The data writing (or programming) of the memory cell of the memory cell array 2202 utilizes a voltage applied to a specific terminal, such as controlling the gate voltage to change the amount of electrons in one of the gates of the charge trapping layer. Thus, the gate voltage of the memory cell is changed to present different storage states. For example, when the current page data is 1 and the upper page data is 1, the control circuit 2212 controls the word line control circuit 2204 to change the storage state of the memory cell to "11" without changing the gate voltage in the memory cell. When the current page data is 1 and the upper page data is 0, the word line control circuit 2204 changes the gate voltage in the memory cell under the control of the control circuit 2212, and changes the storage state of the memory cell to "10". When the current page data is 0 and the upper page data is 0, the word line control circuit 2204 changes the gate voltage in the memory cell under the control of the control circuit 2212, and changes the storage state of the memory cell to "00". Moreover, when the current page data is 0 and the upper page data is 1, the word line control circuit 2204 changes the gate voltage in the memory cell under the control of the control circuit 2212, and changes the storage state of the memory cell to "01". .

FIG. 9 is a schematic diagram of a stylized memory cell according to a first exemplary embodiment.

Referring to FIG. 9, in the embodiment of the present example, the stylization of the memory cell is performed by a pulse write/verify threshold voltage method. Specifically, when data is to be written to the memory cell, the memory control circuit unit 102 sets the initial write voltage and the write voltage pulse time, and indicates the control circuit 2212 of the rewritable non-volatile memory module 106. The memory cells are programmed using the set initial write voltage and write voltage pulse time for data writing. Thereafter, the memory control circuit unit 102 uses the verification voltage to verify the memory cell to determine whether the memory cell is in the correct storage state. If the memory cell is not programmed to the correct storage state, the memory control circuit unit 102 instructs the control circuit 2212 to apply the currently applied write voltage plus a preset compensation value as a new write voltage (also referred to as repetition). Write voltage) and program the memory cells again according to the new write voltage and write voltage pulse time. On the other hand, if the memory cell is programmed to the correct storage state, it means that the data has been correctly written to the memory cell. For example, the initial write voltage will be set to 16 volts (Voltage, V), the write voltage pulse time will be set to 18 microseconds (μs) and the preset compensation value is set to 0.6V, but the present invention does not Limited to this. In another exemplary embodiment, the preset compensation value may also be gradually increased or decreased.

FIG. 10 is a schematic diagram of verifying a storage state of a memory cell according to the first exemplary embodiment.

Referring to FIG. 10, the data reading of the memory cell of the memory cell array 2202 uses the threshold voltage to distinguish the gate voltage of the memory cell. In the operation of reading the next page of data, the word line control circuit 2204 applies the second threshold voltage VB to the memory cell and controls whether the control gate of the memory cell is turned on and the corresponding arithmetic expression (1) To determine the value of the next page: LSB = (VB) Lower_pre1 (1)

Wherein (VB) Lower_pre1 represents the first next page verification value obtained by applying the second threshold voltage VB.

For example, when the second threshold voltage VB is smaller than the gate voltage of the memory cell, the control gate of the memory cell does not turn on and outputs the first page verification value of the value '0', whereby the LSB is recognized as 0. For example, when the second threshold voltage VB is greater than the gate voltage of the memory cell, the control gate of the memory cell is turned on and outputs the first page verification value of the value '1', whereby the LSB is recognized as 1. That is to say, the gate voltage for presenting LSB to 1 and the gate voltage for presenting LSB to 0 can be distinguished by the second threshold voltage VB.

In the operation of reading the previous page data, the word line control circuit 2204 separately applies the third threshold voltage VC and the first threshold voltage VA to the memory cell and whether the control gate of the memory cell is turned on and the corresponding arithmetic expression. (2) to judge the value of the previous page data: MSB = ((VA) Upper_pre2) xor (~ (VC) Upper_pre1) (2)

Wherein (VC) Upper_pre1 represents the first upper page verification value obtained by applying the third threshold voltage VC, and (VA) Upper_pre2 represents the second upper page verification value obtained by applying the first threshold voltage VA, wherein the symbol "~" stands for inversion. In addition, in the present exemplary embodiment, when the third threshold voltage VC is less than the gate voltage of the memory cell, the control gate of the memory cell is not turned on and outputs the first upper page verification value of the value '0' ((VC) Upper_pre1 When the first threshold voltage VA is less than the gate voltage of the memory cell, the control gate of the memory cell is not turned on and outputs the second upper page verification value of the value '0'. ((VA) Upper_pre2).

Therefore, in the present exemplary embodiment, according to the operation formula (2), when the third threshold voltage VC and the first threshold voltage VA are both smaller than the gate voltage of the memory cell, the memory cell is subjected to the third threshold voltage VC. The control gate does not conduct and outputs the first upper page verification value of the value '0' and the control gate of the memory cell is not turned on and the second upper page verification value of the value '0' is outputted when the first threshold voltage VA is applied. At this point, the MSB will be recognized as 1.

For example, when the third threshold voltage VC is greater than the gate voltage of the memory cell and the first threshold voltage VA is less than the gate voltage of the memory cell is less than the gate voltage of the memory cell, the control of the memory cell under the application of the third threshold voltage VC The gate is turned on and outputs the first upper page verification value of the value '1', and the control gate of the memory cell is not turned on and the second upper page verification value of the value '0' is outputted when the first threshold voltage VA is applied. At this point, the MSB will be recognized as 0.

For example, when the third threshold voltage VC and the first threshold voltage VA are both greater than the gate voltage of the memory cell, under the application of the third threshold voltage VC, the control gate of the memory cell is turned on and outputs the first value of the value '1'. The previous page verifies the value, and the control gate of the memory cell is turned on under the first threshold voltage VA and outputs the second upper page verification value of the value '1'. At this point, the MSB will be recognized as 1.

It must be understood that although the invention has been described in terms of MLC NAND type flash memory. However, the present invention is not limited thereto, and other multi-layer memory cell NAND type flash memories can also read data according to the above principle.

For example, taking the TLC NAND type flash memory as an example (as shown in FIG. 11), each storage state includes the least significant bit LSB of the first bit from the left side and the second bit from the left side. Intermediate Significant Bit, CSB) and the most significant bit MSB of the third bit from the left side, where the LSB corresponds to the next page, the CSB corresponds to the middle page, and the MSB corresponds to the upper page. In this example, the gate voltage in each memory cell may be based on the first threshold voltage VA, the second threshold voltage VB, the third threshold voltage VC, the fourth threshold voltage VD, the fifth threshold voltage VE, and the sixth threshold voltage. The VF and the seventh threshold voltage VG are divided into eight storage states (ie, "111", "110", "100", "101", "001", "000", "010", and "011"). For example, taking SLC NAND type flash memory as an example (not shown), each storage state can only store one bit of data. Therefore, the gate voltage in each memory cell can recognize the memory according to a threshold voltage. The storage state of the cells (ie, "1", "0").

FIG. 12 is a schematic block diagram of a memory control circuit unit according to a first exemplary embodiment. It should be understood that the structure of the memory control circuit unit shown in FIG. 12 is only an example, and the present invention is not limited thereto.

Referring to FIG. 12 , the memory control circuit unit 104 includes a memory management circuit 202 , a host interface 204 , a memory interface 206 , and a temperature sensor 208 .

The memory management circuit 202 is used to control the overall operation of the memory control circuit unit 104. Specifically, the memory management circuit 202 has a plurality of control commands, and when the memory storage device 100 is in operation, the control commands are executed by the following sequence of instructions to the rewritable non-volatile memory module 106. Data writing, reading and erasing operations.

In the present exemplary embodiment, the control instructions of the memory management circuit 202 are implemented in a firmware version. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control commands are burned to This read-only memory. When the memory storage device 100 is in operation, such control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control command of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 (for example, the memory module is dedicated to storage). In the system area of the system data). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a drive code, and when the memory control circuit unit 104 is enabled, the microprocessor unit first executes the drive code segment to be stored in the rewritable non-volatile memory module. The control command in 106 is loaded into the random access memory of the memory management circuit 202. After that, the microprocessor unit will run these control commands to perform data writing, reading and erasing operations.

In addition, in another exemplary embodiment of the present invention, the control command of the memory management circuit 202 can also be implemented in a hardware format. For example, the memory management circuit 202 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is configured to manage the physical erasing unit of the rewritable non-volatile memory module 106; the memory writing circuit is configured to issue a write command to the rewritable non-volatile memory module 106. The data is written into the rewritable non-volatile memory module 106; the memory read circuit is used to issue a read command to the rewritable non-volatile memory module 106 to rewritable non-swing The memory module 106 reads data; the memory erasing circuit is used to issue an erase command to the rewritable non-volatile memory module 106 to transfer data from the rewritable non-volatile memory module 106. The data processing circuit processes the data to be written to the rewritable non-volatile memory module 106 and the data read from the rewritable non-volatile memory module 106.

The host interface 204 is coupled to the memory management circuit 202 and is configured to receive and identify instructions and data transmitted by the host system 1000. That is to say, the instructions and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204. In the present exemplary embodiment, host interface 204 is compatible with the USB standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the SD standard, the SATA standard, the UHS-I interface standard, and the UHS-II interface standard. MS standard, MMC standard, eMMC interface standard, UFS interface standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 206 is coupled to the memory management circuit 202 and is used to access the rewritable non-volatile memory module 106. That is, the data to be written to the rewritable non-volatile memory module 106 is converted to a format acceptable to the rewritable non-volatile memory module 106 via the memory interface 206.

The temperature sensor 208 is coupled to the sensing memory management circuit 202 and configured to detect the operating temperature of the memory storage device 100.

In an exemplary embodiment of the present invention, the memory control circuit unit 104 further includes a buffer memory 252, a power management circuit 254, and an error check and correction circuit. 256.

The buffer memory 252 is coupled to the memory management circuit 202 and is used to temporarily store data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106.

The power management circuit 254 is coupled to the memory management circuit 202 and is used to control the power of the memory storage device 100.

The error checking and correction circuit 256 is coupled to the memory management circuit 202 and is used to perform error checking and correction procedures to ensure the correctness of the data. In the present exemplary embodiment, when the memory management circuit 202 receives a write command from the host system 1000, the error check and correction circuit 256 generates a corresponding error check and correction code (Error) for the data corresponding to the write command. Checking and Correcting Code (ECC Code), and the memory management circuit 202 writes the data corresponding to the write command and the corresponding error check and correction code into the rewritable non-volatile memory module 106. Thereafter, when the memory management circuit 202 reads the data from the rewritable non-volatile memory module 106, the error check and correction code corresponding to the data is simultaneously read, and the error check and correction circuit 256 is based on the error. Check and calibration code Perform error checking and calibration procedures on the data read. In particular, error checking and correction circuit 256 will be designed to correct a number of error bits (hereinafter referred to as the maximum number of correctable error bits). For example, the maximum number of correctable error bits is 24. If the number of error bits occurring in the read data is not greater than 24, the error checking and correction circuit 256 can correct the error bit back to the correct value based on the error correction code. Conversely, the error checking and correction circuit 256 will report the error correction failure and record The memory management circuit 202 transmits a message indicating that the data has been lost to the host system 1000.

In the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) records the wear level value of the memory cells in the rewritable non-volatile memory module 106. For example, erasing of the rewritable non-volatile memory module 106 is performed in units of physical blocks, and thus, for example, the memory control circuit unit 104 (or the memory management circuit 202) records rewritable The number of erasures of each physical block in the non-volatile memory module 106, thereby monitoring the degree of wear of each memory cell. However, it must be understood that, in addition to the number of erasures as the value of the wear level, in another exemplary embodiment of the present invention, the number of writes of the memory cells, the number of error bits, the proportion of error bits, or the number of readings Or combined according to some or all of the above parameters can also be used to measure the degree of wear of memory cells.

In particular, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the operating temperature of the memory storage device 100 is greater than a predefined temperature, and if the operating temperature of the memory storage device 100 is greater than When the temperature is predefined, the memory control circuit unit 104 (or the memory management circuit 202) adjusts the initial write voltage used in the stylization according to the degree of wear of the passivation oxide layer of each memory cell. Corresponding at least one predefined operational parameter of the rewritable non-volatile memory module 106 to generate adjusted operational parameters of the corresponding rewritable non-volatile memory module 106, thereby avoiding overwriting and generating erroneous bits . Specifically, if the operating temperature of the memory storage device 100 is greater than a predefined temperature, the memory control circuit unit 104 (or the memory management circuit 202) As the value of the wear level of the memory cell increases, the initial write voltage corresponding to the memory cell is lowered.

For example, when a memory cell is to be programmed and the operating temperature of the memory storage device 100 is greater than a predefined temperature, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the value of the wear level of the memory cell is Less than the first threshold. If the value of the wear level of the memory cell is less than the first threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the first write voltage as the initial write voltage. If the value of the wear level of the memory cell is not less than the first threshold value, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the value of the wear level of the memory cell is less than the second threshold value. Moreover, if the wear level value of the memory cell is less than the second threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the second write voltage as the initial write voltage. If the value of the wear level of the memory cell is not less than the second threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the third write voltage as the initial write voltage. Here, the second threshold value is greater than the first threshold value, the first write voltage is greater than the second write voltage and the second write voltage is greater than the third write voltage. For example, the first threshold is 500; the second threshold is 1000; the first write voltage is 16V; the second write voltage is 14V, and the third write voltage is 12V. That is, as shown in Table 1, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) uses the pulse write/verify threshold voltage method to program the memory cells, which is used. The write voltage (ie, the initial write voltage (Vpro_0), the first repeated write voltage (Vpro_1), the second repeated write voltage (Vpro_2)...) will be based on the memory cell The degree of wear (WD) varies.

It must be understood that although in the above example, the threshold value of the memory cell is distinguished by the two threshold values (the first threshold value and the second threshold value) and the first write voltage, the second write voltage and the first The three write voltages are used to set the initial write voltages of the memory cells corresponding to different degrees of wear, but the invention is not limited thereto. In another exemplary embodiment of the present exemplary embodiment, the degree of wear of the memory cell can be divided into more levels, and the write voltage of each memory cell can be calculated according to the following formula: Vpgm(i, n)=IVpgm -i×A+(n)×C

Where i represents the degree of wear of the memory cell, n is the number of repeated writes, IVpgm presets the initial write voltage, C is the preset offset value and A is the preset adjustment value. Here, Vpgm (0, 0) indicates an initial write voltage when the wear of the memory cell is minimal (for example, WD < 500), and Vpgm (0, 1) indicates that the wear of the memory cell is minimal (for example, The first repeated write voltage at WD<500), and so on. In another exemplary embodiment, the preset compensation value may be correspondingly changed due to the degree of wear, wherein the change may be a linear or non-linear increase or decrease. In another exemplary embodiment, the preset adjustment value may be correspondingly changed due to a change in the number of repeated writes, wherein the change may be a linear or non-linear decrease or increase.

FIG. 13 is a data writer according to a first exemplary embodiment of the present invention. Flow chart of the law.

Referring to FIG. 13, in step S1201, the wear level value of the memory cell is recorded.

In step S1203, the operating temperature of the memory storage device 100 is detected, and in step S1205, whether the operating temperature of the memory storage device 100 is greater than a predefined temperature is judged.

If the operating temperature of the memory storage device 100 is greater than a predefined temperature, in step S1207, the initial write voltage of the corresponding memory cell is adjusted according to the wear level value of the memory cell.

Thereafter, in step S1209, the adjusted initial write voltage and the write voltage pulse time of the corresponding memory cell are used to program the memory cell to write the data into the memory cell.

If the operating temperature of the memory storage device 100 is not greater than a predefined temperature, in step S1211, the preset initial write voltage and the write voltage pulse time of the corresponding memory cell are used to program the memory cell to write the data. Into the memory cell.

FIG. 14 is a flow chart of adjusting an initial write voltage of a corresponding memory cell according to the first exemplary embodiment.

Referring to FIG. 14, whether the value of the wear level of the memory cell is less than the first threshold value is determined in step S1301.

If the value of the wear level of the memory cell is less than the first threshold value, the first write voltage is used as the initial write voltage in step S1303.

If the value of the wear level of the memory cell is not less than the first threshold value, then In step S1305, whether the value of the wear level of the memory cell is less than the second threshold value is judged.

If the value of the wear level of the memory cell is less than the second threshold value, the second write voltage is used as the initial write voltage in step S1307.

If the value of the wear level of the memory cell is not less than the second threshold value, the third write voltage is used as the initial write voltage in step S1309.

[Second exemplary embodiment]

The structure of the memory storage device of the second exemplary embodiment is similar to that of the memory storage device of the first exemplary embodiment, except that the memory control circuit unit (or memory management circuit) of the second exemplary embodiment will Adjusting at least one predefined operational parameter of the corresponding rewritable non-volatile memory module 106 to generate a corresponding rewritable by adjusting the write voltage pulse time used in the stylization according to the degree of wear of each memory cell The operational parameters of the non-volatile memory module 106 are adjusted to thereby avoid overwriting and generating erroneous bits. The differences between the second exemplary embodiment and the first exemplary embodiment will be described below using the component numbers of the first exemplary embodiment.

Generally, the memory control circuit unit 104 (or the memory management circuit 202) will use a predetermined time (also referred to as a preset write voltage pulse time, for example, 16 microseconds) as a flash memory storage module. The write voltage pulse time of the memory cell of 106. Moreover, when the memory cell is programmed, the memory control circuit unit 104 (or the memory management circuit 202) uses the write voltage pulse time to match the initial write voltage to inject electrons into the memory cell. In the present exemplary embodiment, the memory control circuit is single The element 104 (or the memory management circuit 202) determines whether the operating temperature of the memory storage device 100 is greater than a predefined temperature, and if the operating temperature of the memory storage device 100 is greater than a predefined temperature, the memory control circuit unit 104 (or The memory management circuit 202) decreases the write voltage pulse time corresponding to the memory cell as the value of the wear level of the memory cell increases.

15-17 are schematic diagrams of stylized memory cells according to a second exemplary embodiment.

Referring to FIG. 15-17, for example, when a memory cell is to be programmed, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the value of the wear level of the memory cell is less than the first threshold. If the value of the wear level of the memory cell is less than the first threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the first time as the write voltage pulse time (as shown in FIG. 15). If the value of the wear level of the memory cell is not less than the first threshold value, the memory control circuit unit 104 (or the memory management circuit 202) determines that the wear level value of the memory cell is less than the second threshold value. Moreover, if the wear level value of the memory cell is less than the second threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the second time as the write voltage pulse time (as shown in FIG. 16). If the value of the wear level of the memory cell is not less than the second threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the third time as the write voltage pulse time (as shown in FIG. 17). For example, the first time is 18 microseconds, the second time is 14.4 microseconds, and the third time is 11.7 microseconds. That is, as shown in Table 1, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) is used. When the pulse write/verify threshold voltage method is used to program the memory cell, the write voltage pulse time used will vary depending on the memory cell wear level value (WD).

In another exemplary embodiment, the initial write voltage pulse time may be correspondingly changed due to the degree of wear, wherein the change may be a linear or non-linear increase or decrease. In another exemplary embodiment, the preset adjustment value of the write voltage pulse time may be correspondingly changed due to a change in the number of repeated writes, wherein the change may be a linear or non-linear decrease or increase.

For example, when the adjusted write voltage pulse time is determined according to the wear level of the memory cell according to the preset write voltage pulse time, the write voltage pulse is adjusted during the use of the pulse write/verify threshold voltage method to program the memory cell. The time will be used for the first repetitive stylization and the second repetitive stylization, and the preset write voltage pulse time will be the third repetitive stylization, the fourth repetitive stylization...etc. That is, during the use of the pulse write/verify threshold voltage method to program the memory cells, the adjusted write voltage pulse time is used for a portion of the reprogramming, and the preset write voltage pulse time is Used for repeated stylization of another part (as shown in Figure 18).

In addition, it is worth mentioning that, in the exemplary embodiment, when the verification voltage is used to confirm that the memory cell is not programmed to the correct storage state, the memory control power The circuit unit 102 instructs the control circuit 2212 to use the currently applied write voltage plus the preset compensation value as the new write voltage (also referred to as the repeated write voltage) and according to the new write voltage and the same write voltage pulse. Time to program the memory cells again. However, the present invention is not limited thereto, and in another exemplary embodiment of the present invention, the write voltage pulse time may also increase as the number of repetitions of the program is increased.

FIG. 19 is a flowchart of a data writing method according to a second exemplary embodiment of the present invention.

Referring to FIG. 19, in step S1701, the wear level value of the memory cell is recorded.

In step S1703, the operating temperature of the memory storage device 100 is detected, and in step S1705, whether the operating temperature of the memory storage device 100 is greater than a predefined temperature is judged.

If the operating temperature of the memory storage device 100 is greater than a predefined temperature, in step S1707, the write voltage pulse time of the corresponding memory cell is adjusted according to the wear level value of the memory cell.

In step S1709, the initial write voltage of the corresponding memory cell and the adjusted write voltage pulse time are used to program the memory cell to write the data into the memory cell.

If the operating temperature of the memory storage device 100 is not greater than a predefined temperature, in step S1711, the initial write voltage of the corresponding memory cell and the preset write voltage pulse time are used to program the memory cell to write the data. Into the memory cell.

FIG. 20 is a diagram of adjusting corresponding memory cells according to a second exemplary embodiment Flowchart for writing voltage pulse time.

Referring to FIG. 20, whether the value of the wear level of the memory cell is less than the first threshold value is determined in step S1801.

If the value of the wear level of the memory cell is less than the first threshold value, the first time is used as the write voltage pulse time in step S1803.

If the value of the wear level of the memory cell is not less than the first threshold value, then in step S1805, whether the value of the wear level of the memory cell is less than the second threshold value is determined.

If the value of the wear level of the memory cell is less than the second threshold value, the second time is used as the write voltage pulse time in step S1807.

If the value of the wear level of the memory cell is not less than the second threshold value, the third time is used as the write voltage pulse time in step S1809.

[Third exemplary embodiment]

When it is determined that the operating temperature of the memory storage device 100 is greater than a predefined temperature, the amount of electrons injected into the memory cell is reduced and the amount of electrons injected into the memory cell is reduced by adjusting the initial write voltage used in the staging according to the degree of wear of each memory cell. The degree of wear of the memory cells to adjust the write voltage pulse time used in the stylization to reduce the amount of electrons injected into the memory cells are separately described in the first exemplary embodiment and the second exemplary embodiment. However, in another exemplary embodiment of the present invention, the memory control circuit unit (or the memory management circuit) can also simultaneously adjust the initial write voltage and write used in the stylization according to the degree of wear of each memory cell. The voltage is pulsed, thereby avoiding overwriting and generating erroneous bits. For example, when the memory cell wear level value is not less than the first When a threshold is less than the second threshold, the initial write voltage is adjusted to 90% of the original initial write voltage and the write voltage pulse time is adjusted to 90% of the original write voltage pulse time; when the memory cell is worn When the degree value is not less than the second threshold value and less than the third threshold value, the initial write voltage is adjusted to 85% of the original initial write voltage and the write voltage pulse time is adjusted to 80% of the original write voltage pulse time; And when the wear level value of the memory cell is not less than the third threshold value, the initial write voltage is adjusted to 80% of the original initial write voltage and the write voltage pulse time is adjusted to 70% of the original write voltage pulse time.

FIG. 21 is a flowchart of a data writing method according to a third exemplary embodiment of the present invention.

Referring to FIG. 21, in step S1901, the wear level value of the memory cell is recorded.

In step S1903, the operating temperature of the memory storage device 100 is detected, and in step S1905, whether the operating temperature of the memory storage device 100 is greater than a predefined temperature is judged.

If the operating temperature of the memory storage device 100 is greater than a predefined temperature, in step S1907, the initial write voltage and the write voltage pulse time of the corresponding memory cell are adjusted according to the wear level value of the memory cell.

In step S1909, the adjusted initial write voltage and the adjusted write voltage pulse time of the corresponding memory cell are used to program the memory cell to write data into the memory cell.

If the operating temperature of the memory storage device 100 is not greater than a predefined temperature In step S1911, the preset initial write voltage and the preset write voltage pulse time corresponding to the memory cell are used to program the memory cell to write data into the memory cell.

[Fourth exemplary embodiment]

The structure of the memory storage device of the fourth exemplary embodiment is similar to that of the memory storage device of the first exemplary embodiment, except that the memory control circuit unit (or memory management circuit) of the fourth exemplary embodiment will Adjusting at least one predefined operational parameter of the corresponding rewritable non-volatile memory module 106 to generate a corresponding rewritable by adjusting a preset compensation value used in the stylization according to the degree of wear of each memory cell The operational parameters of the non-volatile memory module 106 have been adjusted, thereby avoiding overwriting and generating erroneous bits. The differences between the fourth exemplary embodiment and the first exemplary embodiment will be described below using the component numbers of the first exemplary embodiment.

In the fourth exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the operating temperature of the memory storage device 100 is greater than a predefined temperature, and if the operating temperature of the memory storage device 100 is greater than a predefined At the temperature, the memory control circuit unit 104 (or the memory management circuit 202) adjusts the corresponding compensation value used in the stylization according to the degree of wear of the through oxide layer of each memory cell to adjust the corresponding value. At least one predefined operational parameter of the rewritable non-volatile memory module 106 to generate adjusted operational parameters of the rewritable non-volatile memory module 106, thereby avoiding overwriting and generating erroneous bits. Specifically, if the operating temperature of the memory storage device 100 is greater than a predetermined At the sense of temperature, the memory control circuit unit 104 (or the memory management circuit 202) decreases the preset compensation value corresponding to the memory cell as the value of the wear level of the memory cell increases (ie, the compensation value ΔV' has been lowered). ).

For example, when a memory cell is to be programmed and the operating temperature of the memory storage device 100 is greater than a predefined temperature, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the value of the wear level of the memory cell is Less than the first threshold. If the value of the wear level of the memory cell is less than the first threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the first compensation value as the preset compensation value. If the value of the wear level of the memory cell is not less than the first threshold value, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the value of the wear level of the memory cell is less than the second threshold value. Moreover, if the wear level value of the memory cell is less than the second threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the second compensation value as the preset compensation value. If the value of the wear level of the memory cell is not less than the second threshold value, the memory control circuit unit 104 (or the memory management circuit 202) uses the third compensation value as the preset compensation value. Here, the second threshold value is greater than the first threshold value, the first compensation value is greater than the second compensation value and the second compensation value is greater than the third compensation value. For example, the first threshold is 500; the second threshold is 1000; the first compensation value is 0.06V; the second compensation value is 0.05V, and the third compensation value is 0.04V. That is, as shown in Table 3, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) uses the pulse write/verify threshold voltage method to program the memory cells, which is used. Write voltage (ie, initial write voltage (Vpro_0), first repeated write voltage (Vpro_1), The second repeated write voltage (Vpro_2)...) will vary depending on the wear level value (WD) of the memory cell.

It must be understood that although in the above example, the threshold value of the memory cell is distinguished by two threshold values (the first threshold value and the second threshold value) and the first compensation value, the second compensation value and the third compensation are used. The value is used to set a preset compensation value of the memory cell corresponding to different degrees of wear, but the present invention is not limited thereto. In another exemplary embodiment of the present exemplary embodiment, the degree of wear of the memory cell can be divided into more levels, and the write voltage of each memory cell can be calculated according to the following formula: Vpgm(i, n)=IVpgm +n×(Ci×A)

Where i represents the degree of wear of the memory cell, n is the number of repeated writes, IVpgm presets the initial write voltage, C is the preset offset value and A is the preset adjustment value. Here, Vpgm (0, 0) indicates an initial write voltage when the wear of the memory cell is minimal (for example, WD < 500), and Vpgm (0, 1) indicates that the wear of the memory cell is minimal (for example, The first repeated write voltage at WD<500), and so on. In another exemplary embodiment, the preset adjustment value may be correspondingly changed depending on the degree of wear, wherein the change may be a linear or non-linear increase or decrease.

It is necessary that although in the fourth exemplary embodiment, the preset compensation value is fixed after being correspondingly determined according to the degree of wear of the memory cell, the present invention Not limited to this. In another exemplary embodiment, the preset compensation value of the corresponding memory cell may have been changed during the programming of the memory cell using the pulse write/verify threshold voltage method. For example, if the adjusted compensation value is determined according to the degree of wear of the memory cell according to the preset compensation value, the adjusted compensation value is used to calculate the value during the use of the pulse writing/verification threshold voltage method to program the memory cell. The write voltage and the second repeated write voltage are repeated, and the preset compensation value is used to calculate the third repeated write voltage, the fourth repeated write voltage, and the like. That is, during the use of the pulse write/verify threshold voltage method to program the memory cell, a portion of the write voltage is calculated based on the adjusted compensation value (the reduced compensation value ΔV'), and the other portion The write voltage is calculated based on the preset compensation value ΔV (as shown in Figure 23).

FIG. 24 is a flowchart of a data writing method according to a fourth exemplary embodiment of the present invention.

Referring to FIG. 24, in step S2101, the wear level value of the memory cell is recorded.

In step S2103, the operating temperature of the memory storage device 100 is detected, and in step S2105, whether the operating temperature of the memory storage device 100 is greater than a predefined temperature is judged.

If the operating temperature of the memory storage device 100 is greater than a predefined temperature, in step S2107, the preset compensation value of the corresponding memory cell is adjusted according to the wear level value of the memory cell.

Thereafter, in step S2109, the preset initial write voltage, the preset write voltage pulse time, and the adjusted compensation value corresponding to the memory cell are used to program the memory. Cell to write data into memory cells.

If the operating temperature of the memory storage device 100 is not greater than a predefined temperature, the preset initial write voltage, the preset write voltage pulse time, and the preset compensation value corresponding to the memory cell are used to be programmed in step S2111. Memory cells to write data into memory cells.

FIG. 25 is a flowchart of adjusting a compensation value of a corresponding memory cell according to the fourth exemplary embodiment.

Referring to FIG. 25, whether the value of the wear level of the memory cell is less than the first threshold value in step S2201 is judged.

If the wear level value of the memory cell is less than the first threshold value, the first compensation value is used as the preset compensation value in step S2203.

If the value of the wear level of the memory cell is not less than the first threshold value, then in step S2205, whether the value of the wear level of the memory cell is less than the second threshold value is judged.

If the value of the wear level of the memory cell is less than the second threshold value, the second compensation value is used as the preset compensation value in step S2207.

If the value of the wear level of the memory cell is not less than the second threshold value, the third compensation value is used as the preset compensation value in step S2209.

In summary, in the data writing method, the memory control circuit unit and the memory storage device of the exemplary embodiment of the present invention, if the operating temperature of the memory storage device is greater than a predefined temperature, corresponding to the rewritable non-volatile memory At least one predefined operational parameter of the body module is adjusted based on the degree of wear of the memory cell. Accordingly, the electrons injected into the memory cell each time the program is converted are adjusted according to the wear state of the memory cell, thereby effectively preventing overwriting and reducing the occurrence of erroneous bits.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

S1001, S1003, S1005, S1007‧‧‧ steps of data writing method

Claims (18)

A data writing method for writing data to a memory cell of a rewritable non-volatile memory module of a memory storage device, the data writing method comprising: detecting the memory storage device An operating temperature; determining whether the operating temperature of the memory storage device is greater than a predefined temperature; and adjusting the corresponding rewritable non-volatile memory if the operating temperature of the memory storage device is greater than the predefined temperature At least one predefined operational parameter of the body module to generate at least one adjusted operational parameter corresponding to the rewritable non-volatile memory module and to write the data to the memory cell based on the at least one adjusted operational parameter, And adjusting the at least one predefined operational parameter corresponding to the rewritable non-volatile memory module to generate the at least one adjusted operational parameter corresponding to the rewritable non-volatile memory module and according to the at least one The step of writing the data to the memory cell by adjusting the operating parameter comprises: recording a wear level value of the memory cell; Adjusting, according to the wear level value of the memory cell, at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell; and using the initial corresponding to the memory cell Writing a voltage, the write voltage pulse time, and the compensation value to program the memory cell to write the data to The memory cell, wherein the step of adjusting at least one of the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell according to the wear level value of the memory cell includes : as the value of the degree of wear of the memory cell increases, the compensation value corresponding to the memory cell is reduced. The data writing method of claim 1, wherein the initial writing voltage, the writing voltage pulse time corresponding to the memory cell are adjusted according to a value of a wear level of the memory cell The step of at least one of the compensation values includes decreasing the initial write voltage corresponding to the memory cell as the wear level value of the memory cell increases. The data writing method of claim 1, wherein the initial writing voltage, the writing voltage pulse time corresponding to the memory cell are adjusted according to a value of a wear level of the memory cell The step of at least one of the compensation values includes decreasing the write voltage pulse time corresponding to the memory cell as the wear level value of the memory cell increases. The data writing method of claim 3, wherein the programming the memory by using the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell The step of writing the data to the memory cell includes: Performing at least one repetitive stylization of the memory cell using the initial write voltage, the reduced write voltage pulse time, and the compensation value; and using the initial write voltage, the write voltage pulse time and The compensation value is used to perform other repetitive stylization of the memory cell. The data writing method of claim 1, wherein the memory cell wear level value is based on an erasure number of the memory cell, a write count, an error bit number, and an error bit. The ratio and the number of readings are determined by at least one of them. The data writing method of claim 1, wherein the program is used to program the memory by using the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell. And the step of writing the data to the memory cell includes: performing at least one repetitive stylization of the memory cell using the initial write voltage, the write voltage pulse time, and the reduced compensation value And using the initial write voltage, the write voltage pulse time, and the compensation value to perform other repetitive stylization of the memory cell. A memory control circuit unit for writing data into a memory cell of a rewritable non-volatile memory module of a memory storage device, the memory control circuit unit comprising: a host interface, To be coupled to a host system; a memory interface for coupling to the rewritable non-volatile memory module; a memory management circuit coupled to the host interface and the memory interface; and a temperature sensor coupled to the memory management circuit and configured to detect an operating temperature of the memory storage device, The memory management circuit is configured to determine whether the operating temperature of the memory storage device is greater than a predefined temperature, and if the operating temperature of the memory storage device is greater than the predefined temperature, the memory management circuit is further </ RTI> adjusting at least one predefined operational parameter corresponding to the rewritable non-volatile memory module to generate at least one adjusted operational parameter corresponding to the rewritable non-volatile memory module and adjusted according to the at least one The operating parameter issues a sequence of instructions to the rewritable non-volatile memory module to write the data to the memory cell, wherein the adjusting the at least one pre-corresponding non-volatile memory module Defining operational parameters to generate the at least one adjusted operational parameter corresponding to the rewritable non-volatile memory module and according to the Having an adjusted operating parameter to issue the sequence of instructions to the rewritable non-volatile memory module to write the data into the memory cell, the memory management circuit recording the degree of wear of the memory cell And adjusting, according to the wear level value of the memory cell, at least one of an initial write voltage, a write voltage pulse time, and a compensation value corresponding to the memory cell, and using the corresponding to the memory cell Initializing a write voltage, the write voltage pulse time, and the compensation value to program the memory cell to write the data to the memory cell, Wherein in the operation of adjusting at least one of the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell according to the wear level value of the memory cell, the memory The body management circuit is configured to reduce the compensation value corresponding to the memory cell as the wear level value of the memory cell increases. The memory control circuit unit of claim 7, wherein the initial write voltage, the write voltage pulse time corresponding to the memory cell are adjusted according to the wear level value of the memory cell In operation of at least one of the compensation values, the memory management circuit is configured to decrease the initial write voltage corresponding to the memory cell as the value of the wear level of the memory cell increases. The memory control circuit unit of claim 7, wherein the initial write voltage, the write voltage pulse time corresponding to the memory cell are adjusted according to the wear level value of the memory cell In operation of at least one of the compensation values, the memory management circuit is configured to reduce the write voltage pulse time corresponding to the memory cell as the wear level value of the memory cell increases. The memory control circuit unit of claim 9, wherein the program is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell. Denoting a memory cell to write the data into operation of the memory cell, the memory management circuit performing the initial write voltage, the reduced write voltage pulse time, and the compensation value At least one of the memory cells is repeatedly programmed, and the other repeated programming of the memory cell is performed using the initial write voltage, the write voltage pulse time, and the compensation value. The memory control circuit unit of claim 7, wherein the memory cell wear level value is based on an erasure number of the memory cell, a write count, an error bit number, and an error bit. The meta ratio and at least one of the number of readings are determined. The memory control circuit unit of claim 7, wherein the initial writing voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell are used to program the program Denoting a memory cell to write the data into operation of the memory cell, the memory management circuit performing the initial write voltage, the write voltage pulse time, and the reduced compensation value At least one of the memory cells is repeatedly programmed, and the other repeated programming of the memory cell is performed using the initial write voltage, the write voltage pulse time, and the compensation value. A memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module; and a memory control circuit unit coupled to the connection interface unit And the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to detect an operating temperature of the memory storage device, wherein the memory control circuit unit is further configured to determine the memory Whether the operating temperature of the bulk storage device is greater than a predefined temperature, wherein if the operating temperature of the memory storage device is greater than the predefined temperature The memory control circuit unit is further configured to adjust at least one predefined operational parameter corresponding to the rewritable non-volatile memory module to generate at least one corresponding to the rewritable non-volatile memory module. Adjusting the operational parameters and issuing a sequence of instructions to the rewritable non-volatile memory module to write the data to the memory cell according to the at least one adjusted operational parameter, wherein the adjustment corresponds to the rewritable non- The at least one predefined operational parameter of the volatile memory module to generate the at least one adjusted operational parameter corresponding to the rewritable non-volatile memory module and to issue the instruction sequence according to the at least one adjusted operational parameter The rewritable non-volatile memory module for writing the data into the memory cell, wherein the memory control circuit unit records the wear level value of the memory cell according to the degree of wear of the memory cell The value adjustment corresponds to at least one of an initial write voltage, a write voltage pulse time, and a compensation value of the memory cell, and The memory cell is programmed using the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell to write the data to the memory cell, wherein The memory control circuit is configured to adjust at least one of the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell according to the wear level value of the memory cell The unit is configured to reduce the compensation value corresponding to the memory cell as the wear level value of the memory cell increases. The memory storage device of claim 13, wherein the initial write voltage, the write voltage pulse time and the corresponding memory cell are adjusted according to the wear level value of the memory cell At least one of the compensation values In one operation, the memory control circuit unit is configured to decrease the initial write voltage corresponding to the memory cell as the wear level value of the memory cell increases. The memory storage device of claim 13, wherein the initial write voltage, the write voltage pulse time and the corresponding memory cell are adjusted according to the wear level value of the memory cell In operation of at least one of the compensation values, the memory control circuit unit is configured to reduce the write voltage pulse time corresponding to the memory cell as the wear level value of the memory cell increases. The memory storage device of claim 15, wherein the program is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell. a memory cell for writing the data to the operation of the memory cell, the memory control circuit unit performing the initial write voltage, the reduced write voltage pulse time, and the compensation value At least one of the memory cells is repeatedly programmed, and the other repeated programming of the memory cell is performed using the initial write voltage, the write voltage pulse time, and the compensation value. The memory storage device of claim 13, wherein the memory cell wear level value is based on an erasure number of the memory cell, a write count, an error bit number, and an error bit. The ratio and the number of readings are determined by at least one of them. The memory storage device of claim 13, wherein the program is programmed to use the initial write voltage, the write voltage pulse time, and the compensation value corresponding to the memory cell. Memory cell to write the data to In operation of the memory cell, the memory control circuit unit performs at least one repetitive stylization of the memory cell using the initial write voltage, the write voltage pulse time, and the reduced compensation value, and uses The initial write voltage, the write voltage pulse time, and the compensation value perform other repetitive stylization of the memory cell.