TWI533122B - Boot detecting circuit, computer system and boot detecting method thereof - Google Patents

Description

Boot detection circuit, computer system and its boot detection method

The invention relates to a boot detection circuit, and in particular to a boot detection circuit of a computer system.

At present, the basic input/output system (BIOS) code used by most computer systems to execute the boot program is stored in the memory of the computer system. When the computer system is started, the central processor first performs a Power on self test (POST) according to the basic input and output system code to check whether each basic device (the motherboard, the display card) is normal, and then Follow the procedure. The basic input/output system code is used to manage the system date, display mode, floppy disk drive, hard disk type, peripheral devices (such as communication ports, printers, etc.), and random access memory (Random Access Memory, RAM). ) and configuration of cache memory (Cache Memory). Therefore, the basic input/output system code is an important startup program for the computer system to boot.

However, when the computer system is started, if some components operate abnormally, such as the memory used to store the basic I/O system code or the operating voltage of the central processor, the computer system cannot perform the boot self-test. At this point, you need to detect the components in the computer system separately to find out the anomalies.

Therefore, there is a need for a boot detection circuit that detects the initial state of the computer system and displays a corresponding system health code (SHC) before the computer system performs the boot self test.

The invention provides a boot detection circuit suitable for use in a computer system. The boot detection circuit includes a display device and a controller coupled to the display device. Before the computer system executes a boot self-test program according to a basic input/output system code, the controller provides a system health code to the display device, wherein the system health code is used to indicate an operating voltage of components in the computer system. Is it normal?

Furthermore, the present invention provides a computer system. The computer system includes: a central processing unit; a memory; a peripheral device control center; and a power-on detection circuit coupled to the central processing unit, the memory, and the peripheral device control center. The boot detection circuit executes a boot detection process, and after completing the boot detection process, provides a reset signal to the central processor, so that the central processor executes a boot self test procedure according to a basic input/output system code.

Furthermore, the present invention provides a boot detection method suitable for use in a computer system, wherein the computer system includes a boot detection circuit. The booting detection method includes: performing a boot detection process by one of the controllers of the boot detection circuit, and displaying a system health code corresponding to the result of the boot detection procedure via one of the boot detection circuits; and After completing the boot detection procedure, a reset signal is provided to the central processing unit of the computer system by the controller, so that the central processor executes a boot self-test program according to a basic input/output system code. The system health code is used to indicate whether the operating voltage of the components in the computer system is normal.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Example:

1 shows a computer system 100 in accordance with an embodiment of the present invention. The computer system 100 includes a power management module 110, a power-on detection circuit 120, a central processing unit 130, a memory 140 (such as a dynamic random access memory (DRAM)), and a peripheral device control center (Platform Controller Hub, PCH) 150, power supply 180, and flash memory 190. The power supply 180 generates a standby power P _SB and an input power P _in according to the DC power source DC or the AC power source AC. The power management module 110 generates operating voltages of different voltage levels to various components within the computer system 100 according to the input power source P _in . For example, the power management module 110 can generate the operating voltages CPU_PWR, MEM_PWR, and PCH_PWR of the central processing unit 130, the memory 140, and the peripheral device control center 150 according to the input power source P _in , which may be the same voltage level or Different voltage levels. The power-on detection circuit 120 includes a controller 160 and a display device 170. The controller 160 executes a boot detection procedure and provides a corresponding system health code SHC to the display device 170 to display the boot detection status of the computer system 100 before the central processor 130 executes a boot self test procedure. After the controller 160 successfully completes the power-on detection procedure, the controller 160 provides a reset signal CPU_RESET_N to the central processing unit 130 to notify the central processing unit 130 that the power-on self-test procedure can be performed. Next, the peripheral device control center 150 transmits the BIOS of the basic input/output system code stored in the flash memory 190 to the central processing unit 130. During execution of the power-on self-test procedure by the central processor 130, the controller 160 transmits a power-on self test code POST from the central processor 130 to the display device 170 to display the corresponding result.

2 is a diagram showing a power-on detection method according to an embodiment of the present invention, which is applicable to a computer system including a power-on detection circuit (for example, the power-on detection circuit of FIG. 1). First, a controller in the power-on detection circuit executes a power-on detection program and displays a system health code corresponding to the result of the power-on detection program through a display device (step S210). Then, after the boot detection process is completed, the controller in the boot detection circuit provides a reset signal CPU_RESET_N to the central processing unit of the computer system, so that the central processing unit can execute the boot self test procedure according to the basic input and output system code (step S220). ) in order to complete the boot process. Simultaneously, the controller in the power-on detection circuit transmits the power-on self-test code from the central processing unit to the display device for display.

3A and 3B are flowcharts showing execution of a power-on detection procedure according to an embodiment of the present invention. Referring to FIG. 1 and FIGS. 3A and 3B simultaneously, first, the controller 160 determines whether the standby power source P _SB is normal (step S302). If not, the controller 160 provides the system health code SHC ₁ to the display 170 and ends the power-on detection procedure (step S304). If the standby power P _SB is normal, the controller 160 determines whether the instant clock CLK is normal (step S306), wherein the instant clock CLK is a clock signal of 32.768 Hz. If not, the controller 160 provides the system health code SHC ₂ to the display 170 and ends the power-on detection procedure (step S308). If the instant clock CLK is normal, the controller 160 determines whether the BIOS of the basic input/output system code stored in the flash memory 190 is normal (step S307). If not, the controller 160 provides the system health code SHC ₁₀ to the display 170 and ends the power-on detection procedure (step S309). If the basic input/output system code BIOS is normal, the controller 160 provides the system health code SHC ₃ to the display 170 (step S310). Next, the controller 160 detects that the power switch of the computer system is pressed by the user (step S312). Then, the controller 160 determines whether the sleep control signal SLP_S3 is normal (step S314), wherein the sleep control signal SLP_S3 is provided by the controller 160 to the power management module 110 for enabling the power management module 110 to generate the computer system 100. Different operating voltages required. If not, the controller 160 provides the system health code SHC ₄ to the display 170 and ends the power-on detection procedure (step S316). If the sleep control signal SLP_3 is normal, the controller 160 further determines whether the operating voltage of the different voltage levels generated by the power management module 110 is normal (step S318). If not, the controller 160 provides the corresponding system health code SHC ₅ to the display 170, and ends the power-on detection procedure (step S320). For example, when 12,5,3.3,1.5 1.2 volts operating voltage is not normal, the controller 160 can provide system health are code _{SHC 5_1, SHC 5_2, SHC 5_3} , SHC 5_4, SHC 5_5 to the display 170. If the operating voltages of different voltage levels generated by the power management module 110 are normal, the controller 160 further determines whether the control signal CPU_PWRGD is normal (step S322). If not, the controller 160 provides the system health code SHC ₆ to the display 170 and ends the power-on detection procedure (step S324). If the control signal CPU_PWRGD is normal, the controller 160 provides a control signal CPU_PWRGD to the central processor 130 to notify the central processor 130 that the power is ready. Next, the controller 160 further determines whether the control signal MEM_PWRGD is normal (step S326). If not, the controller 160 provides the system health code SHC ₇ to the display 170 and ends the power-on detection procedure (step S328). If the control signal MEM_PWRGD is normal, the controller 160 provides a control signal MEM_PWRGD to the central processor 130 to notify the memory 140 that the power is ready. Next, the controller 160 further determines whether the control signal SYS_PWRGD is normal (step S330). If not, the controller 160 provides the system health code SHC ₈ to the display 170 and ends the power-on detection procedure (step S332). If the control signal SYS_PWRGD is normal, the controller 160 provides a control signal SYS_PWRGD to the peripheral device control center 150 to notify that all of the power is ready. Next, the controller 160 further determines whether the reset signal CPU_RESET_N is normal (step S334). If not, the controller 160 provides the system health code SHC ₉ to the display 170 and ends the power-on detection procedure (step S336). If the reset signal CPU_RESET_N is normal, the controller 160 provides a reset signal CPU_RESET_N to the central processing unit 130 to initialize the central processing unit 130, so that the central processing unit 130 executes the boot self-test program according to the basic input/output system code. And generate the corresponding boot self test code POST. Next, the controller 160 transmits the power-on self test code POST from the central processing unit 130 to the display device 170 to display the corresponding result (step S338). If the boot self test procedure is normal, the computer system 100 will complete the boot process.

Figure 4 is a diagram showing a power-on detection circuit 200 in accordance with an embodiment of the present invention. The power-on detection circuit 200 includes a controller 210 and a display device 220. The controller 210 includes an 80 埠 decoder 230, a detector 240, and a multiplexer 250. The 80 埠 decoder 230 is configured to decode the boot self test code POST from the central processor to generate a decoded material POST_D to the multiplexer. 250. The detector 240 is configured to execute a power-on detection program to detect and determine signals such as the instantaneous clock CLK, the operating voltages CPU_PWR, MEM_PWR and PCH_PWR, and the standby power P _SB , and generate a sleep control signal SLP_S3, a control signal CPU_PWRGD, MEM_PWRGD and SYS_PWRGD and reset signal CPU_RESET_N. Simultaneously, the detector 240 generates a corresponding system health code SHC to the multiplexer 250. When the power-on detection procedure is executed, the detector 240 provides a reset signal CPU_RESET_N to the multiplexer 250 having a first logic level. Then, the multiplexer 250 transmits the system health code SHC provided by the detector 240 to the display device 220. After successfully completing the boot detection process, the detector 240 provides a reset signal CPU_RESET_N with a second logic level to the central processor to control the central processor to perform the boot self test procedure. Simultaneously, the detector 240 provides a reset signal CPU_RESET_N to the multiplexer 250 having a second logic level. Then, the multiplexer 250 transmits the decoded material POST_D provided by the 80-inch decoder 230 to the display device 220. In one embodiment, the detector 240 further includes a memory 260 for storing the previous basic input/output system code BIOS. In addition, the detector 240 further provides a system health code for indicating whether the basic input/output system code BIOS stored in the memory 260 is the same as the basic input/output system code stored in the flash memory. For example, after the basic input/output system code BIOS of the computer system is updated, the computer system will boot according to the updated basic input/output system code BIOS. After the computer system is successfully powered on for the first time, the power-on detection circuit 200 copies the complete basic input/output system code BIOS or part of the information (for example, checksum) from the flash memory to the memory 260. Thus, the detector 240 can confirm whether the BIOS of the basic input/output system code of the flash memory is normal, as described in step S307 of FIG. 3A. In this embodiment, display device 220 includes a plurality of light emitting diodes. In addition, the system health code SHC and the decoded material POST_D have respective codes for respectively controlling the corresponding light-emitting diodes. In an embodiment, the controller 210 is disposed in a Complex Programmable Logic Device (CPLD).

According to the embodiment of the present invention, the system health code SHC and the boot self-test code POST can be displayed through the display device 170, so that the user can obtain the boot detection program and the result of the boot self-test program during the boot process.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . computer system

110. . . Power management module

120. . . Boot detection circuit

130. . . CPU

140. . . Memory

150. . . Peripheral device control center

160. . . Controller

170. . . Display device

180. . . Power Supplier

190. . . Flash memory

AC. . . AC power

BIOS. . . Basic input and output system code

200. . . Boot detection circuit

210. . . Controller

220. . . Display device

230. . . 80埠 decoder

240. . . Detector

250. . . Multiplexer

260. . . Memory

CLK. . . Instant clock

CPU_PWR, MEM_PWR, PCH_PWR. . . Operating voltage

CPU_PWRGD, MEM_PWRGD, SYS_PWRGD. . . control signal

CPU_RESET_N. . . Reset signal

DC. . . DC power supply

POST. . . Boot self test code

POST_D. . . Decoding data

P _in . . . Input power

P _SB . . . Standby power

SHC. . . System health code

SLP_S3. . . Sleep control signal

1 is a diagram showing a computer system according to an embodiment of the invention;

2 is a diagram showing a boot detection method according to an embodiment of the present invention, which is applicable to a computer system including a boot detection circuit;

3A and 3B are flowcharts showing execution of a boot detection procedure according to an embodiment of the present invention;

Figure 4 is a diagram showing a power-on detection circuit according to an embodiment of the present invention.

100. . . computer system

110. . . Power management module

120. . . Boot detection circuit

130. . . CPU

140. . . Memory

150. . . Peripheral device control center

160. . . Controller

170. . . Display device

180. . . Power Supplier

190. . . Flash memory

AC. . . AC power

BIOS. . . Basic input and output system code

CLK. . . Instant clock

CPU_PWR, MEM_PWR, PCH_PWR. . . Operating voltage

CPU_PWRGD, MEM_PWRGD, SYS_PWRGD. . . control signal

CPU_RESET_N. . . Reset signal

DC. . . DC power supply

POST. . . Boot self test code

P _in . . . Input power

P _SB . . . Standby power

SLP_S3. . . Sleep control signal

Claims (20)

A boot detection circuit is applicable to a computer system, comprising: a display device; and a controller coupled to the display device for performing a boot self-test program according to a basic input/output system code of the computer system Providing a system health code to the display device, wherein the system health code is used to indicate whether an operating voltage of the component in the computer system and an instant clock are normal. The boot detection circuit of claim 1, wherein when the computer system executes the boot self test procedure, the controller provides a boot self test code corresponding to the boot self test program to the display device. The boot detection circuit of claim 2, wherein the system health code is used to indicate whether the standby power of the computer system is normal, and the clock signal of the component in the computer system is 32.768 Hz. The boot detection circuit of claim 3, wherein the operating voltage of the component in the computer system is operated by a central processing unit, a memory, and a peripheral device control center generated by a power management module of the computer system. Voltage. The boot detection circuit of claim 4, wherein the system health code is used to indicate whether the control signals of the central processing unit, the memory, and the peripheral device control center are normal. The boot detection circuit of claim 2, wherein the controller further stores a previous basic input/output system code, and The system health code is further used to indicate whether the stored previous basic input/output system code is the same as the basic input/output system code. The boot detection circuit of claim 2, wherein the display device comprises a plurality of light emitting diodes. A computer system comprising: a central processing unit; a memory; a peripheral device control center; and a boot detection circuit coupled to the central processor, the memory, and the peripheral device control center for performing a boot Detecting a program to indicate whether the instant clock of the computer system is normal, and after completing the boot detection procedure, providing a reset signal to the central processor, so that the central processor performs a boot according to a basic input/output system code Self-testing program. The computer system of claim 8, wherein the boot detection circuit comprises: a display device; and a controller coupled to the display device for providing a system corresponding to the result of the boot detection process The health code is to the above display device. The computer system of claim 9, wherein the system health code is used to indicate whether the standby power of the computer system is normal, and the instantaneous clock of the component in the computer system is a clock signal of 32.768 Hz. For example, the computer system described in claim 10, wherein The system health code system is further configured to indicate whether the operating voltages of the central processing unit, the memory, and the peripheral device control center are normal. The computer system of claim 11, wherein the system health code is used to indicate whether the control signals of the central processing unit, the memory, and the peripheral device control center are normal. The computer system of claim 11, wherein when the central processor executes the boot self-test program according to the basic input/output system code, the controller further provides a boot self corresponding to the boot self-test program. Test the code to the above display device. The computer system of claim 13, wherein the controller further stores a previous basic input/output system code, and the system health code is further used to indicate whether the stored previous basic input/output system code is the same. The above basic input and output system code. The computer system of claim 13, wherein the display device comprises a plurality of light emitting diodes. A booting detection method is applicable to a computer system, wherein the computer system includes a boot detection circuit, and the boot detection method includes: performing a boot detection program by using one of the boot detection circuits, and performing the boot detection circuit a display device for displaying a system health code corresponding to the result of the boot detection process; and, after completing the boot detection process, providing a reset signal to a central processor of the computer system by the controller, So that the central processing unit executes a boot self-test program according to a basic input/output system code; The system health code is used to indicate whether the operating voltage of the components in the computer system and the instant clock are normal. The booting detection method of claim 16, further comprising: providing a boot self test code corresponding to the boot self test program to the display device by using the controller when performing the boot self test procedure . The power-on detection method according to claim 17, wherein the system health code is used to indicate whether the standby power of the computer system is normal, and the clock signal of the component in the computer system is 32.768 Hz. . The boot detection method of claim 17, wherein the controller further stores a previous basic input/output system code, and the system health code is further used to indicate whether the stored previous basic input/output system code is stored. Same as the above basic input and output system code. The power-on detecting method according to claim 17, wherein the display device comprises a plurality of light-emitting diodes.