TWI532319B - Triangular wave generating circuit providing clock synchronization - Google Patents

Description

Triangle wave generating circuit with clock signal synchronization

The present invention relates to a triangular wave generating circuit, and more particularly to a triangular wave generating circuit synchronized with an external clock signal.

The triangular wave generating circuit generates a triangular wave signal by charging and discharging a capacitor. The triangular wave generating circuit can be applied to many circuits, one of which is to convert an analog voice signal into a pulse width modulated signal in a class-D power amplifier.

The first figure shows a circuit 10 for generating a triangular wave signal VOUT using a square wave signal VIN. The accuracy of the triangular wave signal can affect the performance of the device using the triangular wave signal, such as the performance of a pulse width modulation (PWM) device. In this figure, the switching frequency fsw of the triangular wave signal VOUT is equal to 1/(TU+TD), where TU is the rising time of the triangular wave signal VOUT from VL to VH, and TD is the falling time of the triangular wave signal VOUT from VH to VL. The rise time TU is equal to C x (VH - VL) / IC, where C is the capacitance of capacitor C1 across operational amplifier 12, and IC is the charge current provided by current source I1. Similarly, the fall time TD is equal to C × (VH - VL) / ID, where ID is the discharge current provided by the current source I2. Hypothetical IC Equal to the ID, the switching frequency fsw is equal to IC/(2 × C × (VH - VL)). From this equation, it is known that the triangular wave switching frequency fsw is proportional to IC and ID, and inversely proportional to the triangular wave amplitude (VH-VL).

The second figure is a schematic diagram of the potential problem of the triangular wave generating circuit 10 of the first figure. As shown in the second figure, in the problem 1, if the current source does not match, that is, if the current IC is greater than the ID or the current ID is greater than the IC, the triangular wave signal VOUT will not be switched at the predetermined limit peaks VH and VL. Similarly, question 2 reveals that the triangular wave waveform when the duty cycle of the square wave is not the ideal value, the problem 2 often occurs because the internal clock signal is not synchronized with the external clock signal. Synchronizing the internal clock signal with the external clock signal is a very important thing, such as the 5.1 channel or 7.1 channel D-type amplifier voice system application. If the switching frequency is not the same, the jitter of the frequency will appear in the sound band.

Accordingly, it is necessary to propose a triangular wave generating circuit to improve the above problem.

The invention provides a triangular wave generating circuit with clock signal synchronization. The triangular wave generating circuit comprises a capacitor, a first constant current source, a second constant current source, a third constant current source, a fourth constant current source, a first switching unit, a second switching unit, and a high / low level limit unit, one clock signal generator, and one phase detection unit. The first and second constant current sources are used to charge the capacitor. The third and fourth constant current sources are used to discharge the capacitor. The first switching unit includes a first switch and a first And a second switch, the first switching unit is configured to control a coupling state of the first and third constant current sources to the capacitor in response to an internal clock signal. The high/low level quasi-limiting unit includes a first and a second comparing unit, wherein the first comparing unit is configured to compare the triangular wave signal with a high level reference voltage, and generate a one when the triangular wave signal reaches the high level reference voltage And outputting a signal, the second comparing unit is configured to compare the triangular wave signal with a low level reference voltage, and generate an output signal when the triangular wave signal reaches the low level reference voltage. The clock signal generator is configured to generate the internal clock signal in response to the output signal of the first comparing unit and the output signal of the second comparing unit. The phase detecting unit is configured to receive an externally supplied clock signal and the internal clock signal, and generate a first phase signal and a second according to a phase difference between the externally supplied clock signal and the internal clock signal Phase signal. The second switching unit includes a third switch and a fourth switch, the third switch is configured to control the coupling state of the second constant current source and the capacitor in response to the first phase signal, and the fourth switch And responsive to the second phase signal to control a coupling state of the fourth constant current source and the capacitor.

10‧‧‧ Triangle wave generating circuit

12‧‧‧Operational Amplifier

30,30'‧‧‧ triangle wave signal generator

32‧‧‧Switch unit

33‧‧‧Second drive circuit

34‧‧‧High and low level limit circuit

242‧‧‧ Comparator

344‧‧‧ Comparator

36‧‧‧Internal clock signal generator

38‧‧‧ phase detection unit

82‧‧‧Switching current array

84‧‧‧Switching current array

86‧‧‧Comparative circuit

C1‧‧‧ capacitor

I1-IN‧‧‧ constant current source

M1, M2, M3, M4‧‧ ‧ switch

SW1-SWN‧‧‧ switch

S100-S110‧‧‧Steps

The first figure is a circuit that conventionally generates a triangular wave signal using a square wave signal.

The second figure is a schematic diagram of the potential problem of the triangular wave generating circuit of the first figure.

The third figure shows a circuit diagram of a triangular wave signal generator incorporating an embodiment of the present invention.

The fourth figure shows a possible operational waveform of the phase detecting unit shown in the third figure.

The fifth figure shows another possible operational waveform of the phase detecting unit shown in the third figure.

Figure 6 shows a waveform diagram of the triangular wave signal generator incorporating an embodiment of the present invention.

The seventh figure shows a waveform diagram of the triangular wave signal generator incorporating another embodiment of the present invention.

The eighth diagram shows a circuit diagram of a triangular wave signal generator incorporating an embodiment of the present invention.

The ninth diagram shows a circuit diagram of the switching current arrays in connection with an embodiment of the present invention.

Figure 11 is a flow chart showing the operation of the triangular wave signal generator in accordance with an embodiment of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, "coupling The term "connected" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

The third diagram shows a circuit diagram of a triangular wave signal generator 30 incorporating an embodiment of the present invention. As shown in the third figure, the triangular wave signal generator 30 includes a capacitor C1, a pair of matched charging/discharging constant current sources I1 and I2, and a switching unit 32. The term "matching" as used herein means that the current values of the charge/discharge constant current sources I1 and I2 are substantially the same. The switching unit 32 includes two switches M1 and M2 controlled by an internal clock signal. The two switches M1 and M2 are switched in a complementary manner, so when the switch M1 is turned on, the switch M2 is turned off, and vice versa. In addition, when the switch M1 is turned on, the constant current source I1 is coupled to the capacitor C1. When the switch M2 is turned on, the constant current source I2 is coupled to the capacitor C1.

Referring to the third diagram, the triangular wave signal generator 30 further includes a high and low level limit circuit 34 including two comparators 342 and 344. The comparator 342 compares a signal VTRI on the capacitor C1 with a high level reference voltage VH, and the comparator 342 compares the signal VTRI with a low level reference voltage VL. The output signal CPH of the comparator 342 and the output signal CPL of the comparator 344 are supplied to an internal clock signal generator 36. In the present embodiment, the signal generator 36 is an RS locker. The signal generator 36 provides an internal clock signal ICK to control the two switches in the switching unit 32 according to the comparison result. M1 and M2.

Referring to the third figure, the triangular wave signal generator 30 further includes a pair of matched charge/discharge constant current sources I3 and I4 and a switching unit 33. The switching unit 33 includes two switches M3 and M4. The switch M3 is controlled by an output signal DP of a phase detecting unit 38, and the switch M4 is controlled by an output signal DN of the phase detecting unit 38. When switch M3 is turned on, switch M4 is off and vice versa. In addition, when the switch M3 is turned on, the constant current source I3 is coupled to the capacitor C1. When the switch M4 is turned on, the constant current source I4 is coupled to the capacitor C1.

As described above, the operation of the switching unit 33 is controlled by the phase detecting unit 38. The phase detecting unit 38 receives an externally supplied clock signal ECK and the internal clock signal ICK, and generates the phase signals DP and DN according to the phase difference between the clock signal ECK and the clock signal ICK. When the signal DP is at the logic 0 level, the switch M3 in the switching unit 33 is turned on. When the signal DN is at the logic 1 level, the switch M4 in the switching unit 33 is turned on.

The fourth figure shows a possible operational waveform of the phase detecting unit 38 shown in the third figure. In the fourth figure, the phase of the external clock signal ECK leads the phase of the internal clock signal ICK, that is, The rising edge of the external clock signal ECK leads the rising edge of the internal clock signal ICK, and the falling edge of the external clock signal ECK leads the falling edge of the internal clock signal ICK. The phase detecting unit 38 generates the phase signal DP when the rising edge of the external clock signal ECK leads the rising edge of the internal clock signal ICK. When the external clock signal ECK drops The phase detecting unit 38 generates the phase signal DN when the edge leads the falling edge of the internal clock signal ICK. Therefore, the width W1 of the phase signal DP and the width W2 of the phase signal DN are determined by the phase difference between the external clock signal ECK and the internal clock signal ICK.

The fifth figure shows another possible operational waveform of the phase detecting unit 38 shown in the third figure. In the fifth figure, the phase of the external clock signal ECK lags behind the phase of the internal clock signal ICK, that is, The rising edge of the external clock signal ECK lags behind the rising edge of the internal clock signal ICK, and the falling edge of the external clock signal ECK lags behind the falling edge of the internal clock signal ICK. The phase detecting unit 38 generates the phase signal DP when the rising edge of the external clock signal ECK falls behind the rising edge of the internal clock signal ICK. The phase detecting unit 38 generates the phase signal DN when the falling edge of the external clock signal ECK falls behind the falling edge of the internal clock signal ICK. Therefore, the width W3 of the phase signal DP and the width W4 of the phase signal DN are determined by the phase difference between the external clock signal ECK and the internal clock signal ICK.

The operation of the triangular wave signal generator 30 of the present invention will now be described with reference to the third to seventh figures, wherein the sixth figure shows a waveform diagram of the triangular wave signal generator 30 in combination with an embodiment of the present invention. In this embodiment, the phase of the external clock signal ECK is advanced by the phase of the internal clock signal ICK.

Referring to the sixth figure, before the time t1, when the clock signal ICK is at the logic 0 level, the capacitor C1 is charged by the current flowing through the constant current source I1. Electrically, the voltage VTRI across the capacitor C1 rises linearly. When the phase detecting unit 38 detects the phase difference between the external clock signal ECK and the internal clock signal ICK, the phase of the external clock signal ECK leads the internal clock in response to the phase difference between the external clock signal ECK. The phase of the signal ICK is generated to produce the phase signal DP, which causes the constant current source I3 to charge the capacitor C1. Since the slope of the rising portion of the triangular wave signal is proportional to the direct current flowing through the capacitor, the signal VTRI quickly reaches the high level reference voltage VH at time t2. When the signal VTRI reaches the reference voltage VH, the output signal CPH of the comparator 342 outputs a logic 1 level, so that the RS latch 36 outputs a clock signal ICK having a logic 1 level.

After time t2, switches M1 and M3 are turned off, and switch M2 is turned on in response to clock signal ICK, and the capacitor is discharged by the current flowing through constant current source I2. Therefore, the voltage VTRI across the capacitor C1 decreases linearly. At time t3, when the phase detecting unit 38 detects the phase difference between the external clock signal ECK and the internal clock signal ICK, the phase of the external clock signal ECK is advanced in the internal clock. The phase of the signal ICK is generated to produce the phase signal DN, which causes the constant current source I4 to be added to the constant current source I2 to discharge the capacitor C1. Higher DC current values result in shorter ramp time intervals. Therefore, the signal VTRI will quickly reach the low level reference voltage VL at time t4. When the signal VTRI reaches the reference voltage VL, the output signal CPL of the comparator 344 outputs a logic 1 level, so that the RS latch 36 outputs a clock signal ICK having a logic 0 level.

The above operation is repeated, so that the voltage VTRI on the capacitor C1 is generated in a triangular wave manner. As described above, the triangular wave signal generator 30 synchronizes the internal clock signal ICK to the externally supplied clock by detecting the phase difference between the external clock signal ECK and the internal clock signal ICK. Signal ECK. When the phase of the external clock signal ECK leads the phase of the internal clock signal ICK, the slope of the signal VTRI increases according to the detection result, thereby shortening the ramp period. In this way, the internal clock signal ICK is synchronized to the externally supplied clock signal ECK after several cycles.

The seventh diagram shows a waveform diagram of the triangular wave signal generator 30 in combination with another embodiment of the present invention. In this embodiment, the phase of the external clock signal ECK lags behind the phase of the internal clock signal ICK.

Referring to the seventh figure, before time t1, the clock signal ICK is at the logic 0 level, and the capacitor C1 is charged by the current flowing through the constant current source I1, which makes the voltage VTRI on the capacitor C1 linear. Rise. At time t1, the signal VTRI will reach the high level reference voltage VH, which causes the output signal CPH of the comparator 342 to output a logic 1 level, and causes the RS latch 36 to output a clock signal having a logic 1 level. ICK. Therefore, the switch M1 will be turned off and the switch M2 will be turned on, so that the current source I2 will be coupled to the capacitor C1. After the time t1, the phase detecting unit 38 detects a phase difference between the external clock signal ECK and the internal clock signal ICK, and generates the phase signal DP according to the detection result, which causes a constant current. The source I3 is coupled to the capacitor C1. In this embodiment, the current value of the current source I3 is greater than the current value of the current source I2. Therefore, the capacitor C1 is charged by the net current I3-I2.

The clock signal ECK enters a logic 1 level at time t2, so the phase signal DP also returns to a logic 1 level. Next, the switch M3 is turned off, and the capacitor C1 is discharged by the current flowing through the constant current source I2, which causes the voltage VTRI across the capacitor C1 to decrease linearly. At time t3, the signal VTRI will reach the low level reference voltage VL, which causes the output signal CPL of the comparator 344 to output a logic 1 level, and the RS latch 36 outputs a clock signal having a logic 0 level. ICK. Therefore, the switch M2 is turned off and the switch M1 is turned on, so that the current source I1 is coupled to the capacitor C1. After the time t3, the phase detecting unit 38 detects a phase difference between the external clock signal ECK and the internal clock signal ICK, and generates the phase signal DN according to the detection result, which causes the current source to be fixed. I4 begins to discharge the capacitor C1. In this embodiment, the current value of the current source I4 is greater than the current value of the current source I1. Therefore, the capacitor C1 is charged by the net current I4-I1.

The clock signal ECK enters a logic 0 level at time t4, so the phase signal DN also returns to a logic 0 level. Then, the switch M4 is turned off, and the capacitor is charged by the current flowing through the constant current source I1. The capacitor is charged and discharged in a similar manner after time t5, so that the voltage VTRI across the capacitor C1 is generated in a triangular wave manner.

As described above, the triangular wave signal generator 30 synchronizes the internal clock signal ICK to the externally supplied clock by detecting the phase difference between the external clock signal ECK and the internal clock signal ICK. signal ECK. When the phase of the external clock signal ECK falls behind the phase of the internal clock signal ICK, the capacitor C1 maintains the previous charge/discharge state in the phase difference interval. Since the slope of the signal VTRI is generally slow, the ramp period is increased. In this way, the internal clock signal ICK is synchronized to the externally supplied clock signal ECK after several cycles.

In the above embodiment, the capacitor C1 is additionally charged and discharged by the constant current sources I3 and I4. However, in various embodiments, the capacitor C1 can also be additionally charged and discharged by the variable current source in a phase difference interval. The eighth diagram shows a circuit diagram of a triangular wave signal generator 30' incorporating an embodiment of the present invention. Referring to the eighth diagram, a comparison circuit 86 compares the pulse width of the phase signal DP with a predetermined time interval TSET to generate a digital code composed of a plurality of bits C0 to CN. At the same time, the comparison circuit 86 compares the pulse width of the phase signal DN with the predetermined time interval TSET to generate a digital code composed of a plurality of bits B0 to BN.

Referring to the eighth figure, after the switching current array 82 receives the digital bits C0 to CN, the charging current is supplied according to the digital bits C0 to CN. After the switching current array 84 receives the digits B0 to BN, the discharge current is supplied according to the digits B0 to BN. The ninth diagram shows a circuit diagram of the switching current arrays 82 and 84 in connection with an embodiment of the present invention. Referring to the ninth diagram, the switching current array 82 includes a plurality of identical current sources I1 to IN, each of which delivers the same current I. The switching current array 82 further includes a plurality of switches SW1 to SWN corresponding to the plurality of current sources I1 to IN. For example, the switch SW1 is responsible for controlling the coupling state of current source I1 and capacitor C1. The circuit configuration of the switching current array 84 approximates the current array 82. Referring to the ninth diagram, the switching current array 84 includes a plurality of identical current sources I1 to IN, each of which delivers the same current I. The switching current array 84 further includes a plurality of switches SW1 to SWN corresponding to the plurality of current sources I1 to IN.

The tenth diagram shows a flow chart of the operation of the triangular wave signal generator 30' in conjunction with an embodiment of the present invention. The flow begins in step S100. Please refer to the eighth to tenth figures for the following description. In step S102, the phase detecting unit 38 receives the external clock signal ECK and the internal clock signal ICK, and generates the phase signal DP according to the phase difference between the two. In step S104, the comparison circuit 86 compares the pulse width of the phase signal DP with a predetermined time interval TSET to generate a plurality of digits C0 to CN. In one embodiment, the digits C0 to CN are responsive to a difference between a pulse width of the phase signal DP and the predetermined time interval TSET. In another embodiment, the comparison circuit 86 compares the pulse width of the phase signal DP with a plurality of predetermined time intervals TSETI through TSETN to produce a plurality of digital bits C0 through CN.

Next, in step S106, if the pulse width of the phase signal DP is greater than the predetermined time interval TSET, the total current value flowing through the current array 82 is increased to charge the capacitor C1. Then, the flow returns to step S104. If the pulse width of the phase signal DP after the increase in the charging current is less than the predetermined time interval TSET, the flow is ended.

Referring to the eighth to tenth embodiments, in an embodiment of the present invention, The capacitor C1 is initially charged and discharged only by one of the current sources 82 and one of the current arrays 84. Next, in step S106, if the pulse width of the phase signal DP is greater than the predetermined time interval TSET (eg, 100 ns) after several clock cycles, another current source in the current array 82 is coupled to the Capacitor C1 to increase the charging current. After a number of clock cycles, the comparison circuit 86 compares the pulse width of the phase signal DP again with the predetermined time interval TSET. If the pulse width of the phase signal DP is still greater than the predetermined time interval TSET, it indicates that the total charging current flowing through the current array 82 cannot reduce the phase difference between the external clock signal ECK and the internal clock signal ICK. Therefore, another switch in the current array 82 is turned on to couple a further current source to the capacitor C1 to increase the charging current. If the pulse width of the phase signal DP is still greater than the predetermined time interval TSET after a number of cycles, then another switch in the current array 82 is turned on to couple a further current source to the capacitor C1 to increase the charging current. The switches are continuously turned on to sequentially connect different current sources to the capacitor C1 to increase the charging current until the pulse width of the phase signal DP is less than the predetermined time interval TSET. In this way, the pulse width of the phase signal DP will be less than the predetermined time interval TSET.

In the above embodiment, the switches SW1 to SWN in the current array 82 are sequentially turned on to increase the total charging current, and the current array 84 only has the switch SW1 turned on to increase the discharge current. In another embodiment, the switches SW1 through SWN in the current array 84 are sequentially turned on to increase the total discharge current, and the current array 82 has only the switch SW1 turned on to increase the charging current. However, in still another embodiment, the switches SW1 to SWN in the current array 82 and the switches SW1 to SWN in the current array 84 are sequentially turned on according to the external clock signal ECK and the internal clock signal. The phase difference between ICK increases the total charge and total discharge current. In this way, the pulse width of the phase signal DP is gradually reduced until it is less than the predetermined time interval TSET.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

30‧‧‧ Triangle Wave Signal Generator

32‧‧‧Switch unit

33‧‧‧Second drive circuit

34‧‧‧High and low level limit circuit

342‧‧‧ Comparator

344‧‧‧ Comparator

36‧‧‧Internal clock signal generator

38‧‧‧ phase detection unit

C1‧‧‧ capacitor

I1, I2, I3, I4‧‧‧ constant current source

M1, M2, M3, M4‧‧ ‧ switch

Claims (9)

A triangular wave generating circuit with clock signal synchronization, comprising: a capacitor having an output terminal for providing a triangular wave signal; first and second constant current sources for charging the capacitor; third and fourth constant current sources Discharging the capacitor; a first switching unit includes a first switch and a second switch, the first switching unit is configured to control the first and the third predetermined in response to an internal clock signal a state in which the current source is coupled to the capacitor; a high/low level limiting unit includes a first and a second comparing unit, the first comparing unit is configured to compare the triangular wave signal with a high level reference voltage, and When the triangular wave signal reaches the high level reference voltage, an output signal is generated, and the second comparison unit is configured to compare the triangular wave signal with a low level reference voltage, and generate an output signal when the triangular wave signal reaches the low level reference voltage; a pulse signal generator responsive to the output signal of the first comparison unit and the output signal of the second comparison unit to generate the internal clock signal a phase detecting unit configured to receive an externally supplied clock signal and the internal clock signal, and generate a first phase signal and a first phase according to a phase difference between the externally supplied clock signal and the internal clock signal a second phase switching unit, and a second switching unit including a third switch and a fourth switch, the third switch responsive to the first phase signal to control the second constant current source a state of being coupled to the capacitor, and the fourth switch is responsive to the second phase signal to control a coupling state of the fourth constant current source to the capacitor. The triangular wave generating circuit of claim 1, wherein the phase detecting unit generates the first phase signal when an rising edge of the externally supplied clock signal leads the rising edge of the internal clock signal. The triangular wave generating circuit of claim 1, wherein the phase detecting unit generates the second phase signal when a falling edge of the externally supplied clock signal leads the falling edge of the internal clock signal. According to the triangular wave generating circuit of claim 1, wherein the current value of the second constant current source is greater than the current value of the third constant current source, and the rising edge of the externally supplied clock signal lags behind the internal clock signal The phase detecting unit generates the first phase signal when the edge is raised. According to the triangular wave generating circuit of claim 1, wherein the current value of the fourth constant current source is greater than the current value of the first constant current source, and the falling edge of the externally supplied clock signal lags behind the internal clock signal The phase detecting unit generates the second phase signal when the edge is lowered. The triangular wave generating circuit of claim 1, further comprising: a first comparing unit for comparing a pulse width of the first phase signal with a plurality of predetermined time intervals, and a pulse wave of the first phase signal Generating a first digit code when the width is greater than the predetermined time interval; and a first switching current array comprising a plurality of identical constant current sources and a plurality of switches corresponding to the constant current sources; The constant current sources in the first switching current array are sequentially coupled to the capacitor in response to the first digital code. According to the triangular wave generating circuit of claim 1, further comprising: a second comparing unit, configured to compare a pulse width of the second phase signal with a plurality of predetermined time intervals, and a pulse wave of the second phase signal Generating a second digit code when the width is greater than the predetermined time interval; and a second switching current array comprising a plurality of identical constant current sources and a plurality of switches corresponding to the constant current sources; wherein the second switching current The constant current sources in the array are coupled to the capacitor in sequence in response to the second digital code. The triangular wave generating circuit of claim 1, further comprising: a first comparing unit for comparing a pulse width of the first phase signal with a predetermined time interval, and according to a pulse width of the first phase signal And a phase difference value of the predetermined time interval to generate a first digit code; and a first switching current array comprising a plurality of identical constant current sources and a plurality of switches corresponding to the constant current sources; wherein the first switching The constant current sources in the current array are coupled to the capacitor in sequence in response to the first digital code. The triangular wave generating circuit of claim 1, further comprising: a second comparing unit for comparing a pulse width of the second phase signal with a predetermined time interval, and according to a pulse width of the second phase signal And a phase difference value of the predetermined time interval generates a second digit code; a second switching current array comprising a plurality of identical constant current sources and a plurality of switches corresponding to the constant current sources; wherein the constant current sources in the second switching current array are responsive to the second digital code The capacitors are sequentially coupled to the capacitor.