TWI529919B - ?semiconductor array arrangement including carrier source - Google Patents

Description

Semiconductor array arrangement including carrier supply

The present invention relates to a high density memory device, and more particularly to a memory device that can include a plurality of thin film transistor memory cells arranged to form a three dimensional (3D) array.

The design of a high density memory device includes a plurality of arrays of flash memory cells or a plurality of other types of memory cells. In some examples, a plurality of memory cells including a plurality of thin film transistors can be arranged in 3D architectures.

Three-dimensional memory devices have evolved into a variety of different configurations, including a plurality of films and a plurality of bit lines spaced apart by an insulating material. The known three-dimensional vertical gate structure uses a plurality of thin film transistors as a three-dimensional memory device of a plurality of memory cell types, for example, as described in U.S. Patent Application Serial No. 13/078,311, filed on April 1, 2011. The invention is entitled "Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures" (U.S. Patent Publication No. US 2012/0182806 A1, published in 2012 July 19, the inventor is the two US patents of Chen Shihong and Lu Yanting. The shareholder of the application is jointly owned and can be used as a reference. The three-dimensional vertical gate structure includes a plurality of film strip stacks and a word line structure overlying the stack such that the word line structure portion extends vertically between the plurality of stacks, the portion of the word line structure extends, and the plurality of film strips The intersection is used as a plurality of word lines in the memory cell. A plurality of thin film bit lines may be lightly doped and have no body contact in this or other types of memory structures, so that a plurality of thin film bit lines are insulated from the source of the charge carriers during operation of the device. In the case of insufficient supply of the hole carrier, the operational efficiency of the structure is impaired.

Accordingly, it is desirable for the related art to provide an array structure for higher operational efficiency in a three-dimensional integrated circuit.

The present invention provides a structure for a thin film transistor substrate memory device that satisfies the supply requirements of the hole carrier.

In one embodiment, a memory can include a diode, a sequence of arrangements, a first source line, a second source line, a plurality of word lines, and a circuit. The diode has a first end and a second end. The sequence arrangement includes a plurality of memory cells. The sequence arrangement is, for example, coupled to a bit line in a NAND string by a first switch on a first end, and coupled to a second switch on a second end. The first end of the diode. The first source line and the second source line that are individually driven are respectively coupled to the first end and the second end of the diode. A plurality of word lines are coupled to the corresponding memory cells. The circuit is coupled to the first and second source lines, and the circuit biases the first and second source lines under different bias conditions according to an operation mode.

In another embodiment, the circuitry is configured to employ an erase bias arrangement in a selected memory cell or a block of a plurality of memory cells to induce hole generation. The erase bias arrangement for the n-type channel includes a source side bias on the second source line, the source side bias biasing the diode in a forward direction to provide a source of holes such that one or more The strip line is erased. The erase bias arrangement can also include the first source line remaining floating, applying an erase voltage across the plurality of word lines to induce hole generation.

In still another embodiment, the circuit biasing arrangement can apply a bias on a source side of the first source line to allow the second source line to remain floating or be programmed during programming operation. A bias is applied to bias the diodes in a reverse direction.

Different embodiments include a three-dimensional memory arrangement of a three-dimensional vertical gate structure, wherein the diodes as described above can be used in some modes of operation of the device to provide a carrier supply. In general, the embodiments are provided for a hole carrier supply of a plurality of bit lines of a semiconductor material that may be insulated from a conductive substrate and may not have body contact.

In order to better understand the other aspects and advantages of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10‧‧‧Array

11‧‧‧ column decoder

12‧‧‧ bit line

13‧‧‧ page buffer

14‧‧‧ overall bit line

15, 17‧‧ ‧ busbar

16, 18, 20‧‧‧ blocks

19‧‧‧ State Machine

825-1, 825-2, 825-3‧‧‧N+ areas

325, 326, 327, 356, 610, 611, 612, 857-1, 859-2, 859-8, 869-1, 869-2, 869-8‧ ‧ inter-layer conductor

332, 333, 342, 343, 353, 592, 593, 655, 656, ‧ ‧ PN junction

410, 410A, 420, 420A, 430‧‧ ‧ stepped contact

500‧‧‧Upper

501, 502, 503‧‧ ‧ through holes

509‧‧‧Top insulating material layer

510‧‧‧Second active material layer

511‧‧‧First active material layer

512‧‧‧Semiconductor materials

519‧‧‧Charge storage structure

524‧‧‧N+ implant

555, 579‧‧‧ mask

556‧‧‧P+ implant

565‧‧‧Polysilicon layer

598‧‧‧ Telluride layer

600, 855‧‧‧insulating filling layer

601, 650‧‧ ‧ interlayer dielectric filling layer

651‧‧‧N+ cylinder

652‧‧‧N+ part

653, 654‧‧‧P+

661‧‧‧P+ cylinder

23‧‧‧ data input line

24‧‧‧Other circuits

25‧‧‧Integrated circuit

102, 103, 104, 105, 112, 113, 114, 115, 202, 202-1, 202-2, 202-8, 203, 203-2‧‧ ‧ bit line

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A, 202-A~202-D, 203-A~203-D, 220, 223, 330, 331‧ ‧ contact pads

109, 119, 119-A1, 119-A2, 119-D1, 119-D2‧‧‧ tandem selection line gate structure

125-0~125-N, WL‧‧‧ character line

126, 127, GSL‧‧‧ grounding selection line

128‧‧‧ source line

205-1~205-8, 210-A~210-D, 211-A~211-D‧‧‧ Serial connection

219-1~219-8‧‧‧First source line contact

221-1~221-8‧‧‧Second source line contact

220A~220D, 605, 606, 607, 650-1~650-8, 651-1~651-8, 850-1~850-8‧‧‧ openings

224, 351, 557, 558, 724, 824‧‧‧P+ areas

302‧‧‧Substrate

225, 350‧‧‧ joint

305‧‧‧Insulation

320, 345, 346, 355, 550-1, 550-2, 550-8, 651, 660, 665‧‧ ‧ cylinder

321, 524-1, 524-2, 524-3, 590, 591, 725-1, 725-2, 725-3, 750-1~750-8, 751-1~751-8‧‧‧Interlayer connection layer

800‧‧‧ diode

801‧‧‧Diode N-type end

804-1~804-4‧‧‧Contact

824-1, 824-2, 825-1, 825-2‧‧‧ tandem selection switch

814-1~814-4‧‧‧ Grounding selection switch

840, 842, 845, 847‧‧‧ memory cells

Between 859-1, 859-2, 859-8, 866-1, 869-2, 869-8‧‧ ‧ interlayer conductor

861, 866‧‧‧ first end

860, 865‧‧‧ second end

SSL‧‧‧ tandem selection line

BLL1, BLL2‧‧‧ bit line layer

GSL‧‧‧ Grounding selection line

SC‧‧‧Source contact

PNS, PNS1, PNS2‧‧‧PN junction source extreme

P1PNS‧‧‧Upper diode source extreme

P2PNS‧‧‧lower diode source extreme

X, Y, Z‧‧ Direction

ML1, ML2, ML3‧‧‧ metal layer

Blocks A, B, C, D‧‧

1 is a perspective view of a three-dimensional vertical gate NAND memory array structure, wherein the three-dimensional vertical gate NAND memory array includes no body contact without junction Film bit line.

2 is a layout view of a three-dimensional vertical gate memory including a diode structure according to an embodiment of the present invention.

2A, 2B, and 2C are diagrams showing a diode structure suitable for use in the three-dimensional memory as in Fig. 2.

Figure 3 is a layout diagram of an intermediate structure in a process for fabricating a memory structure similar to Figure 2 having a diode structure as in Figure 2A.

3A and 3B are cross-sectional views shown in the process stage of the layout diagram of Fig. 3.

Figure 4 is a layout diagram showing another intermediate structure in a process for fabricating a memory structure similar to Figure 2 having a diode structure as in Figure 2A.

4A, 4B are cross-sectional views showing additional stages in accordance with the process stages of the floor plan of FIG. 4.

Figure 5 is a layout diagram showing another intermediate structure in a process for fabricating a structure similar to that in Figure 2.

5A, 5B are cross-sectional views showing additional stages in accordance with the process stages of the layout of Figure 5.

Figure 6 is a layout diagram showing another intermediate structure in a process for fabricating a structure similar to that in Figure 2.

The 6A, 6B, 6C, and 6D drawings illustrate additional stages of the cross-sectional view according to the process stages of the layout of FIG.

Figure 7 is a diagram showing the structure for making a structure similar to that shown in Figure 2 for Figure 6. A layout of an intermediate structure after the process.

7A, 7B are cross-sectional views showing additional stages in accordance with the process stages of the layout of Figure 7.

Figure 8 is a layout diagram showing another intermediate structure in a process for fabricating a memory structure similar to Figure 2 having a diode structure as in Figure 2B.

8A, 8B are cross-sectional views showing additional stages in accordance with the process stages of the layout of Fig. 8.

Fig. 9 is a layout view showing an intermediate structure after the process of Fig. 8 is performed for manufacturing a process similar to the structure of Fig. 2.

Figures 9A and 9B show cross-sectional views of additional stages in accordance with the process stages of the layout of Figure 9.

Figure 10 is a layout diagram showing another intermediate structure in a process for fabricating a memory structure similar to Figure 2 having a diode structure as shown in Figure 2C.

10A, 10B are cross-sectional views showing additional stages in accordance with the process stages of the floor plan of FIG.

Fig. 11 is a layout view showing another intermediate structure after the process of Fig. 10 is performed for manufacturing a process similar to the structure of Fig. 2.

11A, 11B are cross-sectional views showing additional stages in accordance with the process stages of the floor plan of FIG.

Figure 12 is a schematic diagram of a three-dimensional NAND structure similar to Figure 2, showing the bias arrangement for a programming operation.

Figure 13 is a schematic diagram of a three-dimensional NAND structure similar to Figure 2, shown in the figure A bias arrangement for an erase operation.

Figure 14 is a schematic diagram of a three-dimensional NAND structure similar to Figure 2, showing an alternative erase bias arrangement.

Figure 15 is a schematic diagram of a three-dimensional NAND structure similar to Figure 2, showing a read bias arrangement.

Figure 16 is a schematic diagram of another three-dimensional NAND structure showing one embodiment of a bit line stack of a circuit having a diode, the three-dimensional NAND structure being biased for a programming operation.

Figure 17 is a simplified block diagram of an integrated circuit including a three-dimensional memory system including a carrier supply of one embodiment.

Various embodiments are described in detail in conjunction with the accompanying drawings.

1 is a perspective view of a three-dimensional NAND memory array structure, which is commonly owned by the assignee of the present application, which is incorporated herein by reference. Case No. 078,311. In order to better represent the additional structure, the insulating material is removed from the illustration. For example, a plurality of insulating layers between a plurality of bit lines (eg, 112-115) in a stack and between a plurality of bit line stacks are removed.

The multilayer array is formed on an insulating layer and includes a plurality of word lines (Word Lines, WLs) 125-0 to 125-N, and the plurality of word lines are conformal to the plurality of stacked lines. The plurality of stacks includes a plurality of bit lines 112, 113, 114, 115, and the plurality of bit lines includes a plurality of impurity dopings having a relatively low concentration, Or other thin film strip of semiconductor material of intrinsic semiconductor, the strip of semiconductor material film can be made into a channel in the NAND string. A plurality of memory devices can be configured for n-channel or p-channel operation. In some exemplary configurations, the plurality of bit lines do not include source/drain connections between a plurality of word lines, and are therefore referred to as "no-join" bit lines. And the plurality of bit lines are also not connected to a semiconductor substrate or other semiconductor body, so when a voltage is applied to the plurality of bit lines via a string select or ground select switch, the plurality of bit lines Lines can be considered "floating".

The plurality of bit lines on the same level are electrically coupled together by a contact pad having a landing area in contact with an interlayer conductor. A plurality of contact pads of a plurality of layers as shown in FIG. 1 may be arranged in a stepped structure, and each of the contact pads sequentially disposed on the first step of the structure has a landing zone. A plurality of landing zones for the connection of the plurality of contact pads, and a plurality of interlayer conductors of the plurality of landing zones on the plurality of contact pads may be arranged in a pattern other than a simple step for a desired manufacturing or desired special manufacturing setting.

The word line numbers for the even memory pages shown in the figure are incremented from 0 to N from the back end to the front end of the entire structure. The word line number for odd memory pages is decremented from N to 0 from the back end to the front end of the entire structure.

Contact pads 112A, 113A, 114A, and 115A terminate interleaved plurality of bit lines, in this example contact pads 112A, 113A, 114A, and 115A, for example, terminating bit lines 112, 113, 114, and 115 in the layers. . As shown As shown, these contact pads 112A, 113A, 114A, and 115A are electrically coupled to different word lines for connection to decoding circuitry to select planes in the array. These contact pads 112A, 113A, 114A, and 115A can be patterned while defining a plurality of stacks.

Contact pads 102B, 103B, 104B, and 105B terminate the interleaved plurality of bit lines, in this example, for example, terminating bit lines 102, 103, 104, and 105 in the layers. As shown in the figure, in order to connect to the decoding circuit to select a plane in the array, the contact pads 102B, 103B, 104B, and 105B are electrically connected to different word lines. These contact pads 102B, 103B, 104B, and 105B and the plurality of vias in the landing zone can be patterned while defining a plurality of stacks.

In other examples, all of the bit lines in a block can terminate on a single line contact pad on the same end.

In the illustrated example, all of the bit line stacks are coupled to contact pads 112A, 113A, 114A, and 115A or contact pads 102B, 103B, 104B, and 105B, but not both. The stacking direction of a plurality of bit lines is from the end of the bit line to the end of the source line (bit line end-to-source line end) or from the end of the source line to the end of the bit line (source line end-to -bit line end) One of the two opposite bit directions. For example, the stack of a plurality of bit lines 112, 113, 114, and 115 has a bit direction from the end of the bit line to the end of the source line, and the stack of the plurality of bit lines 102, 103, 104, and 105 has a slave source The end of the pole line to the end of the bit line.

One of a plurality of stacked bit lines 112, 113, 114, and 115 The end system traverses the String Select Line (SSL) gate structure 119, the Ground Select Line (GSL) 126, the word lines 125-0 to 125-N, and the ground selection line 127 and terminates in contact. Pads 112A, 113A, 114A, and 115A, and the other end terminates in source line 128. The stack of complex bit lines 112, 113, 114, and 115 does not extend to contact pads 102B, 103B, 104B, and 105B.

One end of the stack of a plurality of bit lines 102, 103, 104, and 105 passes through the tandem select line gate structure 109, the ground select line 127, the word lines 125-N to 125-0, and the ground select line 126 and terminates The pads 102B, 103B, 104B, and 105B are contacted, and the other end terminates in the source line (covered by another portion of the figure). The stack of bit lines 102, 103, 104, and 105 does not extend to contact pads 112A, 113A, 114A, and 115A.

A layer of memory material separates word lines 125-0 through 125-N from bit lines 112-115 and 102-105. Ground select lines 126 and 127 are similar to the tandem select line gate structure and are conformal to the bit line.

One end of each of the plurality of bit lines terminates in a plurality of contact pads and the other end terminates in a source line. For example, one end of the plurality of bit lines 112, 113, 114, and 115 terminates in contact pads 112A, 113A, 114A, and 115A, and the other end terminates in source line 128. At the proximal end of the figure, the stack of spaced plurality of bit lines terminates at contact pads 102B, 103B, 104B, and 105B, and the stack of spaced plurality of bit lines terminates at a different source line. At the far end of the drawing, the stack of spaced plurality of bit lines terminates at contact pads 112A, 113A, 114A, and 115A, and the stack of spaced plurality of bit lines terminates On a different source line.

A plurality of bit lines and a plurality of string selection lines are formed at a plurality of patterned conductor layers, such as metal layers (ML) ML 1, ML 2, and ML 3 . A plurality of electro-crystalline systems are formed at intersections between a plurality of bit lines (e.g., 112-115) and word lines 125-0 to 125-N. In a plurality of transistors, a bit line (e.g., 113) is used as a channel region in the device.

The tandem selection structure (e.g., 119, 109) can be simultaneously patterned during the process of defining word lines 125-0 through 125-N (as shown in Figure 2). A plurality of electro-crystalline systems are formed at intersections between a plurality of bit lines (e.g., 112-115) and a string selection structure (e.g., 119, 109). In order to select a particular plurality of stacks in the array, a plurality of transistors that are serial select switches are coupled to the decoding circuit.

A charge storage structure layer is disposed at least at the intersection of memory cell formation. The charge storage structure can include a multilayer dielectric charge storage structure, such as a neon-oxynitride-oxygen (SONOS) structure. Known dielectric charge storage structures are bandgap engineered SONOS or "BE-SONOS". The BE-SONOS charge storage structure may comprise a plurality of tunneling layers, such as a tantalum oxide layer having a thickness of about 2 nm, a tantalum nitride layer having a thickness of about 2-3 nm, and a thickness of about 2 3 nm yttrium oxide layer. The BE-SONOS charge storage structure can include a dielectric layer positioned above the multilayer tunneling layer for storing charge, such as a tantalum nitride layer having a thickness of 5-7 nm. The charge storage structure may also include a dielectric layer on the charge storage layer for blocking leakage, such as a yttria layer having a thickness of 5-8 nm. Other types of materials are also available in BE-SONOS stacking.

In a device comprising a BE-SONOS charge storage layer, an erasing operation may include F-F tunneling from the channel to the charge storage layer to neutralize electrons trapped in the charge storage layer.

However, for the structure as shown in Fig. 1, there is no P+ region in the entire series. It is possible to induce a band-to-band hot hole current through a Gate Induced Drain Leakage (GIDL) mechanism. However, an additional or additional source of holes may be required. As described in the present disclosure, a carrier supply including a diode can create a source of holes to solve this problem.

FIG. 2 is a layout diagram showing a first array arrangement of a three-dimensional finger vertical gate NAND memory device (finger VG (vertical gate) 3D NAND memory device). For reference, the "X" axis is parallel to the direction of the word line (eg, 125-0, 125-5, 125-15) in the structure, and the "Y" axis is parallel to the bit line in the structure (for example It is the direction of 202-1, 202-8), and the "Z" axis is in the direction orthogonal to the bit line and the bit line in the structure.

In the layout of Figure 2, the array arrangement includes a plurality of bit lines. The memory cell is placed at the intersection of bit lines (eg, 202-1, 202-2, 202-8) and word lines (eg, 125-0, 125-5, 125-15). In the illustrated embodiment, there are four blocks labeled A, B, C, D. For simplicity, each block of the embodiment has two layers of two bit line stacks deep. In other embodiments, there may be more The layers are, for example, 4, 8, 16 or more, and there may be a plurality of bit line stacks in each block, for example 4, 8, 16 or more. In this embodiment, the four blocks A, B, C, and D depicted share a carrier supply, as will be described in more detail below.

A plurality of bit lines in the upper level extend from a corresponding contact pad (upper level contact pads 202-A, 202-D) to the top of the source line and carrier supply structure. The carrier supply structure includes first source line contacts 217-1 to 219-8 in N+ regions 524-3 of a plurality of bit lines, and contact pad 220 includes a P+ region and a P+ region of the contact pads. The two source lines are in contact with 221-1 to 221-8. The N+ region 524-3 establishes the source terminal of the bit line. A junction 225 between the N+ region 524-3 and the P+ region 224 on the source line contact pad 220 provides a PN junction of a diode. In a p-channel embodiment, the doping types of regions 224 and 524-3 are reversed.

The bit lines in the lower level extend from a corresponding contact pad (lower level contact pads 203-A, 203-D), as shown in the figure, the bit lines in the lower level can be stepped by contact pads in the upper level The opening is obtained. In a patterned conductor layer such as the metal layer ML3 shown in FIG. 1, the series selection connections 210-A to 210-D and 211-A to 211-D are coupled to the contact pads and the bit elements thereon. line.

Horizontal word lines (e.g., 202-1, 202-2, 202-8) and horizontal ground select lines 127 are overlaid on bit lines (e.g., 125-0, 125-5, 125-15). The tandem select line gate structure is also overlying the bit line, including a tandem select line gate structure 119-A1 for coupling the bit line and contact pads 202-A, 203-A. 119-A2, the tandem select line gate structure 119-D1, 119-D2 for coupling the bit line with the contact pads 202-D, 203-D, and a plurality of serial selections in the blocks B and C The line gate structure is not labeled with a reference symbol. The tandem select line gate structure controls the electrical connection between any one of the bit lines and the contact pads (eg, 202-A, 203-A) corresponding to the bit lines. In a patterned conductor layer such as the metal layer ML2 shown in FIG. 1, the series selection connections 205-1 to 205-8 are coupled to a plurality of series selection line gate structures and the above-described series selection line.

The three-dimensional NAND memory device includes a plurality of memory cell planes. A plurality of bit lines in a plurality of memory cell planes select a particular plane via a plurality of contact pads (e.g., 202-A and 202-B). The particular plane is decoded by a plurality of serial selection structures, a plurality of horizontal ground selection lines, and a plurality of bit lines. A positive string select line voltage (V _SSL ) is applied to the string select structure (119-A1) to select a particular stack (eg, including the upper level bit line 202-1). For example, applying a voltage of 0 volts (V) to a plurality of string selection structures to deselect a plurality of other stacks.

2A-2C illustrate a structure that can be used for alternative carrier supply in a layout similar to that of FIG. 2.

Fig. 2A is a side view in the Z-Y plane direction, showing a carrier supply structure at the end of the stack of bit lines 202, 203 similar to the structure of Fig. 2. The stack of bit lines 202, 203 is disposed on an insulating layer 305 over a substrate 302. The ground selection line 127 is coupled to a side adjacent to the bit lines 125-N, 125-N-1, and the like. In this example, the bit lines 202, 203 are selected by grounding. The line selection 127 extends to an N+ end region 321 in the bit line. The N+ end region 321 is in contact with an N+ column 320 of semiconductor material or a portion of the N+ pillar 320 of semiconductor material, and the N+ pillar 320 of the semiconductor material provides the N+ end of the bit line. An inter-layer conductor 325 is coupled to the N+ pillar 320 and connected to a first source line (not shown). The bit lines 202, 203 extend from the vertical pillars 320 into the P+ regions of the source line contact pads 330, 331. The PN junctions 332, 333 between the P+ region in the source line contact pads 330, 331 and the N+ region on the N+ pillar 320 establish a diode. The interlayer conductors 326, 327, for example, may include tungsten plugs extending from the P+ regions in the source line contact pads 330, 331 in a stepped configuration and provided for connection to a second A source line (not shown) or a plurality of second source lines are separated in each horizontal plane. The P1PNS shown in FIG. 2A is the upper diode source terminal, the P2PNS is the lower diode source terminal, and the SC is the source contact terminal (the function is the source of the conventional NAND string).

Figure 2B depicts a side view of an alternate carrier supply structure, like elements being referenced to the same element symbols. In this configuration, bit lines 202, 203 extend the semiconductor contact pads and include a vertical N+ semiconductor material pillar 345 that is coupled to a first source line (not shown). The semiconductor contact pads also include a vertical P+ semiconductor material pillar 346 coupled to the contact pads to produce PN junctions 342, 343. A vertical cylinder 346 is used to connect a second source line (not shown).

Figure 2C depicts a side view of another alternative carrier supply structure. In this example, the bit line (eg, bit line 202 terminating at junction 350) terminates in a vertical N+ semiconductor material connected to a first source line (not shown). Cartridge 355. A vertical pillar system in the semiconductor substrate 302 is coupled to a P+ region 351 to establish a PN junction 353 at the interface. The inter-layer conductor 356, for example, may include a tungsten plug that is provided to connect the P+ region 351 with a second source line (not shown). The plurality of diode carrier supply structures illustrated in Figures 2A-2C can be used with three-dimensional memory. Other structures suitable for the implementation of memory and other components can also be used.

3, 3A, 3B, 4, 4A, 4B, 5, 5A, 5B, 6, 6A, 6B, 6C, 6D, 7, 7A, and 7B illustrate the process for fabricating the memory structure as shown in FIG. At different stages, the memory structure has a carrier supply structure as shown in Figure 2A. The third figure depicts a plan view of a top layer 500 of material used to fabricate the bit lines, as the upper layer 500 can be overlaid on a stack of staggered active materials and insulating materials. The material used to fabricate the plurality of bit lines may be a semiconductor material such as a germanium deposited polysilicon layer. Alternatively, the material can be a single crystal semiconductor material or other type of semiconductor material. The material may be relatively lightly doped as a channel in a thin film transistor or intrinsically doped for a particular need. For n-type channel thin film transistors, the material has a p-type lightly doped or intrinsically doped.

As shown in FIG. 3, after forming the staggered active material and the insulating material, a plurality of vias (for example, 501, 502, 503) are formed through the stack, and the plurality of via holes extend at least to the active material. bottom. A structure having a plurality of bit line stacks, forming a plurality of via holes, each hole corresponding to one bit line. A plurality of vias (e.g., 501, 502, 503) are aligned by a stack of patterned staggered active materials and insulating materials to align a plurality of bit lines.

Figure 3A depicts a side view of a stack of staggered active materials and insulating materials. From this perspective, a substrate 302, which may be a semiconductor or other type of material, is overlaid with an insulating material layer 305. A first active material layer 511 and a second active material layer 510 are separated by an insulating layer. A top layer of insulating material 509 overlies the stack. A via 501 is formed through the top insulating material layer 509 and extends at least to the first active material layer 511.

FIG. 3B illustrates a side view of the stack after filling the vias 501 with a semiconductor material 512 having an N+ doping. A planarization step can be performed such that the top of the semiconductor material aligns with one surface of the top insulating material layer 509.

FIG. 4 is a plan view showing the structure in FIG. 3 after performing a pattern etching process. The patterned etch defines a plurality of bit line contact pads (eg, 202-A, 202-B, 202-C, and 202-D) for use in each of the three-dimensional blocks A, B, and C as shown in FIG. , D. The patterned etch also defines a source line contact pad (e.g., 220), in this example the source line contact pad (e.g., 220) is shared by four blocks. A plurality of semiconductor material bit lines (eg, 202-1, 202-2, 202-8) extend from the source line contact pads (eg, 220) to a corresponding bit line contact pad (eg, 202-A, 202-B, 202-C and 202-D).

As shown in FIG. 4, the patterned etch also etches through the semiconductor material 512 filling the vias (eg, 501, 502, 503), the vias being depicted in FIG. Thus, the N+ type semiconductor material pillars (eg, 550-1, 550-2, 550-8) are connected to the bit lines in the first layer and the bit lines in the upper layer, and in this example the N+ type semiconductor material The width of the cylinder conforms to the width of the bit line. In other embodiments, The pattern in the region of the plurality of cylinders may be desired to have a variety of different widths.

FIG. 4 also illustrates a region 224 of P+ doping in the source line contact pads (eg, 220).

Figure 4A depicts a stacked side view along one of the bit lines (e.g., 202-2). Thus, the first layer of semiconductor material and the second layer of semiconductor material have been patterned to define a stack of bit lines, in which the stack of bit lines includes the underlying bit line 203-2 and the upper bit line 202-2. FIG. 4A illustrates a charge storage structure layer 519 deposited over the patterned bit lines. A mask, such as a photoresist mask 555, is also overlaid on the structure, and the photoresist mask 555 has an open exposed area 224 for P+ implant 556. P+ implantation is performed with sufficient energy such that P+ is doped into the lower layer and upper source line contact pads in the first and second active material layers.

Figure 4B depicts the structure after implantation and removal of the mask 555. The structure of FIG. 4B includes a P+ region 557 of the same layer of the second source contact pad as the upper layer bit line 202-2 and a P+ region 558 of the second source contact pad that is in the same layer as the lower layer bit line 203-2.

FIG. 5 is a plan view showing a process of forming a word line, a ground selection line, and a string selection line. The process may include depositing a P+ or N+ doped polysilicon over the charge storage structure (not shown in FIG. 5) in a manner of filling a plurality of trenches between the plurality of bit lines, thus in a plurality of stripes A vertical gate structure is formed between the lines (for example, 202-1, 202-2, 202-8).

This process makes horizontal word lines (for example, 125-0, 125-5, 125-15) and horizontal ground selection line 127 are overlaid on bit lines (eg, 202-1, 202-2, 202-8). The tandem select line gate structure also covers the bit line, including a tandem select line gate structure 119-A1, 119-A2 for coupling the bit line and the contact pad 202-A for coupling the bit line Similar to the tandem select line gate structures 119-D1, 119-D2 of contact pads 202-D, similar tandem select line gate structures in blocks B, C are not labeled with reference symbols. The flash memory cell is formed at the intersection between a plurality of bit lines and a vertical gate structure located on the plurality of word lines 125-0 to 125-15. The flash memory cells are stored by a thin film, a double gate, and a charge. The composition of the transistor. A dual gate transistor is formed at an intersection between a plurality of bit lines and a vertical gate structure on the ground select line 127 and the tandem selection structure, the dual gate transistor being selectively coupled as a switch along The memory cells of the bit lines are listed in a bit line contact pad or carrier supply structure. 5A, 5B are side views of the word line and ground selection line process, as shown in FIG. 5A, a P+ or N+ doped polysilicon layer 565 is deposited over the charge storage structure layer 519, and then as shown in FIG. 5B. The word line (eg, 125-N, 125-N-1, 125-N-2) and the ground selection line (eg, 127) are formed after patterning the polysilicon layer 565, and the string selection line is selected. It is also formed at this step.

FIG. 6 illustrates the formation of openings 220A, 220B, 220C, and 220D in source line contact pads 220 and formation in bit line contact pads (eg, 202-A, 202-B, 202-C, and 202-D). A plan view after the process of the corresponding opening. These openings expose the underlying source line contact pads (eg, 223) and the underlying bit line contact pads (eg, 203-A, 203-B, 203-C, and 203-D) so that interlayer contacts can be formed (interlayer contacts) ). The figure also shows a diagram for the N+ doped region. The method includes an N+ region 524-1 on a plurality of bit line contact pads, an N+ region 542-2 between a plurality of serial selection structures (eg, 119-A1) and a first word line 125-0, and An N+ region 524-3 over a plurality of N+ pillars (e.g., 550-2) in a plurality of bitlines. The N+ region 524-3 also partially overlies the source line contact pads 220 and extends up to or near the ground select line 127 along a plurality of bit lines.

Figure 6A depicts a structure similar to that of Figure 5B, having a photolithographic mask 579 overlying it, the lithographic mask 579 having an opening corresponding to region 524-3. The opening allows implant 524 of N-type dopants and is implanted into the lower bit line 203-2 as shown.

FIG. 6B illustrates the formation of a stepped opening 220A after removal of the mask 579 (see FIG. 6). As shown in Fig. 6B, a PN junction 592 is formed between the N+ region 590 in the upper layer and the P+ region 557 in the upper layer. Similarly, a PN junction 593 is formed between the N+ region 591 located in the lower layer and the P+ region 558 in the lower layer.

FIG. 6C illustrates the formation of an insulating fill layer 600 over the structure, and the planarization insulating fill layer 600 may expose a plurality of word lines (eg, 125-N) and an upper surface of the ground select line 127. Next, a vaporized layer 598, such as cobalt telluride, is formed over the ground selection line and the plurality of word lines. In the preferred embodiment, the germanide layer 598 is also formed over the tandem selection structure (not shown in Figure 6C).

Figure 6D illustrates another interlayer dielectric formed over the telluride layer Fill layer 601. The interlayer dielectric fill layer 601 is insulated with a word line, a ground select gate, and a tandem select gate structure and an overlying patterned conductor layer.

Figure 7 is a plan view showing the process of forming interlayer contact in the structure. The structure includes stepped contacts in the source line contact pads 220, 223 (eg, 410, 410A) and stepped contacts in the bit line contact pads (eg, 202-A, 203-A) (eg, 420, 420A) ). The structure also includes a stepped contact (e.g., 430) positioned above the tandem selection structure (e.g., 119-D1). Figure 7 incorporates many of the features described above in Figures 4, 5, and 6.

FIG. 7A illustrates a side view of the openings 605, 606, 607, the openings 605, 606, 607 being formed through the fill layer (eg, 601, 600) and the charge storage structure layer 519 to form the N+ pillar 550-2. Contact, formation of contact with the P+ region 557 of the upper source line contact pad and contact with the P+ region 558 of the underlying source line contact pad.

After the interlayer conductor fills the opening, the interlayer conductors 610, 611, 612 are formed, for example, tungsten plugs or other conductive structures, and the planarized structure is such that the surface of the structure is suitable for forming one or more overlying patterned conductive layers. .

As shown in FIG. 7B, the carrier supply structure includes PN junctions 592, 593 formed by N+ regions 550-2, corresponding N+ regions on each bit line, and P+ regions 557, 558 along the source contact pads. . The carrier supply structure also includes interlayer conductors 610, 611, 612. These interlayer conductors are provided for contact with the overlying first and second source lines as will be further described below.

Figures 8, 8A, 8B, 9, 9A, and 9B depict fabrication as shown in Figure 2B Multiple process stages of the carrier supply structure. Starting from Fig. 8, a pattern of etching after the staggered stacking of active material and insulating material is formed is illustrated. In this etch, a first end of the formed bit lines 202-1, 202-2, 202-8 is connected to the bit line contact pads (eg, 202-A, 202-B, 202-C, 202). -D). A second end of the bit line is connected to the source line contact pad (e.g., 220). In this example, openings 650-1 through 650-8, 651-1 through 651-8 are formed in the source line contact pads (e.g., 220). In this example, two openings (e.g., 650-2, 651-2) are aligned with one of the bit lines (e.g., 202-2).

FIG. 8A illustrates openings 650-2, 651-2 formed along the bit line 202-2 in the bit line contact pads, the openings 650-2, 651-2 extending into the lower bit line 203-2.

The opening 650-2, 651-2 is filled with a semiconductor material to form pillars 665, 666 that are in contact with the bit lines in the active material layer (e.g., 510, 511). The surface can be planarized and then a charge storage structure layer 519 is formed on a stack of a plurality of bit lines.

Figure 9 is a plan view showing the structure of the above plurality of steps related to the first manufacturing process. Thus, the plan view shows the step contact in the bit line contact pad, the contact on the tandem selection structure, and the two sets of contacts (750-1 to 750-8 and 751-1 to 751-8). The interlayer connections 750-1 to 750-8 are connected to the pillars formed in the source line contact pads, for example, the pillars formed in Figs. 8A, 8B. The plan view of Fig. 9 also shows the N+ implant region 725-1 covering the portion of the source line contact pad adjacent to the ground selection line 127, and the N+ implant between the first word line and the tandem selection structure. Region 725-2 and N+ implant region 725-3 covering the bit line contact pad region. FIG. 9 also illustrates a P+ implant region 724 that covers a region of the source line contact pad (eg, 220) that is further away from the bit line.

The result of implanting a region near the source line contact pad is illustrated in FIG. 9A, and N+ pillars 651 and N+ portions in the source line contact pads of the upper and lower layers are implanted in region 725-1 (eg, 652), P+ pillars 661 and P+ portions 653, 654 in the source line contact pads of the upper and lower layers are implanted in region 724. Thus PN junctions 656, 655 are formed in the structure.

FIG. 9B illustrates a structure in which a germanide layer 598, an interlayer dielectric fill 650, and interlayer connections 751-2, 750-2 are formed on the structure. It can be seen that the carrier supply structure as shown in Fig. 2B is formed by this flow.

10, 10A, 10B, 11, 11A, and 11B illustrate a plurality of process stages for fabricating a carrier structure as shown in FIG. 2C. Beginning with Figure 10, the pattern of etching after the staggered stacking of active material and insulating material is formed is illustrated. In this etch, a first end of the formed bit lines 202-1, 202-2, 202-8 is connected to the bit line contact pads (eg, 202-A, 202-B, 202-C, 202). -D). A second end of the bit line is connected to the source line contact pad (e.g., 220). In this example, the upper source line contact pads (e.g., 220) are etched to expose a portion of the semiconductor substrate. Openings 850-1 through 850-8 are also formed through the upper source line contact pads up to the level of the lower source line contact pads. This plan view also shows the P+ implanted region 824 in the substrate 302 for forming the P+ region 351.

Figure 10A is a side view of the stack along the bit lines 202-2, 203-2 The figure shows an opening 850-2 extending through the P+ region 351 stacked in the substrate 302.

FIG. 10B illustrates a side view of a semiconductor material N+ pillar (column 355) after the semiconductor material N+ pillar extends through the source line contact pad 220 to couple to a plurality of bit lines. The PN junction is formed at an interface between the N+ pillar (column body 355) and the P+ region 351 to establish a diode of the carrier supply structure. The formation of the charge storage structure layer 519 over the patterned bit lines is also illustrated in FIG. 10B.

Figure 11 is a plan view showing the structure of the above plurality of steps related to the first manufacturing process. Therefore, in the plan view, a step contact in the bit line contact pad, a contact on the tandem selection structure, and a set in the region of the source line contact pad 220 are formed in a manner of referring to the above-mentioned 10A, 10B. The interlayer conductors (859-1, 859-2, 859-8) and a set of interlayer conductors (869-1, 869-2, 869-8) for connection to the P+ region 351 in the substrate. Figure 11 also shows a P+ implanted region 824, an N+ implant region 825-1 located on the source line contact pad 220, and an N+ implant region 825 between the first word line and the tandem selection structure. -2 and N+ implant area 825-3 on the bit line contact pad.

11A is a side view similar to FIG. 6C, showing a charge storage structure 519 forming a covered bit line, a horizontal word line (eg, 125-N, 125-N-1, 125-N-2) and The result of horizontal ground selection line 127.

FIG. 11B illustrates the results of formation of the telluride layer 598, the insulating fill 855, the interlayer conductor 859-2 connecting the N+ pillar (cylinder 355), and the interlayer conductor 869-2 connecting the P+ region 351 in the substrate 302. It can be seen that the PN junction 353 is formed to establish a diode of the carrier supply structure.

12 to 15 are one of the two-layer three-dimensional arrays, for example, a block diagram of the block A shown in FIG. 2, and the block may have the carrier supply structure of the 2A-2C chart. Any one. Although standard transistor symbols are used herein, embodiments of the invention include junction-free NAND strings.

For the sake of clarity, the term "programming" as used in the present invention relates to an operation that increases the threshold voltage of a memory cell. The data stored in the programmed memory cell can be represented as logic "0" or logic "1". The term "erase" as used in the present invention relates to an operation of lowering the threshold voltage of a memory cell. The data stored in the erased memory cell can be represented by a logical "1" or a logical "0". Multi-bit cells can also be programmed with a number of different threshold levels or erases to have a single minimum or maximum critical level, as desired by the designer. Furthermore, the term "write" as used in the present invention describes an operation that changes the threshold voltage of a memory cell, and it is desirable to include both programming and erasing or a combination of programming and erasing operations.

The programming operations described herein include biasing a selected memory cell to inject electrons into a charge storage structure in a selected memory cell, thereby increasing the threshold voltage. A programming operation can be performed to program a memory cell, such as a page, a character, or one or more selected ones of a tuple. In a programming operation, biasing the unselected memory cells to avoid or reduce the disturbance of stored charge.

The present invention describes a block erase operation for n-type channel memory, A block biased into a plurality of cells is included to inject a hole into a charge storage structure unit in the selected block, thereby reducing the threshold voltage, at least a plurality of cells of the block initially having no low threshold voltage. Other programming and erase bias operations may be used.

Taking a two-layer three-dimensional stack structure as an example, as shown in FIG. 12, according to the two-layer structure block, as shown in FIG. 2, there are four NAND strings arranged in the upper, lower, left and right, and the upper two series are coupled to the bit line layer BLL1. The lower two strings are coupled to the bit line layer BLL2. A first stacked tandem selection structure in the stack of a plurality of bit lines includes tandem select switches 824-1, 824-2 coupled to a series of select lines SSL1. Similarly, a second stacked serial selection structure in a stack of a plurality of bit lines includes string select switches 825-1, 825-2 coupled to a series of select lines SSL2. The ground select line GSL covers a plurality of bit lines, forming four ground select switches 814-1, 814-2, 814-3, and 814-4. The bit line is also coupled to the N-type terminal 801 of the PN diode 800, and is sequentially coupled to a first source line by the contacts 804-1, 804-2, 804-3, and 804-4. 803. The P-type end of the PN diode 800 is coupled to a second source line 802. The same circuit structure is shown in Figures 12-15.

Figure 12 illustrates a biasing arrangement for programming a selected unit. Figure 13 is a diagram showing a bias arrangement for erasing a block in a plurality of memory cells. Figure 14 illustrates another bias arrangement for erasing a block in a plurality of memory cells. Figure 15 illustrates a bias arrangement for reading a selected cell in a block.

Therefore, the memory circuit includes a sequence arrangement of a plurality of memory cells, including, for example, memory cells 840, 842, 845, and 847. The string. A second switch (eg, 814-1) on a second end of the sequence is coupled to a first end of the diode. The memory circuit also includes a plurality of word lines WL. The circuit is coupled to the plurality of word lines, the first and second source lines, the ground selection line GSL, the sequence selection line SSL, and the bit line for controlling the operation of the memory circuit. In this configuration, the circuit is configured to drive or bias the first and second source lines under different bias conditions. The controller can include an erase bias arrangement configured to apply an induced hole generation, a programmed bias arrangement, and a read bias arrangement. The controller is described with reference to Fig. 17 as follows.

Figure 12 shows the programming bias arrangement. In this bias arrangement, a source side bias is applied to the first source line 803 (eg, the first source contact terminal SC=0), and when the second source line 802 receives a reverse biased diode When the bias voltage or the second source line 802 is in a floating state, the diode is turned off and the current cannot be transferred to the second source line 802. At this time, the source terminal diode does not affect the component programming. .

The programming bias arrangement as illustrated in Fig. 12 in one embodiment is as follows:

Selected word line BL: 0V

Unselected word line BL: 3.3V

Selected serial selection line SSL: 3.3V

Unselected serial selection line SSL: 0V

Selected word line WL: Vpgm

Unselected word line WL: Vpass

Ground selection line GSL: 0V

Source contact terminal SC: 0V

PN junction source terminal PNS: 0V (PN diode off)

The programming bias arrangement can represent a programming pulse in a stylized operation, such as an Incremental Step Pulsed Programming (ISPP) method, for a more conventional flash memory array, without requiring additional loading. Sub-supply, while the dipole system is closed.

Figure 13 is a diagram showing an erase bias arrangement for inducing hole tunneling. In one embodiment, the erase bias arrangement as illustrated in FIG. 13 is as follows:

All bit lines BL: floating

All serial selection lines SSL: 0V

All word lines WL: -8V

Ground selection line GSL: -2V

Source contact terminal SC: floating

PN junction source terminal PNS: V>Vbi (PN diode on)

In this erase operation, the PN diode system is turned on to provide a source of holes for tunneling. In the ground selection line switch, the gate induces a drain leakage to provide a hole to the bit line.

Figure 14 illustrates another erase bias arrangement using gate-induced drain leakage for both the tandem selection structure and the ground selection structure. In one embodiment, the erase bias arrangement as illustrated in FIG. 14 is as follows:

All bit lines BL: -8V

All serial selection lines SSL: -2V

All word lines WL: -8V

Ground selection line GSL: -2V

Source contact terminal SC: floating

PN junction source terminal PNS: V>Vbi (PN diode on)

In this erase bias arrangement, the two-pole system is turned on, keeping the source contact at a reference voltage, and when the first source line is in a floating state, the first source line does not participate in the bias voltage. In order to induce the formation of a hole, the series selection switch receives a suitable negative gate voltage, causing the gate to induce a drain leakage. Biasing the selected memory cells produces FN hole tunneling.

Figure 15 illustrates a read bias arrangement. In this read bias arrangement, the two-pole system is off and the signal can be transmitted from the first source terminal, allowing operation in accordance with a more typical read method. In one embodiment, the read bias arrangement illustrated in Figure 15 is as follows:

Selected word line BL: 1V

Unselected word line BL: 0V

Selected serial selection line SSL: 3.3V

Unselected serial selection line SSL: 0V

Selected word line WL: Vref

Unselected word line WL: Vpass

Ground selection line GSL: 3.3V

Source contact terminal SC: 0V

PN junction source terminal PNS: 0V (PN diode off)

Biasing the diode during reading causes no voltage drop across the diode. For high speed and efficient reading, the bias voltage of the diode remains loaded.

Figure 16 illustrates a schematic diagram of an alternative circuit showing another different structure that can be implemented. In this configuration, each layer has its own carrier supply diode. Therefore, the layer coupled to the bit line layer BLL1 has a diode including a first end 866 and a second end 865. The layer coupled to the bit line layer BLL2 has a diode including a first end 861 and a second end 860. Separate second source lines 862 and 867 are connected to the second end of the diode. Different biasing arrangements can be applied to the circuit shown in Figure 16 as discussed above and with reference to Figures 12-15.

Figure 17 is a simplified block diagram of an integrated circuit 25 that includes a p-type channel, NAND flash memory array 10 that can be operated by embodiments of the present invention. In some embodiments, array 10 is a three-dimensional memory comprising a plurality of layers of memory cells. A column of decoders 11 is coupled to a plurality of bit lines 12 along a column arrangement in memory array 10. The plurality of row decoders in block 16 are coupled to a set of page buffers 13, which in this embodiment are coupled via a data bus 17. The global bit lines 14 are coupled to local bit lines (not shown) along the rows in the memory. Addresses are transmitted via bus 15 to the row decoder (block 16) and the column decoder (block 11). Moreover, it can be inferred by block 20 that the circuitry includes drivers for the first and second source lines such that the first and second source lines are biased separately or independently.

Data from other circuits 24 on the integrated circuit (including, for example, input The /output port is provided via a data input line 23, such as a general purpose processor, a special purpose application circuitry, or a system single chip that provides functional support by the array 10. (system-on-a-chip) module combination. The data is transmitted via the data input line 23 to the input/output port, other internal data destinations, or to the external integrated circuit 25.

A controller, in one embodiment, for example, a state machine 19, provides signals to control the application of bias supply voltages provided or generated via one or more voltage controllers in block 18 to implement the present invention. Different operations include read and write operations in the array. These operations include erasing, programming, or reading. The controller can be implemented by special-purpose logic circuitry of the prior art. In another embodiment, the controller includes a general purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In another embodiment, the implementation of the controller may use a combination of special purpose logic circuitry and a general purpose processor.

The controller can include circuitry for performing a program that includes biasing the diodes in a forward bias condition during operation to provide a minority carrier to sequence alignment, altering a criticality of one or more memory cells in the memory The voltage is biased to the diode in a reverse bias condition during reading. For example, a program executed by circuitry in the controller can include biasing the diodes in a forward bias condition during an erase operation. The program executed by the circuitry in the controller may also include biasing the diodes in a reverse bias condition during the programming operation.

The described structure improves the erase performance in an external PN diode-derived three-dimensional memory on the source side of the NAND string in the array.

In one embodiment, the carrier supply structure is disposed in a vertical gate NAND flash memory. In operation, the electro-optic tunneling of the thin film transistor (TFT) structure and the lack of body contact with the three-dimensional vertical gate memory may be quite different from conventional NAND. In this case, the source of the hole can improve the device erase.

In the above, the present invention has been described above by way of preferred embodiments and detailed examples, which are not intended to limit the invention. It will be appreciated that those skilled in the art having the present invention can make various modifications and changes without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

202-1, 202-2, 202-8‧‧‧ bit line

119-A1, 119-A2, 119-D1, 119-D2‧‧‧ tandem selection line gate structure

125-0, 125-5, 125-15‧‧‧ character lines

127‧‧‧ Grounding selection line

202-A~202-D, 203-A~203-D, 220‧‧‧ contact pads

205-1, 205-8, 210-A, 210-D, 211-A, 211-D‧‧‧ Serial connection

219-1, 219-8‧‧‧first source line contact

221-1~221-8‧‧‧Second source line contact

224‧‧‧P+ area

225‧‧‧Connected

524-3‧‧‧N+ area

X, Y‧‧ direction

Blocks A, B, C, D‧‧

Claims (24)

A semiconductor array arrangement comprising a carrier supply, comprising: a diode having a first end and a second end; a sequence arrangement comprising a plurality of memory cells arranged by a first end The first switch is coupled to the one bit line, and the second switch of the second end is coupled to the first end of the diode; a first source line and a second source a line, respectively connected to the first end and the second end of the diode; a plurality of word lines, the word lines are coupled to the corresponding ones of the plurality of memory cells; and a circuit The first word line and the second source line are coupled to the word line, the first source line and the second source line, and the circuit is configured to bias the first source line and the second source line under different bias conditions. The semiconductor array arrangement of claim 1, wherein the circuit is configured to employ an erase bias arrangement to induce hole tunneling, the erase bias arrangement being included in the second source a source side bias on the line, the source side bias biases the diode forward, and when the first source line remains floating, the erase voltage on the word lines induces tunneling . The semiconductor array arrangement of claim 1, wherein the circuit is configured to apply a programming bias arrangement comprising a source side bias on the first source line. The second source line remains floating or biased to reverse bias the diode. The semiconductor array arrangement of claim 1, wherein the memory cells comprise a plurality of thin film transistors. The semiconductor array arrangement of claim 1, wherein the memory cells comprise a plurality of thin film transistors arranged on a single semiconductor strip, wherein the first of the diodes in the single semiconductor strip One end includes a doped region. The semiconductor array arrangement of claim 1, wherein the memory cells comprise a plurality of thin film transistors arranged on a single semiconductor strip, wherein the first of the diodes in the single semiconductor strip One end and the second end each include a doped region. The semiconductor array arrangement of claim 1, wherein the memory cells comprise a plurality of thin film transistors arranged on a single semiconductor strip overlying a semiconductor substrate, the second of the diodes One end includes a doped semiconductor material coupled to the single semiconductor strip and the semiconductor substrate, and the second end of the diode includes a doped region in the semiconductor substrate. The semiconductor array arrangement of claim 1, wherein the sequence is a NAND string, the memory comprising at least one additional coupled to the first end of the diode. The reverse and the brake string. The semiconductor array arrangement of claim 1, wherein the memory cells are configured for operation in an n-type channel in a read mode, the first end of the diode having an n-type doping, The second end of the diode has p-type doping. The semiconductor array arrangement of claim 1, wherein the memory cells are configured for a p-type channel operation in a read mode, the diode The first end has a p-type doping and the second end of the diode has an n-type doping. The semiconductor array arrangement of claim 1, wherein the memory cells comprise a thin film and a plurality of vertical gate cells. A semiconductor array arrangement comprising a carrier supply, comprising: a three-dimensional array comprising a plurality of horizontal planes, each of the horizontal planes comprising a contact pad and a plurality of strips of semiconductor material extending from the contact pad; a plurality of first two a pole end, one of the first diode ends being a contact point of one or more of the strips of semiconductor material on the distal end; a second diode end, the second diode end contacting One of the first diode ends; a first source line connected to the first diode ends; a second source line connected to the second diode end; a plurality of a word line coupled to the strips of semiconductor material in the horizontal planes; a charge trapping element and a data storage element positioned between the word lines and the strips of semiconductor material, wherein the plurality of memory cells And disposed at the intersections of the strips of semiconductor material and the word lines; and a circuit coupled to the first source line and the second source line, the circuit is used for different bias voltages The first source line and the second source line are biased under conditions. The semiconductor array arrangement of claim 12, wherein the circuit is configured to employ a wiper bias arrangement to induce hole tunneling, the erase bias arrangement comprising a source on the second source line a side bias, the source side bias is forward biased to a diode, and when the first source line remains floating, on the word lines The erase voltage induces tunneling. The semiconductor array arrangement of claim 12, wherein the circuit is configured to align with a programming bias to close a diode terminal, the programming bias arrangement comprising a source side of the first source line Bias, when the second source line remains floating or pressurized to reverse bias the diode, the diode terminal does not affect component programming. The semiconductor array arrangement of claim 12, further comprising a plurality of first selection lines and a second selection line, the first selection lines of the semiconductor material strips at a proximal end of the contact pads The second selection line is disposed on the stack of the semiconductor material strips between the first diode ends and the word lines. The semiconductor array arrangement of claim 12, wherein the first diode ends comprise a plurality of doped regions located in the strips of semiconductor material. The semiconductor array arrangement of claim 12, wherein the first diode ends and the second diode ends comprise a plurality of doped regions located in the strips of semiconductor material. The semiconductor array arrangement of claim 12, wherein the horizontal planes cover a semiconductor substrate, the first diode ends and the second diode ends, the first diodes The terminal includes a doped semiconductor material coupled to the strip of semiconductor material, and the second diode end includes a doped region located in the semiconductor substrate. The semiconductor array arrangement of claim 12, wherein the The memory cells are configured for an n-type channel operation in a read mode, the first diode ends including an n-type semiconductor material, and the second diode ends including a p-type semiconductor material. The semiconductor array arrangement of claim 12, wherein the memory cells are configured for a p-type channel operation in a read mode, the first diode ends comprising a p-type semiconductor material, The second diode end includes an n-type semiconductor material. The semiconductor array arrangement of claim 12, wherein the memory cells comprise a thin film and a plurality of vertical gate cells. An operation comprising a three-dimensional flash memory provided by a carrier, the three-dimensional flash memory comprising a sequence of a plurality of memory cells, and a first source line and a second source a line connected to one of the first end and the second end of the diode, wherein the first end of the sequence is functioning as a source end of the conventional NAND memory element, and the second end of the sequence is An operating end of the diode PN junction, the first end of the sequence is coupled to the diode, the second end of the sequence is coupled to a bit line, the method includes: operating process Biasing the diode under a forward bias condition to provide a sequence of minority carriers to change a threshold voltage of one or more memory cells, biasing the output during a reverse bias condition during reading Diode. The method of claim 22, comprising: biasing the diode under a forward bias condition during the erasing operation. The method of claim 22, including: operating in a program During the process, the diode is biased under a reverse bias condition.