TWI529705B - Data decoder circuit, data encoder circuit and data processing circuit - Google Patents

Description

Data decoder circuit, data encoder circuit and data processing circuit

The present invention relates to storing data, and more particularly to formats, systems, and methods for storing data to a storage medium.

The read channel integrated circuit is a component of the magnetic storage device. In operation, the read channel component converts and encodes the data and enables the read/write head component to write data to the disk and subsequently read the data back. For example, in a hard disk drive, a magnetic disk typically includes a plurality of magnetic tracks containing encoded material and extending around the disk in a radial pattern. Each track includes one or more user data areas and an intermediary servo data area. The information in the servo data area is used to determine the position of the read/write head assembly relative to the disk so that the information stored in the user data area can be accurately captured.

Figure 1 shows a storage medium 100 having two exemplary magnetic tracks 150, 155 indicated by dashed lines. The tracks are isolated by servo data written in the wedge regions 160, 165. These wedge regions include data and support bit patterns 110 that are used to control and synchronize the read/write head assembly over the desired location on the storage medium 100. In particular, these wedge regions typically include a preamble 152 followed by a sector address mark (SAM) 154. Next, the sector address mark 154 is the Gray code 156, and then the Gray code 156 is the burst information 158. It should be noted that although two tracks and two wedge regions are shown, typically hundreds of tracks and wedges will be included on a given storage medium. Further, it should be noted that the servo data set may have two or more cluster information fields. Between the bit patterns 110, a user profile area 184 is provided. Such user profile area 184 includes a substantial administrative overhead and a wasted area that results in a decrease in the density of data held in user profile area 184.

Thus, for at least the foregoing reasons, there is a need in the art for an improved system and method for maintaining data on a storage medium.

The present invention relates to storing data, and more particularly to formats, systems, and methods for storing data to a storage medium.

Various embodiments of the present invention provide a data storage system including a storage medium. The storage medium includes: a first servo data area and a second servo data area separated by a user data area. The user profile area includes at least a portion of the first codeword and a portion of the second codeword, the first codeword and the second codeword being associated with the shared header material. In some examples, the first codeword and the second codeword are coded codewords for low density parity check. In various examples of the aforementioned embodiments, the portion of the first codeword is all of the first codeword, and the portion of the second codeword is less than all of the second codeword. In this case, the remainder of the second codeword is included in another user profile area.

In some cases, the data storage system further includes an encoder circuit operative to: receive the write data; encode the write data into the first codeword and the second codeword; and combine The portion of the first codeword and the portion of the second codeword and the shared header data form a super sector data set. In some such cases, the encoder circuit includes a low density parity check encoder, and the first codeword and the second codeword are low density parity check encoded codewords. In one or more such cases, the encoder circuit further includes a user data area matching circuit operative to combine the portion of the first codeword with the second codeword The portion and the shared header data become the super-sector data set. In a particular case, the super-sector data set includes more than twice the number of bit periods in the first codeword and less than the number of bit periods of the user data area.

In one or more cases, the portion of the first codeword, the portion of the second codeword, and the shared header material are combined in a super-sector data set. The system further includes: a decoder circuit operative to: receive the super-sector data set; synchronize the super-sector data set with the common header data; and segment the super-sector data set to generate the first codeword The portion and the portion of the second codeword; and decoding the first codeword and the second codeword to generate the write data. In some such cases, the decoder circuit includes a low density parity check decoder, and the first codeword and the second codeword are low density parity check coded codewords.

Other embodiments of the present invention provide a data decoder circuit having a codeword boundary matching circuit and a data processing circuit. The codeword boundary matching circuit is operable to: receive a super-sector data set having a first codeword, a second codeword, and a common header data; and divide the super-sector data set to generate the first codeword and the The second code word. The data processing circuit is operative to: apply a decoding algorithm to the first codeword to generate a first data set; and apply the decoding algorithm to the second codeword to generate a second data set. In some cases, the first codeword and the second codeword are low density parity check encoded codewords, and the data processing circuit includes a low density parity check decoder circuit.

This summary provides only a summary of some embodiments of the invention. The other objects, features, advantages and other embodiments of the invention will be more fully apparent from the appended claims appended claims

The present invention relates to storing data, and more particularly to formats, systems, and methods for storing data to a storage medium.

Various embodiments of the present invention provide improved format efficiency for user profiles maintained on a storage medium. Such an embodiment is prepared to concatenate codewords into a super-sector data set that is stored to a storage medium. As used herein, the phrase "super-sector data set" is used in its broadest sense to mean a data set that includes more than one codeword combined with the common header data. Among other things, such a sequence reduces the administrative burden associated with maintaining the data on the storage medium. Various examples of the foregoing embodiments support splitting codewords, allowing for the use of isolated areas of the storage medium. In a particular example of the foregoing embodiment, a single preamble field and a synchronization pattern are included in each user profile area to synchronize the data held in the user profile area. As such, it is possible to use only a single preamble and synchronization pattern to synchronize multiple codewords within the user profile area. The data received from the user profile area is combined into a codeword for processing by the read channel circuitry.

Turning to FIG. 2, a storage system 200 including a read channel 210 is depicted in accordance with various embodiments of the present invention having support for serialized user data. The storage system 200 can be, for example, a hard disk drive. The read channel 210 may include support for the serialized user profile (ie, a super-dataset) consistent with those discussed below with respect to FIG. 3, and/or possibly one or more of Figures 4-5. The operators operate in unison. Further, the read channel 210 includes a data detector such as, for example, a Viterbi algorithm data detector. In addition to reading channel 210, storage system 200 includes a preamplifier 270 that amplifies the minute electrical signals received from read/write head assembly 276. The read/write head assembly 276 is configured relative to the disk 278. The storage system 200 also includes an interface controller 220, a hard disk controller 266, a motor controller 268, and a spindle motor 272. The interface controller 220 controls the addressing and timing of the data sent to/from the disk 278. The data on disk 278 is comprised of a group of magnetic signals that can be detected by the component when read/write head assembly 276 is properly placed over disk 278. In one embodiment, disk 278 includes magnetic signals recorded in accordance with a perpendicular recording architecture. In other embodiments of the invention, disk 278 includes magnetic signals recorded in accordance with a longitudinal recording architecture.

In a typical read operation, the read/write head assembly 276 is accurately placed by the motor controller 268 over the desired data track on the disk 278. The motor controller 268 positions the read/write head assembly relative to the disk 278 by moving the read/write head assembly to the appropriate data track on the disk 278 under the guidance of the hard disk controller 266. 276 and drives the spindle motor 272. Spindle motor 272 rotates disk 278 at a determined spin rate (revolutions per minute, RPM). Once the read/write head assembly 276 is positioned adjacent to the appropriate data track, the magnetic signal representative of the material on the disk 278 is rotated by the spindle motor 272 as the disk 278 is rotated by the read/write head assembly. 276 sensed. The sensed magnetic signal is provided as a continuous, minute analog signal representative of the magnetic material on disk 278. This tiny analog signal is transferred from the read/write head assembly 276 to the read channel 210 via the preamplifier 270. Preamplifier 270 is operative to amplify the tiny analog signals accessed from disk 278. In turn, read channel 210 decodes and digitizes the received analog signal to reproduce the information originally written to disk 278. This information is provided to the receiving circuit as the read data 203. The write operation is essentially the reverse of the previous read operation, providing write data 201 to the read channel module 210. This data is then encoded and written to disk 278.

Turning to Figure 3a, a read channel circuit 205 operable to read and write a sequenced user data set (i.e., a super-sector data set) is shown in accordance with various embodiments of the present invention. The read channel circuit 205 includes an encoder circuit 233 and a decoder circuit 273. The encoder circuit 233 includes a material encoding circuit 213, an encoded data buffer 219, and a user data region matching circuit 223. The write data 201 is supplied to the material encoding circuit 213. The write data 201 can be received from any data source known in the art and can be received via the parallel data bus or via the serial data bus as is known in the art. In a particular embodiment of the invention, the write data 201 is received from an upstream processor (not shown). The write data 201 is combined by the material encoding circuit 213 into code words supplied to the encoded material buffer 219. In one particular embodiment, data encoding circuit 213 is known in the art as a low density parity check (LDPC) encoder circuit. In such an embodiment, data encoding circuit 213 provides a series of LDPC code words to encoded data buffer 219. Such LDPC code words are known in the art to include portions of the data 201 and various encoded information. For a specific example, the codewords can each be four thousand and ninety-six user bits plus the number of coded bits (eg, parity bits). In some cases, depending on the robustness of the code being implemented, the number of coded bits may be between forty and four hundred.

The encoded data buffer 219 can be any data storage device capable of storing the generated codewords from the data encoding circuit 213 until the codewords can be processed and written to the storage medium. For example, the encoded data buffer 219 can be a first in first out memory that provides a portion of the stored codeword to the user data region matching circuit 223 via the codeword interface 227 when asserting the request signal 228.

User profile area matching circuit 223 is operable to combine two or more codewords into a super-sector data set that is provided to the storage medium as encoded data output 293. After the write gate signal 287 has asserted sufficient time for the header data 288 to be written to the storage medium, the encoded material output 293 is presented. The header data insertion circuit 241 provides the header data 288 one bit at a time during the header before writing the encoded material output 293 to the storage medium. Header data 288 can be any header material known in the art. The header data 288 is provided to be controlled based on the assertion of the write gate signal 287 just prior to the encoded data output 293. The header data 288 becomes part of the super-sector data set that is written to the storage medium. In a particular embodiment of the invention, the header data 288 includes a preamble and a synchronization field that can be used to identify the beginning of the user profile when read back from the storage medium and to synchronize the super-sector data set. Based on the disclosure provided herein, those skilled in the art will recognize various header materials that can be used with different embodiments of the present invention.

The number of codewords combined into the super-sector data set and the portion of the codeword can be matched to the size of the user data area of the storage medium. The following formula represents the amount of data incorporated into the super-sector data set:

For example, when the super-sector data set ends at the codeword boundary of the last user data area, the size of the user data area is 10,750, and the size of the header data is 100. The size of the codeword is 4,099, and the number of codewords calculated by the previous formula is 2.6. In this case, the contiguous super-sector data set begins with the header data, followed by two complete codewords available from the encoded data buffer 219, and is equivalent to 0.6 codewords and is buffered from the encoded data. Part of the next codeword of 219. The remainder of the partial codeword (i.e., the last 0.4 codeword) is written after the header data of the succeeding super-sector data set.

The user data area matching circuit 223 receives the servo gate signal 251 from the servo data processing circuit (not shown) and indicates the location of the user data area relative to the intermediate servo data area. Once the super-sector data set is combined as described above and the servo gate signal 251 indicates the beginning of the user data area, the user data area matching circuit 223 asserts the write gate signal 287 and passes the encoded data one bit at a time. Output 293 provides a combined super-sector data set in tandem. This information is provided to a write circuit (not shown) responsible for writing data to the incorporated storage medium.

The decoder circuit 273 includes a header synchronization circuit 252, a codeword boundary matching circuit 253, a decoded data buffer 256, and a data processing circuit 263. The header synchronization circuit 252 receives the read data input 296 from the storage medium and synchronizes the frequency and phase of the received data stream with the preamble and synchronization information included in the header data associated with the received data. . This attempt to synchronize is initiated when the servo gate signal 251 indicates that the servo data region has ended and the user profile region has begun. After synchronizing the received data stream, the header synchronization circuit 252 asserts a synchronization discovery signal 254 indicating that the data received via the read data input 296 is valid user data. Header synchronization circuit 252 can be any circuit known in the art that is capable of synchronizing data sets from user data areas of storage media and claiming material availability indicator signals.

The codeword boundary matching circuit 253 receives the synchronization discovery signal 254 and the read data input 296, and becomes a full codeword according to the synchronization discovery signal and the read data input combination received data. Thus, for example, when the end of the user data area includes the first portion of the codeword, the codeword boundary matching circuit 253 waits to receive the second portion of the codeword from the beginning of the contiguous user data area before providing the complete codeword. The codeword boundary matching circuit 253 uses the information provided by the self-codeword sequence table circuit 283 via the pointer 297 to identify the location of the codeword within the material provided via the read data input 296. In some embodiments, one or more counters synchronized with the synchronization discovery signal 254 are used to count bits from the codeword and codeword portions of a given user data area.

The codeword boundary matching circuit 253 provides a portion of the codeword or codeword and the codeword boundary signal 258 and the material valid signal 257 to the decoded data buffer 256, the codeword boundary signal indicating the separation between the codewords and the data valid signal Used to indicate that the data on any given pulse period is valid. The combination of these signals is used to write the combined codewords into the decoded data buffer 256. In light of the disclosure provided herein, those skilled in the art will recognize other interfaces that can be used to transfer material from the codeword boundary matching circuit 253. The decoded data buffer 256 can be any data storage device capable of storing codewords from the codeword boundary matching circuit 253 until the codewords can be processed by the data processing circuitry 263. For example, the decoded data buffer 256 can be a first in first out memory that provides a codeword from the codeword boundary matching circuit 253 to the data processing circuit 263. The data processing circuit 263 processes the received data and provides the read data 203. When no processing error is caused, the read data 203 corresponds to the information originally received as the write data 201.

Data processing circuitry 263 can be any circuit known in the art that is operable to process encoded data from a storage medium and attempt to reply to an original data set that is encoded and written to the storage medium. For example, data processing circuit 263 can be implemented to include a decoder circuit that is operable to reverse the encoding applied by data encoding circuit 213 as is known in the art. Such a data decoder circuit can be, but is not limited to, an LDPC decoder circuit. Many data processing circuits that can be used with different embodiments of the present invention will be recognized by those skilled in the art from the disclosure provided herein.

Turning to Figure 3b, a read channel circuit 306 operable to read and write a sequenced user data set (i.e., a super-sector data set) is shown in accordance with various embodiments of the present invention. The read channel circuit 306 includes an encoder circuit 334 and a decoder circuit 374. The encoder circuit 334 includes a user data area matching circuit 324, a data encoding circuit 314, and a data writing circuit 304. The write data 301 is supplied to the user profile area matching circuit 324. The write data 301 can be received from any data source known in the art, and the write data 301 can be received via a parallel data bus or via a serial data bus as is known in the art. In a particular embodiment of the invention, the write data 301 is received from an upstream processor (not shown). The write data 301 is combined by the user profile area matching circuit 324 to include sufficient data to fill the entire user profile area on the storage medium. The combined amount of user data is approximately equal to the size of the user data area minus the number of coded bits applied to the data and the amount of header data before the data on the storage medium. Further, in some cases, the combined data is interleaved (i.e., shuffled) by the user data region matching circuit 324 to reduce the impact of any local noise on the data set that is subsequently replied to. The combined and interleaved user data is provided to a data encoding circuit 314 that performs data encoding on the received user data. Data encoding as known in the art can be, for example, LDPC encoding. The data encoding circuit 314 provides the encoded data to the data writing circuit 304 as a super-sector data set. The data write circuit 304 receives the servo gate signal 251 from a servo data processing circuit (not shown) and indicates the location of the user data area relative to the intermediate servo data area. Once the servo gate signal 251 is asserted, the data write circuit 304 asserts the write gate signal 387.

Based on the assertion of the write gate signal 387, the header data insertion circuit 341 begins to spool out the header data 388, which will become part of the super-sector data set on the storage medium. Once the header data is completed, the data write circuit 304 begins writing the encoded data to the storage medium as the encoded data output 394. The header data 388 and the encoded data output 394 are provided to a downstream write circuit (not shown) responsible for writing the data to the incorporated storage medium.

The decoder circuit 374 includes a header synchronization circuit 352, a detection/decoding circuit 353, and a user data separation circuit 356. Header synchronization circuit 352 receives read data input 396 from the storage medium and synchronizes the frequency and phase of the received data stream using preamble and synchronization information included in the header data associated with the received data. . This attempt to synchronize is initiated when the servo gate signal 251 indicates that the servo data region has ended and the user profile region has begun. After synchronizing the received data stream, the header synchronization circuit 352 asserts a synchronization discovery signal 354 indicating that the data received via the read data input 396 is valid user data. Header synchronization circuit 352 can be any circuit known in the art that is capable of synchronizing data sets from user data areas of storage media and claiming material availability indicator signals.

Data processing circuit 353 can be any circuit known in the art that is operable to process encoded data from a storage medium and attempt to reply to an original data set that is encoded and written to the storage medium. For example, data processing circuit 353 can be implemented to include a data detector circuit and a data decoder circuit as are known in the art. Such a data detector circuit can be, but is not limited to, a Viterbi algorithm detector circuit. The decoder circuit can be, but is not limited to, an LDPC decoder circuit. Many data processing circuits that can be used with different embodiments of the present invention will be recognized by those skilled in the art from the disclosure provided herein. For example, the data processing circuit 353 can be the one disclosed in U.S. Patent Application Serial No. 12/114,462, filed on Jan. 8, 2008. Processing one of the circuits. All of the aforementioned references are hereby incorporated by reference for all purposes. In another example, the data processing circuit 263 can be disclosed in U.S. Patent Application Serial No. 12/430,927, the entire disclosure of which is incorporated herein by One of the data processing circuits. All of the aforementioned references are hereby incorporated by reference for all purposes. By way of another example, the data processing circuit 263 can be used in U.S. Patent Application Serial No. 11/341,963, entitled "Systems and Methods for Error Reduction Associated with Information Transfer", filed by Jan et al. One of the disclosed data processing circuits. All of the aforementioned references are hereby incorporated by reference for all purposes.

The data processing circuit 353 provides the decoded data set to the user data separation circuit 356. User data separation circuitry 356 is operable to receive decoded data and implement any de-interleaving that may be required to combine the data into a form that is originally provided as written material 301. In some cases, such interleaving is applied by data encoding circuitry 314 to limit the effects of any local noise in the data by interleaving or mixing user data. The deinterleaved data is then provided by the user data separation circuit 356 as the read data 303.

Turning to FIG. 4a, timing diagram 400 depicts an exemplary write operation of read channel circuit 205 of a third circle in accordance with some embodiments of the present invention. As shown, the encoded data output 293 is a series of data bits that correspond to different regions to be written to the storage medium. In particular, the encoded data output 293 is zero for a period corresponding to the servo data region 403, which is placed on the storage medium as a reference for the presence of the read/write head assembly relative to the storage medium. During the servo data area 403, the servo gate signal 251 is asserted at level 425, indicating to the user data area matching circuit 223 that no data can be written to the storage medium. Once the servo data area 403 is complete, the servo gate signal 251 is de-asserted.

After the solution of the servo gate signal 251, the user data region matching circuit 223 asserts that the write gate signal 287 is at the level 437 while providing a series of data bits corresponding to the user data region 405. In particular, the user profile area matching circuit 223 provides a bit corresponding to the header 415. Header 415 can be used to synchronize the data written in user profile area 405. This header may, for example, include the foregoing as is known in the art, followed by a synchronized pattern. Once the user data area matching circuit 223 completes the write header 415, the user data area matching circuit 223 writes the next code word data available to the own coded data buffer 219. For example, when the user profile before the servo data 403 ends at the codeword boundary, the user profile region matching circuit 223 starts writing the next codeword. Alternatively, when the user profile preceding the servo profile 403 ends in the middle of the codeword, the user profile area matching circuit 223 begins writing at the midpoint of the same codeword. Once the current codeword (i.e., codeword A) is completed, the user profile region matching circuit 223 itself encodes the next codeword (i.e., codeword B), and provides the codeword in tandem as The encoded data is output 293. Once the codeword (i.e., codeword B) is completed, the user profile region matching circuit 223 starts its own coded data buffer 219 to access the next codeword (i.e., codeword C) and provides a portion of the codeword as its own. Encoded data output 293. At some point prior to the end of the user profile area 405, the user profile area matching circuit 223 cuts off the writing of the codeword and then writes the post-amble pattern 491. Such a stencil indicates that the end of the codeword is written to the user area 405. Once the post pattern 491 is written, the user data area matching circuit 223 deasserts the write gate signal 287.

After the end of the user profile area 405, the servo gate signal 251 is again claimed to correspond to the servo data area 407, which is placed on the storage medium as a reference for the presence of the read/write head assembly relative to the storage medium. The assertion of the servo gate signal 251 at level 427 indicates to the user profile area matching circuit 223 that no data can be written to the storage medium. Once the servo data area 407 is complete, the servo gate signal 251 resolves.

After the assertion of the servo gate signal 251, the user data region matching circuit 223 asserts that the write gate signal 287 is at level 439 while providing a series of data bits corresponding to the user data region 409. In particular, the user profile area matching circuit 223 provides a bit corresponding to the header 417. Header 417 can be used to synchronize the data written in user data area 409. This header may, for example, include the foregoing as is known in the art, followed by a synchronized pattern. Once the user data area matching circuit 223 completes the write header 417, the user data area matching circuit 223 writes the remaining portion of the code word C accessed by the own coded data buffer 219 as the encoded data output 293. The user profile area matching circuit 223 continues to write this codeword until it is completed. Once completed, the user profile area matching circuit 223 accesses the next codeword (i.e., codeword D) from the encoded data buffer 219 and provides the codeword as the encoded data output 293 to be written to the storage medium. This procedure continues until near the end of the user profile area 409 where another post-pattern will be written and the user profile area 409 will be completed. It is noted that this method combines one or more codewords into a super-sector data set that is written to the user data area of the storage medium. It is noted that the use of a shared header to synchronize the super-sector data set increases the usable bit density of the user data area.

Turning to FIG. 4b, timing diagram 401 depicts an exemplary write operation of read channel circuit 205 in accordance with FIG. 3 of some embodiments of the present invention. As shown, the read data input 296 is a series of identical data bits that are written to the storage medium in the example of Figure 4a. In particular, the read data input 296 includes a servo data area 403 that is read from the storage medium and used to determine the position of the read/write head assembly relative to the storage medium. During the servo data area 403, the assertion servo gate signal 251 is at level 425, indicating to the header synchronization circuit 252 that it is immediately followed by the header from the user data area 405. As the servo gate signal 251 is asserted, the header synchronization circuit 252 begins the identification process of the header 415 and the synchronized pattern. Once the header 415 is identified, the header synchronization circuit 252 asserts that the synchronization discovery signal 254 is at level 457.

Once the bit associated with header 415 has been received, codeword boundary matching circuit 253 asserts material valid signal 257. After the data valid signal 257 is asserted, the data bit that is provided as the codeword output 259 is stored in the decoded data buffer 256. Codeword boundary matching circuit 253 maintains a count of the number of codeword bits that have been received. This count is continued until the number of remaining bits has been received according to the following formula: number of remaining bits = number of bits in the codeword - number of received codeword bits.

For example, when the total number of bits per codeword is 4,098, and the number of remaining bits is three thousand and ninety-six when receiving a thousand bits from the previous user data area. Bit. Alternatively, when the previous user profile area ends on the codeword boundary, the number of received codeword bits is zero and the number of remaining bits is four thousand and ninety-six. Once the number of remaining bits of codeword A has been received, codeword boundary matching circuit 253 asserts codeword boundary signal 258 (as indicated by 463) indicating the end of codeword A and the next codeword (ie, codeword B). The beginning. Codeword B is then provided to decoded data buffer 256 as codeword output 259. This continues until the number of remaining bits of codeword B is received, at which point a codeword boundary signal 258 (as indicated by 465) is asserted indicating the end of codeword B and the next codeword (ie, codeword C). beginning. Codeword C is then provided to decoded data buffer 256 as codeword output 259 until 491 is identified and the data valid signal 257 is asserted by codeword boundary matching circuit 253. At this moment, the number of received codeword bits (the number of bits in the first portion of codeword C) is less than the number of bits in the codeword. Therefore, this count will be maintained and continued in the subsequent user profile area 409.

The read data input 296 includes a servo data area 407 that is read from the storage medium and used to determine the position of the read/write head assembly relative to the storage medium. During the servo data area 407, the assertion servo gate signal 251 is at level 427, indicating to the header synchronization circuit 252 that it is immediately followed by the header from the user data area 409. As the servo gate signal 251 is asserted, the header synchronization circuit 252 begins the identification process of the header 417 and the synchronized pattern. Once the header 417 is identified, the header synchronization circuit 252 asserts that the synchronization discovery signal 254 is at level 459.

Once the bit associated with header 417 has been received, codeword boundary matching circuit 253 asserts material valid signal 257. After the data valid signal 257 is asserted, the data bit that is provided as the codeword output 259 is stored in the decoded data buffer 256. Codeword boundary matching circuit 253 counts the remainder of codeword C (i.e., the second portion of codeword C), at which point codeword boundary matching circuit 253 asserts codeword boundary signal 258 (as indicated by 467) indicating the codeword The end of C and the beginning of the next codeword (ie, codeword D). Continue this process until you get the information you want to read from the storage media.

Turning to FIG. 5, a flow diagram 500 illustrates a method for accessing a storage medium using a serialized user data set in accordance with some embodiments of the present invention. Flowchart 500 then determines whether a read request is received (block 505) or if a write request is received (block 510). The requested device or system can be, but is not limited to, a processor. The read request may include an address and/or a range of data on the storage medium from which the requested device or system reads the data. The write request may indicate the address and include a data set to be written to the storage medium. In light of the disclosure provided herein, those skilled in the art will recognize that various means or systems are available for various embodiments of the present invention, and/or that can be used to identify that data is being written or read on a storage medium. The address and/or data range of the location.

Upon receiving the read request (block 505), one or more sectors storing the requested material on the storage medium are accessed (block 515), and the corresponding data is retrieved from the sector (block 520). The access and retrieval procedures can be any access and retrieval program known in the art. The received data includes a set of super-sector data that is received and segmented into individual codewords (block 525). This division into individual codewords includes synchronizing with the header data and counting the bits received after the end of the header data. The counter is counted to the number of bits per codeword. When the codeword is spread across the sector boundary, the counter is continued until the end of the user data area and the counter is continued once the bit corresponding to the codeword begins to be received in the subsequent user data area. As the counter reaches the number of bits per codeword, a separate indication between the codewords is asserted, and the first received codeword is combined with the received data. Continue this procedure until all codewords that you have retrieved in the future are separated into individual codewords.

The individual codewords are provided to a data processing circuit where the codewords are decoded to recover the original encoded data to produce the data of the codewords (block 530). Such processing may include, but is not limited to, one or more iterative methods via data detector circuits and data decoder circuits as is known in the art. In one particular case, the aforementioned data detector circuit is a Viterbi algorithm data detector circuit, and the data decoder circuit is an LDPC decoder circuit. Based on the disclosure provided herein, those skilled in the art will recognize various data processing circuits that can be used with different embodiments of the present invention. The decoded codeword is then provided to the requesting device or system (block 535).

Alternatively, upon receiving a write request (block 510), a determination is made as to whether the write request is previously written material (ie, material from the storage medium that has been read and modified) (block 540). When the material has not been previously written (block 540), a new sector (i.e., unused sector) is selected to receive the write data (block 575). The write data is encoded into individual code words (block 580). For example, when the codeword is four thousand and ninety-six bits including sixty added coded bits, the four thousand and thirty bits written into the data are encoded to produce four thousand and ninety-six-bit codewords. . In some embodiments of the invention, as known in the art, the applied encoding is LDPC encoding, and the additional encoding bits are co-located bits that are computed and incorporated in the codeword.

Prepare header data (block 585). This header data may include the previous type and the synchronized pattern. This header data is used for readback to synchronize the data written to the storage medium. Based on the disclosure provided herein, those skilled in the art will recognize various header materials that can be used with different embodiments of the present invention.

One or more of the individual codewords are sequentially coupled to the header data to generate a super-sector data set (block 590). When the amount of data to be written is greater than the amount of data that can be stored in a single sector, another header data is generated and the remaining portion of the data to be written is sequentially connected to the next header data to generate another super sector. Data set. The number of header data and codewords that are combined into a super-sector data set is determined based on the amount of data written as part of the received write request.

The prepared super-sector data set is written to the selected sector (block 595). This can be accomplished using a writing program known in the art. In a particular case, this is accomplished by asserting a write gate signal at a time corresponding to the user data area of the storage medium, at which point the read/write head assembly produces a proximity to the storage medium and The magnetic information is stored in the write field of the storage medium. In light of the disclosure provided herein, those skilled in the art will recognize various methods that can be used to store data on a storage medium. At the end of each super-sector data set, the following pattern is written to the storage medium (block 597). This latter pattern is used on the readback to identify the end of the user's data.

Alternatively, when the data to be written is previously stored to the storage medium (ie, the write program is part of the read/modify program) (block 540), the sector of the original write data is accessed (block 545) and the data from the sectors is retrieved (block 550). The received data includes a set of super-sector data that is received and segmented into individual codewords (block 555). This division into individual codewords includes synchronizing with the header data and counting the bits received after the end of the header data. The counter is counted to the number of bits per codeword. When the codeword is spread across the sector boundary, the counter is continued until the end of the user data area and the counter is continued once the bit corresponding to the codeword begins to be received in the subsequent user data area. As the counter reaches the number of bits per codeword, a separate indication between the codewords is asserted, and the data has been received to combine the next codeword. Continue this procedure until all codewords that you have retrieved in the future are separated into individual codewords. The individual codewords are provided to a data processing circuit where the codewords are decoded to recover the data originally encoded to produce the codewords (block 560). Such processing may include, but is not limited to, one or more iterative methods via data detector circuits and data decoder circuits as is known in the art.

The original data is then overwritten to match the write data associated with the write request (block 565). This may include, for example, modifying the portion of the material that was read back to match the material provided as part of the write request. One or more previously written sectors or one or more new sectors are selected to receive the prepared data set (block 570). Once the sector to be written is selected (block 570), the program of blocks 580 through 597 discussed above is implemented to write the modified material back to the storage medium.

In summary, the present invention provides novel systems, apparatus, methods, formats, and configurations for data storage. While the invention has been described in terms of the embodiments of the present invention, it will be understood that various modifications, modifications, and equivalents may be made without departing from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the scope of the appended claims.

100. . . Storage medium

110. . . Data and support bit pattern

150, 155. . . Magnetic track

160, 165. . . Wedge

152. . . Pre-pattern

154. . . Sector address tag

156. . . Gray code

158. . . Congxun Information

184. . . User profile area

200. . . Storage system

201, 301. . . Write data

203, 303. . . Reading data

205, 306. . . Read channel circuit

213, 314. . . Data encoding circuit

210. . . Read channel

219. . . Coded data buffer

220. . . Interface controller

223, 324. . . User data area matching circuit

227. . . Codeword interface

228. . . Request signal

233, 334. . . Encoder circuit

241, 341. . . Header data insertion circuit

251. . . Servo gate signal

252, 352. . . Header synchronization circuit

253. . . Codeword boundary matching circuit

254, 354. . . Synchronization discovery signal

256. . . Decoded data buffer

257. . . Data valid signal

258. . . Codeword boundary signal

259. . . Code word output

263, 353. . . Data processing circuit

266. . . Hard disk controller

268. . . Motor controller

270. . . Preamplifier

272. . . Spindle motor

273, 374. . . Decoder circuit

276. . . Read/write head assembly

278. . . Disk

287, 387. . . Write gate signal

288, 388. . . Header data

293, 394. . . Coded data output

296, 396. . . Read data input

304. . . Data writing circuit

356. . . User data separation circuit

400, 401. . . Timing circle

403, 407. . . Servo data area

405, 409. . . User profile area

415, 417. . . Header

425, 427, 437, 439, 457, 459. . . Level

463. . . End of codeword A

465. . . End of codeword B

467. . . End of codeword C

500. . . flow chart

A further understanding of the various embodiments of the present invention will be realized by reference to the accompanying drawings. In the drawings, like reference numerals are used to refer to the In some examples, a subtag consisting of lowercase letters is associated with a component symbol to represent one of a plurality of similar components. When the referenced component symbol does not specify an existing subtag, it is intended to refer to all such multiple similar components.

Figure 1 depicts an existing storage medium including servo data;

2 depicts a storage device including a read channel capable of reading and writing a linked user data set in accordance with one or more embodiments of the present invention;

Figure 3a depicts a read channel circuit operable to read and write a linked user data set in accordance with various embodiments of the present invention;

Figure 3b depicts another read channel circuit operable to read and write a linked user data set in accordance with other embodiments of the present invention;

Figure 4a is a timing diagram depicting an exemplary write operation of a read channel in accordance with Figure 3 of some embodiments of the present invention;

Figure 4b is a timing diagram depicting an exemplary read operation of the read channel of Figure 3 in accordance with some embodiments of the present invention;

Figure 5 is a flow diagram showing a method for accessing a storage medium using a linked user data set in accordance with some embodiments of the present invention.

201. . . Write data

203. . . Reading data

205. . . Read channel circuit

213. . . Data encoding circuit

219. . . Coded data buffer

223. . . User data area matching circuit

227. . . Codeword interface

228. . . Request signal

233. . . Encoder circuit

241. . . Header data insertion circuit

251. . . Servo gate signal

252. . . Header synchronization circuit

253. . . Codeword boundary matching circuit

254. . . Synchronization discovery signal

256. . . Decoded data buffer

257. . . Data valid signal

258. . . Codeword boundary signal

259. . . Code word output

263. . . Data processing circuit

273. . . Decoder circuit

287. . . Write gate signal

288. . . Header data

293. . . Coded data output

296. . . Read data input

Claims (26)

A data decoder circuit, the circuit comprising: a codeword boundary matching circuit operable to: receive a first codeword, a second codeword, and a common header data a super sector data set; and dividing the super-sector data set to generate the first codeword and the second codeword, wherein the codeword boundary matching circuit includes a counter operable to Counting the number of bit periods in the super-sector data set and indicating receipt of a complete codeword; and a data processing circuit operable to apply a decoding algorithm to the first codeword to generate a first data set and Applying the decoding algorithm to the second codeword produces a second data set. The data decoder circuit of claim 1, wherein the first data set and the second data set correspond to data originally written to a storage medium. The data decoder circuit of claim 1, wherein the first codeword and the second codeword are low-density parity check encoded data, and wherein the data processing circuit includes a low-density parity Check the decoder circuit. The data decoder circuit of claim 1, wherein the circuit further comprises: a header synchronization circuit operable to: receive the super-sector data set; and synchronize the super with the common header data Sector data set. For example, the data decoder circuit of claim 1 of the patent scope, wherein The data decoder circuit is implemented as part of a storage device. A data encoder circuit, the circuit comprising: a data encoding circuit operable to receive write data and encode the write data into a first codeword and a second codeword; a user data circuit Operating to combine the first codeword, the second codeword, and a header data to form a first super-sector data set; and wherein the data encoding circuit is further operable to encode the write data into a third a codeword, wherein the user profile circuitry is further operable to include at least a first portion of the third codeword in the first super-sector data set, and wherein the user profile circuitry is further operable to A second portion of the third codeword is included in a second super-sector data set. The data encoder circuit of claim 6, wherein the data encoding circuit is a low density parity check encoding circuit, wherein the first codeword is a first low density parity check encoded codeword, and wherein The second codeword is an encoded codeword of a second low density parity check. The data encoder circuit of claim 6, wherein the header data comprises a preamble field and a synchronization field. The data encoder circuit of claim 6, wherein the super-sector data set includes more than twice the number of bit periods in the first codeword and less than a user data area of a storage medium. The number of bit periods. The data encoder circuit of claim 6, wherein the data encoder circuit is implemented as part of a storage device. A data processing circuit, the circuit comprising: a codeword boundary matching circuit operable to: receive a super-sector data set having a first codeword from a storage medium, one from the storage medium a second codeword and a common header data obtained from the storage medium; and dividing the super-sector data set to generate the first codeword and the second codeword; and a data decoder circuit operable to Transmitting a decoding algorithm to the first codeword to generate a first data set; and applying the decoding algorithm to the second codeword to generate a second data set. The circuit of claim 11, wherein the first codeword and the second codeword are coded codewords for low density parity check. The circuit of claim 11, wherein the portion of the first codeword is all of the first codeword, and wherein the portion of the second codeword is less than all of the second codeword. The circuit of claim 11, wherein the circuit further comprises: an encoder circuit operable to: receive the write data; encode the write data into the first codeword and the second codeword; And combining the portion of the first codeword with the portion of the second codeword and the shared header data to form a super-sector data set. The circuit of claim 14, wherein the encoder circuit comprises a low density parity check encoder, and wherein the first codeword and the The second codeword is an encoded codeword for low density parity check. The circuit of claim 14, wherein the encoder circuit further comprises a user data area matching circuit, and wherein the user data area matching circuit is operable to combine the portion of the first codeword with the first The portion of the two codewords and the shared header data become the super-sector data set. The circuit of claim 14, wherein the super-sector data set comprises more than twice the number of bit periods in the first codeword and less than the number of bit periods in the user data area. The circuit of claim 11, wherein the portion of the first codeword, the portion of the second codeword, and the shared header data are combined in a super-sector data set, and wherein the data storage system Further comprising: a decoder circuit operable to: receive the super-sector data set; synchronize the super-sector data set with the common header data; and segment the super-sector data set to generate the first codeword The portion and the portion of the second codeword; and decoding the first codeword and the second codeword to generate an original write data set. The circuit of claim 18, wherein the decoder circuit comprises a low density parity check decoder, and wherein the first codeword and the second codeword are low density parity check coded codewords. The circuit of claim 11, wherein the user data area is a first user data area, wherein the storage medium is further The third servo data area is separated from the second servo data area by a second user data area, wherein the part of the second codeword is the first part of the second codeword, and wherein the second code The second portion of the word is included in the second user profile area. The circuit of claim 11, wherein the data decoder circuit is implemented as part of a storage device. A data encoder circuit, the circuit comprising: a data encoding circuit operable to receive write data and encode the write data into a first codeword and a second codeword; a user data circuit operable Forming a first super-sector data set by combining the first codeword, the second codeword, and a header data, wherein the super-sector data set includes more than twice the bit in the first codeword The number of cycles, and less than the number of bit periods in the user profile area of the storage medium. The data encoder circuit of claim 22, wherein the data decoder circuit is a low density parity check encoding circuit, wherein the first codeword is a first low density parity check encoded codeword, and wherein The second codeword is an encoded codeword of a second low density parity check. For example, the data encoder circuit of claim 22, wherein the header data includes a preamble field and a synchronization field. The data encoder circuit of claim 22, wherein the super-sector data set is a first super-sector data set, wherein the data encoding circuit is further operable to encode the write data into a third code a word, wherein the user profile circuit is further operable to include at least a first portion of the third codeword in the first super-sector data set, and wherein the The user profile circuitry is further operable to include a second portion of the third codeword in a second super-sector data set. The data encoder circuit of claim 22, wherein the data encoder circuit is implemented as part of a storage device.