TWI523023B - Ecc method for memory - Google Patents

Description

Error correction code method for memory

This case is related to memory devices and systems including Error Correction Code (ECC) logic.

The memory technology for integrated circuit memory is evolving toward smaller and smaller technologies and is applied to larger and larger memory arrays of a single integrated circuit. As the technology of Memory Cell advances, the tolerance for sensing data becomes more rigorous. Moreover, when the disturbance of the memory cell state (caused by accessing the memory cell and accessing the high speed and high volume of the adjacent memory cell) exists, the ability of the memory cell to retain the data value (ie, persistence) is more limited by Rigorous tolerance.

When these techniques focus on size and density, the use of error correction codes (ECC) embedded in integrated circuit memory has become more popular in order to address critical issues arising from more stringent tolerances and memory cell perturbations.

Flash memory is typically designed to erase a block at a time by block erasing. When a block is erased, the memory cells in the block are set to a logical value, such as 1. After erasing a block, the memory cells in the block can be programmed to different values, such as zero. Once the memory cell is programmed to zero, block erase of the block of the stylized memory cell can change the memory cell back to 1. Once in a block A memory cell (eg, a byte selected in one of the blocks or a cell in a word) is programmed to 0 during a first programming operation, in a different byte of the same block or The other memory cells in the word (known to be in the erased state) can still be programmed to zero during a second programming operation without the need to pre-erase the block. In the present description, a block erasing along with a first programming operation and a second programming operation for different locations in the same block may be referred to as double patterning. Of course, when each programming operation is directed to a different portion of the block to achieve a "multiple patterning operation," the block erase operation can be accompanied by multiple programming operations (two or more).

In a dual or multiple patterning operation, an error correction code (ECC) can be calculated and programmed into a particular location in the block during the first programming operation. However, because the block erases the relationship of the second programming operation in one of the memories, the ECC cannot be safely changed. The ECC cannot be safely changed in the second programming operation because the ECC calculated repeatedly must change at least one bit in the ECC from 0 (stylized state) to 1 (erased state), and this The change will require a block erase, which will erase the data in the entire block.

Preferably, a solution is provided for reliably controlling the use of ECC logic for error detection and correction of double patterning and multiple patterning operations.

A method of operating a memory includes: storing a plurality of data sets (eg, paging), and a plurality of error correction codes ECC for the data set in the memory, the data set including a plurality of addressable segments (eg, words or bytes) ). When writing new data When one of the memory selects one of the addressable segments of the data set, if the new data is stored and some of the addressable segments of the data that were previously programmed in the selected data set include at least a predetermined number of addressable segments , you can calculate and store an ECC for the selected data set. The predetermined number may be all of the addressable segments of the selected data set.

A plurality of indications can be stored with the data set indicating whether the enabling or disabling of the ECC stored with the data set is enabled. These indications may be provided by storing extended ECC (eg, xtECC[9:0] for 128-bit data), which extends one of the ECC fields of the data set (eg, 128-bit data for xtECC[7: 0]), a field of a first additional ECC bit derived from the ECC (eg, xtECC[8]) and a second additional ECC bit are used in a field (eg, xtECC[9]). A first extra ECC bit is derived by performing a logical exclusive-OR function on the ECC. Extended ECC can indicate whether the use of ECC stored with the data set is enabled or disabled.

The extended ECC may have a first predetermined value (eg, 9'h000 for 128-bit data), a second predetermined value (eg, 9'h1C0 for 128-bit data), and a calculated value, the first predetermined value for the first An extra bit is used with the ECC to indicate a first state to disable the use of data in the field of the ECC, the second predetermined value being used by the first extra bit and the ECC to indicate a second state in which the ECC is extended The original has a calculated value equal to one of the first predetermined values, and the calculated value represents a third state, including a plurality of calculated ECCs in the field of the ECC, and a first additional ECC derived from the calculated ECC One of the bits in the bit field.

This method includes: if you store new data and select the data set in advance Some of the addressable segments of the stylized data include at least a predetermined number (eg, all) of addressable segments, and one of the selected data sets is used to extend the calculated value of one of the ECCs, and an error condition does not occur (in In this error condition, the selected data set has been programmed in the addressable section of the new data.

The method includes: if the selected data set is pre-programmed with the addressable segment for the new data, the extended ECC is set to a first predetermined value to indicate the use of the ECC that is disabled and stored with the selected data set. The method includes setting the extended ECC to a second predetermined value if the extended ECC is equal to the first predetermined value and the selected data set is not programmed in the addressable segment of the new data.

The method further includes setting the second additional ECC bit to a value indicating that the selected data set is stylized in the at least one addressable segment. A blank or unstylized state can result from a block erase of the data set such that one of the ECCs located in the blank ECC state includes all "1"s. After a block erase, the first additional ECC bit also includes a value of '1'. One of the ECC calculations may also be all "1", and the first additional ECC bit of the ECC shall have a number '0', as explained herein. However, in the case of a reservation error, the first additional ECC bit may be erroneously changed to '1'. In that case, in order to determine whether the use of ECC should be enabled, a read operation cannot resolve ECCs that are all "1s", and whether the first extra ECC bits with a value of "1" are calculated values. Or in the erase state. The second additional ECC bit is thus used to indicate whether the selected data set is stylized in at least one addressable segment.

Includes an ECC (eg xtECC[7:0] of 128-bit data), one One of the first additional ECC bits (eg, xtECC[8]) and a second additional ECC bit (eg, xtECC[9]) extends the ECC (eg, xtECC[9:0] of 128-bit data), A selection data set is read, and the first additional ECC bits are derived from the ECC by using a logic function. If the logic function of the ECC is equal to the first additional ECC bit and the ECC is not equal to the first predetermined value representing the first state to disable the use of the ECC, then the use of the ECC stored with the selected data set may be enabled.

The method includes setting the ECC to a first predetermined value indicative of the first state (e.g., 9 'h000), and then enabling use of the ECC having the selected data set. The logic function may be a logical mutually exclusive function, if the logic function of the ECC is not equal to the first additional ECC bit, and the ECC is equal to the second predetermined value (eg, 9'h1C0) (representing the second state, where the ECC originally has equal to the first If one of the predetermined values is calculated).

The method includes: reading a second additional ECC bit indicating whether the selected data set is programmed in at least one addressable segment; and enabling use of the ECC stored with the selected data set, if the logic function of the ECC Not equal to the first additional ECC bit, the ECC is equal to one blank value indicating a blank ECC state (eg, 8'hFF), and the second additional ECC bit indicates that the selected data set is stylized in at least one addressable segment if. A blank ECC state can result from a block erase of the data set such that ECC located in one of the blank ECC states is in an erased state, such as all "1"s. The first and second predetermined values for the first and second states are predetermined to be different from the blank value.

In order to better understand the above and other aspects of the case, the following The preferred embodiment is described in detail with reference to the accompanying drawings, as follows:

100‧‧‧ memory

105‧‧‧ data bus

110‧‧‧ Controller

120‧‧‧ Bias Configuration Power Supply Voltage Block

130‧‧‧ Busbars

140‧‧‧ column decoder

145‧‧‧ word line

150‧‧‧ECC Logic

155‧‧‧ signal

160‧‧‧ data set

165‧‧‧ bit line

170‧‧ ‧ page buffer

175‧‧‧ data bus

190‧‧‧Input/Output Circuit

210‧‧‧First partial data set programming operation

211‧‧‧Other addresses

212‧‧‧Array of ECC

213‧‧‧First extra ECC bit and second extra bit

220‧‧‧Second partial data set programming operation

221‧‧‧Other addresses

222‧‧‧ ECC of the data set

223‧‧‧First extra ECC bit and second extra bit

230‧‧‧Last local array operation

232‧‧‧ECC

233‧‧‧First additional ECC bits

305, 310, 320, 330, 340, 341, 343, 350, 360, 365, 370, 375, 380, 385, 390 ‧ ‧ steps

410, 420, 430, 440, 451, 453, 460, 470, 480, 490 ‧ ‧ steps

510, 520, 530, 550, 551, 560, 561, 563, 570, 571 ‧ ‧ steps

1 is a simplified wafer block diagram of an integrated circuit memory in accordance with an embodiment.

Figure 2 shows the local data set programming operation in a memory.

Figure 3 is a flow chart of the programming operation in a memory.

Figure 4 is a flow chart for ECC generation using extended ECC.

Figure 5 is a flow chart of a read operation using extended ECC.

A detailed description of a plurality of embodiments of the present invention is provided below with reference to the accompanying drawings.

As the technical size of the memory cells in the memory of the integrated circuit is reduced, the tolerance for sensing data becomes more rigorous, and thus the disturbance of the memory cell state (by accessing the memory cell and accessing the adjacent memory cell) In the presence of high speed and high volume, the ability of the memory cell to retain data values is limited. In order to deal with issues arising from more stringent tolerances and memory cell perturbations, an error correction code (ECC) embedded in the integrated circuit memory can be used.

A complete data set programming operation is to program a set of data located at each address in the data set. When a data set (eg, a paged memory cell) is programmed with a full data set programming operation, the ECC of the data set can be calculated and stored with the data set. A partial data set programming operation is used to locate The data set of some, but not all, addresses in the collection is stylized. When a data set is programmed using a first partial data set programming operation, the ECC of the data set can be calculated and stored with the data set. However, when a data set is programmed using a second partial data set programming operation after the first partial data set programming operation, the ECC of the data set cannot be updated (for the reasons explained below), thereby utilizing multiple Local dataset programming operations and stylized datasets may fail using ECC.

The present technique provides control logic by using an extended error correction code ECC for enabling the use of ECC for a data set that is programmed by multiple local data set programming operations. The extended error correction code ECC includes the ECC of the data set, each One of the data sets is a first additional ECC bit and a second additional ECC bit.

1 is a simplified wafer block diagram of an integrated circuit memory in accordance with an embodiment. In the example shown in FIG. 1, a memory 100 stores a plurality of data sets 160, which include a plurality of addressable segments and an extended error correction code ECC of the data set. The extended ECC includes an ECC of the data set, one of the first additional ECC bits of each data set, and a second additional ECC bit.

In the example shown in FIG. 1, a controller 110 using a bias configuration state machine controls the bias configuration (eg, reading and programming using the voltage source generated or provided by the voltage source or power supply of block 120). Application of voltage). The controller 110 is coupled to the page buffer 170, the ECC logic 150, and the data set 160 having an extended ECC (including the first and second additional ECC bits). ECC logic 150 is coupled to paged buffer 170 via a plurality of signals 155.

In a programming mode, the logic included in the controller 110 can calculate and store an ECC for the selected data set when the new data is written into one of the addressable segments of the selected data set in the memory, if stored. The new information and some of the addressable segments of the data that were previously programmed in the selected data set include at least a predetermined number of addressable segments. The predetermined number of addressable segments may be all of the addressable segments of the selected data set. For example, as shown in FIG. 2, for a final partial array operation (eg, 230), new material (eg, final word word _x ) and data previously programmed in the selected data set (eg, word ₀ ) are stored. Some of the addressable segments up to word _x-1 ) include all of the addressable segments of the selected data set. Therefore, the ECC (232) of the selected data set is calculated and stored with the selected data set.

A plurality of indications can be stored with the data set indicating whether the use of the ECC stored with the data set is enabled or disabled. These indications may be provided by storing an extended ECC (including one of the ECC fields of the data set and one of the first additional ECC bits derived from the ECC). Extended ECC indicates whether the use of ECC stored with the data set is enabled or disabled. Controller 110 further includes logic for storing a second additional ECC bit for the selected data set to indicate that the selected data set is stylized in at least one addressable segment.

In a read mode, the controller 110 includes logic to read an extended ECC (including an ECC and a first additional ECC bit) from a selected data set, where the first additional ECC bit is borrowed. It is derived from ECC by using a Logical Function. If the logic function of the ECC is equal to the first additional ECC bit, and the ECC is not equal to indicating the first predetermined value of one of the first states of the ECC use disable, the logic included in the controller 110 may enable the ECC (which And election Use the data set to be stored together). By using the second additional ECC bit, the logic included in controller 110 can enable the use of an ECC of a blank data set.

Controller 110 can be implemented using a Special-Purpose Logic Circuitry as is known in the art. In an alternate embodiment, the control logic includes a general-purpose processor that can be implemented on the same integrated circuit, the general purpose processor executing a computer program to control the operation of the device. In still other embodiments, the control logic can be implemented using a combination of special purpose logic circuitry and a general purpose processor.

In the example shown in FIG. 1, a column of decoders 140 is coupled to a plurality of word lines 145 and arranged along columns in the data set 160. The page buffer 170 is coupled to a plurality of bit lines 165 arranged along the plurality of rows in the data set 160 for reading data from the data set 160 and writing the data to the data set 160. A plurality of addresses are provided from the controller 110 to the page buffer 170 and the column decoder 140 on the bus bar 130. The page buffer 170 can include a row decoder coupled to the data set 160 and the bus 130, and a plurality of sense amplifiers for read operations, and a program buffer coupled to the programming operations of the row decoder. In this example, the page buffer 170 is coupled to the input/output circuit 190 via the data bus 175. The input/output circuit 190 drives the data to a target external to the memory 100. The input/output data and control signals are moved through the data bus 105, which is interposed between the input/output circuit 190, the controller 110 on the memory 100, and the input/output port or other internal or external memory 100. Source of data (such as a general purpose processor or special purpose application circuit, or a system list supported by data set 160) Between one of the modules of the chip function).

Fig. 2 shows a partial data set programming operation in the memory according to the present embodiment. In the example shown in Figure 2, the memory stores, for example, a paged data set. The data set includes a plurality of addressable segments (eg, words or bytes) and error correction codes ECC for the data sets of the memory. Each data set may also include a first additional ECC bit and a second additional bit. As explained in the present case, a data set includes an extended ECC, and the extended ECC includes one of a data set ECC, a first additional ECC bit, and a second additional bit. In the example shown in FIG. 2, during a first partial data set programming operation (eg, 210), a first word (eg, word ₀ ) is programmed in one of the first addresses in a data set, and Other addresses in the dataset remain unprogrammed (eg, 211). The ECC of the array (e.g., 212) is not programmed during the first partial data set programming operation and remains in a blank or unprogrammed state. After the first partial data set programming operation (e.g., 210), the first additional ECC bit and the second additional bit (e.g., 213) are also maintained in a blank or unstylized state.

A blank ECC state may result from a block erase of the data set such that one of the ECC states located in the blank ECC state includes an erase status value, such as all "1s". For example, if an ECC includes 8 bits, the blank ECC status of the ECC is equal to "11111111" or the erased state value. After a block erase, the ECC may have a blank value (eg, "11111111") indicating a blank ECC state. The first additional ECC bit and the second additional ECC bit of the data set as described herein may also have an erase value (eg, '1') after a block erase. Number of different bits The ECC corresponds to different length data. For example, the 8-bit ECC is used for 128-bit data. For an 8-bit ECC of a data set, the extended ECC of the data set includes 10 bits, including 8 bits of ECC, 1 bit of the first additional ECC bit, and 1 bit of the second additional ECC bit. yuan.

During a second partial data set programming operation (e.g., 220), a second word (e.g., word ₁ ) is programmed in the second address of one of the data sets, while other addresses in the data set remain unprogrammed (eg 221). The ECC of the data set (e.g., 222) is not programmed during the second partial data set programming operation and is maintained in a blank ECC state. The first additional ECC bit and the second additional bit (e.g., 223) are also maintained in a blank or unstylized state after the second partial data set programming operation (e.g., 220).

Additional local dataset programming operations can be performed to program more words in the dataset until the dataset is programmed for all of the addresses in the array. As shown in FIG. 2, in a final partial array operation (eg, 230), a word between a second word (eg, word ₁ ) and a final word (eg, word _x ) (eg, word ₂ ~word _{x) -1} ) After the data set is stylized, a final word (such as word _x ) is stylized in the last address of one of the data sets. When the final word of the data set (eg word _x ) is stylized, the ECC (eg 232) of the data set is calculated and stored with the data set. The first additional ECC bit (e.g., 233) may also be calculated during the last partial data set programming operation (e.g., 230) and stored with the data set. Thus, during a read operation, when a multiple local data set stylization operation is used to program the data set, the use of ECCs stored with the data set can be enabled. The first additional ECC bit and the second additional bit are further described with reference to FIGS. 4 and 5. More specifically, when at least one address of the data set is stylized, the second extra bit is stylized.

In one embodiment, the address in the data set increases in the direction from the first word to the final word, where the first word is located at the lowest address and the final word is located at the highest address in the data set. In an alternate embodiment, the address in the data set increases in the direction of the final word to the first word, where the first word is at the highest address and the final word is at the lowest address in the data set.

The control logic is illustrated in conjunction with Figures 3, 4, and 5, which are used to calculate and store the ECC when the final word in a data set is programmed, and to be enabled to be stored with the data set during a read operation. The use of ECC.

Figure 3 is a flow chart of the programming operation of the memory. In the example shown in FIG. 3, in step 305, new data is received from one of the addressable segments of one of the memory selection data sets. In step 310, it is determined whether the programming operation of the new data is a complete data set programming operation or a partial data set programming operation. If the programming operation for the new data is a complete data set programming operation (step 310, YES), then in step 320 an error correction code ECC is calculated for the new data. At step 330, it is checked if the data set is stylized at any address. If the dataset is not stylized at any address, the dataset is called a blank. If the data set is blank (step 340, yes), then in step 341, the data set is stylized along with the new data and the ECC calculated from the data set. If the data set is stylized or not blank at any address (step 340, no), then in step 343, the data set is accompanied by the new data. The ECC is set to a first predetermined value (eg, 9'h00) indicating one of the first states of use of the disabled ECC. The first state is further illustrated in connection with Figure 4. Alternatively, step 320 for calculating ECC for new material may be performed after step 340 (when determining that the data set is blank) and before step 341 (when ECC is programmed).

If the programming operation of the new data is not a complete data set programming operation but a partial data set programming operation (step 310, No), then in step 350, the data set is checked to determine if the address of the new data is blank or Stylized. If the address of the data set in the new data is not blank (step 360, no), then the data set is stylized with the new data and the ECC is set to the first predetermined value (eg 9'h00) ), which indicates the first state of use of the disabled ECC (step 365). The first state is further illustrated in connection with Figure 4.

If the address of the data set in the new data is blank (step 360, yes), then it is determined whether the data set is stylized at the first or last address of the data set (step 370). If the data set is stylized in the first or last address of the data set (step 370, yes), it is further determined whether the data set is blank at other addresses that are not the address of the new data (step 380). ). If not (step 380, no), the new data and other stylized data in the data set may be filled with the data set. Therefore, if the addressable segment storing the new data and the data previously programmed in the selected data set includes at least a predetermined number of addressable segments, a value is calculated for the ECC of the selected data set (step 385). The predetermined number may be all of the addressable segments of the selected data set. In step 390, the data set and the new data and selection resources The ECC of the material set is programmed together.

If the data set is not stylized at the first address, and the last address in the data set is not stylized (step 370, no), or if the data set is at some address (non-new data is used) The address is blank (step 380, yes), and the new data and the data that was previously programmed in the selected data set cannot fill the data set. Therefore, the new data is stylized (step 375), but the ECC is not calculated until the new data and the data previously programmed in the selected data set fill the selected data set.

The hexadecimal and binary representations are used in this case. For example, "8'hFF" is a representation of the hexadecimal number of an 8-bit binary digit "8'b11111111", where each of the binary digits has a value of '1'. "8" in "8'hFF" or "8'b11111111" indicates the number of bits. "h" in "8'hFF" indicates hexadecimal, and "b" in "8'b11111111" indicates binary. The number after "h" in "8'hFF" is a hexadecimal number. The number after "b" in "8'b11111111" is a binary number. The hexadecimal number includes 16 values: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F, which are equal to 0000, 0001 in the binary, respectively. , 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, and 1111. Therefore, "8'hFF", "8'h00", and "8'hC0" in the hexadecimal are equal to "8'b11111111", "8'b00000000", and "8'b11000000" in the binary respectively. For another example, 1'b0 is a binary number that includes only one bit with a value of '0', and 1'b1 is a binary number that includes only one bit with a value of '1'.

Figure 4 is a flow chart for ECC generation using extended ECC. In the example shown in Figure 4, a data set has 128 bit data and the ECC of the data has 8 bits. A plurality of indications can be stored with the data set to indicate whether the use of ECC (stored with the data set) is enabled or disabled. These indications may be provided by storing extended ECC (eg, xtECC[9:0] for 128-bit data), which extends one of the ECC fields of the data set (eg, xtECC[7:0]), derived from ECC. A field of one of the first additional ECC bits (eg, xtECC[8]) and a field of a second additional ECC bit (eg, xtECC[9]). The first additional ECC bit may be derived by performing a logical mutex function (XOR) on the ECC. The length of the ECC varies with the length of the data, and thus the length of the extended ECC varies with the length of the data. For example, in an alternate embodiment, the ECC of 256-bit data has 9 bits (eg, xtECC[8:0]), and the extended ECC of 256-bit data has 11 bits (eg, xtECC[10:0] ]), including the first extra bit (eg xtECC[9]) and the second extra bit (eg xtECC[10]).

The extended ECC may have a first predetermined value (eg, 9'h000), a second predetermined value (eg, 9'h1C0), and a calculated value; the first predetermined value indicates one of the fields in the field of the disabled ECC. a second predetermined value indicating a second state in which the extended ECC originally has a calculated value equal to the first predetermined value; and the calculated value indicates a third state including a plurality of calculated values in the ECC field The ECC and a bit in the field of the first additional ECC bit derived from the computed ECC. In this example, both the first predetermined value and the second predetermined value are the first extra bit of the extended ECC of 128-bit data and the ECC.

The first, second and third states are summarized in the table in Figure 4. When the ECC is set to a first predetermined value (e.g., 9'h000) to disable the use of the ECC, the first state corresponds to the (Yes) branch of step 460 and step 470. When the ECC is set to a second predetermined value (e.g., 9'h1C0) to indicate that the ECC is originally a calculated value equal to the first predetermined value, the second state corresponds to the (Yes) branch of step 440 and step 451. When the calculated use of ECC is enabled, the third state corresponds to the No (No) branch of step 440 and step 453.

The ECC generation process begins at step 410 where the ECC of the data set is calculated by steps 341, 343, 390, 375, and 365 as shown in FIG. For a plurality of reasons described herein, the decision may be such as not to calculate an ECC (step 410, no), such as corresponding to steps 375, 343, and 365, or to calculate an ECC (step 410, yes), as corresponding to the steps. 341 and 390.

If it is decided not to calculate the ECC (step 410, no), it is further determined whether the use of the read ECC is disabled (step 460). This decision may be to disable the use of the ECC of a read operation (step 460, no) because the local data set programming operation has not yet programmed a complete data set (step 375). If the decision is to disable the use of the ECC for a read operation (step 460, no), then the new data received in step 305 is stylized in memory without the need to store ECC for any new data. (Step 480). This decision may be the use of the ECC that disables the read operation (step 460, yes) because a data set is not blank for a complete data set programming operation (step 343), or because a data set is one The local data set programming operation is programmed for the address of the new data (step 365). If the decision is to disable the use of the ECC for a read operation (step 460, yes), then in the step 470. Set the first extra bit and the ECC in the extended ECC of the data set to a first predetermined value (eg, xtECC[8:0]=9'h000), thereby indicating that the ECC is disabled in a read operation ( Used in conjunction with the data set).

If the decision in step 410 is to calculate an ECC (step 410, YES), such as step 341 corresponding to a complete data set programming operation, or a step corresponding to a partial data set programming operation (the final word in the programmed data set) 390. At step 420, calculate the value of the ECC of the data set. At step 430, this value is derived from the first additional ECC bit from the ECC. This value can be derived by performing a logical mutual exclusion function (XOR) on the ECC (eg, xECC[8]=XOR(xtECC[7:0]). The extended ECC including the first additional ECC bit and ECC, Can be used in a read operation to indicate whether the use of ECC (stored with the data set) is enabled or disabled.

At step 440, it is determined whether the ECC is equal to the first predetermined value indicative of the first state, as used in step 470. If so (step 440, yes), then a special case occurs where the calculated value for the extended ECC may be 9'h000, corresponding to the first state of step 470, thereby erroneously indicating the use of the disabled ECC. In order to solve the special case, the first extra bit in the extended ECC and the ECC are set to a second predetermined value indicating a second state (for example, xtECC[8:0]=9'h1C0), wherein the extended ECC original has equal to The calculated value of the first predetermined value. In a read operation as described in connection with Fig. 5, the special case is reversed (steps 550 and 551, Fig. 5). If the ECC is not equal to the first predetermined value indicating the first state, then in step 453, the extended ECC including the first additional ECC bit and the ECC is unchanged.

After step 451, 453 or 470, the second additional ECC bit may be set to a value indicating the stylized state (eg xtECC[9]=1'b0) for indicating that the selected data set is at least one editable The address segment is stylized, so the dataset is not a blank dataset. The second additional ECC bit can thus be used to protect a blank data set, as explained in connection with FIG. The extended ECC (e.g., xtECC[9:0]) of the new and new data received in step 305 can be programmed in the data set of the memory (step 490).

Figure 5 is a flow chart of a read operation using extended ECC. In the example shown in Figure 5, the data in a data set (for example, 128-bit data) and the extended ECC (for example, xtECC[9:0]) are read from the memory; the extended ECC includes the ECC of the data in a data set. (e.g., xtECC[7:0]), a first additional ECC bit (e.g., xtECC[8]), and a second additional ECC bit (e.g., xtECC[9]) (step 510). The first additional ECC bits are derived from the ECC by using a logic function. The same logic function used to derive the first additional ECC bits stored in the data set is performed on the ECC, and then determines whether the first additional ECC bit read from the data set is equal to the result from the logic function (step 520). .

The first state, the second state, the third state, and a blank ECC state used in the reading flow are summarized in the table of FIG. When the use of the ECC is disabled, the first state corresponds to the (Yes) branch of step 560 and step 561. When the ECC is inverted to equal the original value representing the first predetermined value of the first state, the second state corresponds to the (Yes) branch of step 550 and step 551. When the calculated use of ECC is enabled, the third state corresponds to step 563.

If the first additional ECC bit (e.g., xtECC[8]) read from the data set is equal to the result from the logic function (step 520, YES), it is further determined whether the ECC is equal to the first predetermined value indicating the first state ( For example xtECC[7:0]=8'h00). If not (step 560, no), the extended ECC (e.g., xtECC[8:0]) indicates that the data set is programmed by a complete data set (step 341) or one of the final words of the stylized data set. The set programming operation (step 390) is programmed along with the ECC. Thus, the use of ECC (stored with the data set) is enabled (step 563).

In step 560, if the ECC is equal to the first predetermined value indicating the first state (eg, xtECC[7:0]=8'h00), the use of ECC (stored with the data set) is not enabled (step 561). This is because the first state indicates the use of the data in the field of the disabled ECC (steps 470, 4).

If the first additional ECC bit read from the data set (eg, xtECC[8]) is not equal to the result from the logic function (step 520, No), then the ECC may be equal to indicating a second predetermined value of the second state ( xtECC[7:0] = 8'hC0), ECC is equal to the blank value indicating the blank ECC status (xtECC[7:0] = 8'hFF), or the extended ECC has changed due to a reservation error. It is further determined whether the ECC is equal to the first predetermined value indicating the first state (e.g., xtECC[7:0] = 8'h00). If so (step 530, YES), the use of the ECC stored with the data set is not enabled (step 540). If not (step 530, no), it is further determined whether the ECC is equal to whether the second predetermined value of the second state is indicated (e.g., xtECC[7:0] = 8'hC0), as set for the special case (step 451). , Figure 4). If ECC Equal to indicating the first predetermined value of the second state (step 550, YES), then setting the ECC to a first predetermined value (eg, xtECC[7:0]=8'h00), and then enabling storage with the data set Use of ECC (step 551).

If the ECC is not equal to the second predetermined value indicating the second state (step 550, no), then in step 570, it is further determined whether the ECC is equal to a blank value indicating a blank ECC state (eg, xtECC[7:0]=8 'hFF). If the ECC is not equal to a blank value indicating a blank ECC state, then the use of the ECC stored with the data set is not enabled (step 561).

In step 570, if the ECC is equal to a blank value indicating a blank ECC state (eg, xtECC[7:0]=8'hFF), it is further determined whether the second additional ECC bit is stylized (eg, xtECC[9]= 1'b0), indicating that the data set is not blank. If the data set is not blank (step 571, no), then the use of the ECC stored with the data set is not enabled (step 561). Since the data set is not blank, an error has occurred, as indicated by the fact that the first additional ECC bit read from the data set is not equal to the result from the logical function (step 520, no). If the data set is blank (eg, xtECC[9]=1'b1. Step 571, yes), then the use of the ECC stored with the data set is enabled as a blank data set (step 572), thereby protecting A blank data pattern in one of the data sets.

In summary, although the present invention has been disclosed above in the preferred embodiment, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the present case. Therefore, the scope of protection of this case is subject to the definition of the scope of the patent application attached.

305, 310, 320, 330, 340, 341, 343, 350, 360, 365, 370, 375, 380, 385, 390 ‧ ‧ steps

Claims (9)

A method of operating a memory, comprising: storing a plurality of data sets and a complex error correction code (ECC) of the data sets in the memory, the data sets comprising a plurality of addressable segments; when writing new data When in one of the addressable segments of the addressable segment of the selected data set in the memory, if the new data is stored and the addressable segment of the data that was previously programmed in the selected data set is Comprising at least a predetermined number of addressable segments, calculating and storing one of the selected data sets; and storing a plurality of indications for the data sets, the indications indicating whether to enable or disable the data sets The use of these ECCs that are stored. The method of claim 1, comprising: storing a plurality of extended ECCs, including a field of the ECCs of the data sets, and one of the first additional ECC bits derived from the ECC. Field. The method of claim 2, wherein the extended ECC has a first predetermined value, a second predetermined value, and a calculated value, the first predetermined value indicating a first state for disabling the The use of the data in the field of the ECC, the second predetermined value indicating a second state, wherein the extended ECCs originally have a calculated value equal to one of the first predetermined values, and the calculated value represents a third a state comprising a plurality of calculated ECCs in the field of the ECCs, and a bit in the field of the first additional ECC bits derived from the calculated ECC; if stored The new information and the funds previously stylized in the selected data set The optional data may be used if the addressable segment includes at least a predetermined number of addressable segments, and an error condition that the selected data set has been programmed in the addressable segment of the new data does not occur One of the sets of extended ECC calculation values; if the selected data set is programmed in a first addressable segment or a final addressable segment of the number of addressable segments of the selected data set, and the selection The data set is used if the other address of the address other than the new data is stylized; if the selected data set is pre-programmed in the addressable segment of the new data, And then setting the extended ECC to the first predetermined value, thereby indicating that the use of the ECCs that are stored together with the selected data set is disabled; if the extended ECC is equal to the first predetermined value, and the selected data set is not And if the new data is programmed for the addressable segment, the extended ECC is set to the second predetermined value; and the extended ECC includes a field of a second additional ECC bit, including The second additional ECC bit is set to a value, It indicates that the selected data set is based at least in a stylized addressable segments. A method of operating a memory, the memory storing a plurality of data sets including a plurality of addressable segments and a plurality of error correction codes (ECCs) of the data sets in the memory, the method comprising: Selecting a data set to read an extended ECC, the extended ECC including an ECC and a first additional ECC bit, wherein the first additional ECC bit is derived from the ECC by using a logic function; If the logic function of the ECC is equal to the first additional ECC bit, and the ECC is not equal to a first predetermined value, enabling use of the ECC stored with the selected data set, wherein the first predetermined The value represents a first state to disable the use of the ECCs. The method of claim 4, comprising: if the logic function of the ECC is not equal to the first additional ECC bit, and the ECC is equal to a second predetermined value, setting the ECC to the first A predetermined value is then enabled for use of the ECC associated with the selected data set, wherein the second predetermined value represents a second state, the ECC originally having a calculated value equal to one of the first predetermined values. The method of claim 4, comprising: reading a second additional ECC bit, the second additional ECC bit indicating whether the selected data set is stylized in at least one addressable segment; If the logic function of the ECC is not equal to the first additional ECC bit, the ECC is equal to one blank value indicating a blank ECC state, and the second additional ECC bit indicates that the selected data set is blank, then enabling The use of the ECCs stored with the selection data set. A memory comprising: a plurality of data sets, comprising a plurality of addressable segments, and a plurality of error correction codes (ECCs) of the data sets in the memory; and a controller coupled to the data a set, comprising logic, when the new data is written in one of the addressable segments of the addressable segments of the selected data set in the memory, if the new data is stored and prior to the selection Data set If some of the addressable segments of the stylized data include at least a predetermined number of addressable segments, then one of the selected data sets is calculated and stored; and the stored complex number is indicated for the data sets, the indications indicating whether The use or use of the ECCs stored with the data sets is enabled or disabled. The memory of claim 7, wherein the controller comprises: a logic storing a plurality of extended ECCs, the extended ECCs including a field of the ECCs of the data sets, and from the ECC Deriving a field of a first additional ECC bit, the extended ECC having a first predetermined value, a second predetermined value, and a calculated value, the first predetermined value indicating a first state for The use of the data in the fields of the ECCs, the second predetermined value indicating a second state, wherein the extended ECCs originally have a calculated value equal to one of the first predetermined values, and the calculated values represent a third state comprising a plurality of calculated ECCs in the field of the ECCs, and a bit in the field of the first additional ECC bits derived from the calculated ECC a logic that uses one of the selected data sets to extend a calculated value of one of the ECCs, and if the new data is stored and the addressable segments of the data that were previously programmed in the selected data set include at least a predetermined number of addressable Segment, and the selection data set is already in the new data If the error condition that the addressable segment is stylized does not occur; a logic that sets the extended ECC to the first predetermined value, thereby Determining the use of the ECCs stored with the selected data set, if the selected data set is pre-programmed in the addressable segment of the new data; a logic, setting the extended ECC to the a second predetermined value, if the extended ECC is equal to the first predetermined value and the selected data set is not programmed in the addressable segment of the new data, the extended ECC includes a second additional ECC bit a field; and a logic that sets the second additional ECC bit to a value to indicate that the selected data set is stylized in at least one addressable segment. The memory of claim 7, wherein the controller comprises: a logic for reading an extended ECC including an ECC and a first additional ECC bit from a selected data set, wherein the An additional ECC bit is derived from the ECC by using a logic function; a logic for enabling use of the ECC stored with the selected data set, if the logical function of the ECC is equal to the An additional ECC bit, and the ECC is not equal to a first predetermined value, the first predetermined value indicating a first state to disable use of the ECCs; and a logic to set the ECC to the first predetermined a value, and then enabling use of the ECC having the selected data set, if the logic function of the ECC is not equal to the first additional ECC bit, and the ECC is equal to a second predetermined value, the second predetermined value is represented The ECC originally has a second state equal to one of the calculated values of the first predetermined value; a logic to read a second additional ECC bit, the second additional ECC bit indicating whether the selected data set is stylized in at least one addressable segment; and a logic to enable the selected data set The use of the ECCs stored, if the logic function of the ECC is not equal to the first additional ECC bit, the ECC is equal to one blank value indicating a blank ECC state, and the second additional ECC bit indicates Select the data set to be blank.