TWI521377B - Integrated circuit, code generating method, and data exchange method - Google Patents

Description

Integrated circuit, method for generating password, and method for data exchange [Cross-Reference to Related Applications]

This application is a continuation and claims priority to U.S. Patent Application Serial No. 14/335,957, filed on July 21, 2014. The entire disclosure of the above-identified patent application is hereby incorporated by reference.

The present invention relates to an integrated circuit, a method for generating a password, and a method for data exchange.

As the Internet has become popular since the middle of the last century, encryption and authentication technologies are needed to secure the network. Most of these technologies are designed by assuming that they are used in servers or PCs with powerful computing power. For example, antivirus software and random number generation software require powerful computing power to operate. On the other hand, the use of small devices has been increasing in recent years, and the small devices have weak computing power and can be connected to the network, such as SIM card, sensing. Devices, smart meters, smart cards, USB memory, and more. With the use of cloud computing, social networking, smart grids, machine-to-machine (M2M) networks, etc., a network of similarly small devices has created new application services. Because LSI chips are components of small devices, the number of chips used in the network must increase dramatically. Therefore, some new technologies need to be embedded in LSI chips to ensure the security of a network composed of LSI chips. Since each of the LSI chips has only weak computing power, it is expected that component level modules must be used for encryption and authentication techniques. It should also be noted that the cost of the security module in the wafer is also an important consideration.

In general, component level modules for security include a) circuitry for performing encryption and authentication operations, and b) circuitry for storing/maintaining confidential information necessary to run encryption and authentication. (key maintenance).

It should be noted that adding a second portion (key maintenance) circuit to the wafer increases the cost of the wafer. It is also worth noting that an attacker will likely attack key maintenance. An example of key maintenance is illustrated in FIG. (Physically-Unclonable Function (PUF))

As shown in FIG. 2, the key maintenance circuit has been expected in recent years to be replaced by a physical non-reproducible function (PUF) in which individual differences in the wafer are used to identify the wafer. For example, as shown in Figure 3, the module of the PUF will return the output (R) for the input (C). As shown in Figure 4, another wafer will return another output for the same input. One can use the difference in output between the wafers for the same input to identify the wafer. In other words, the PUF will create the ID if necessary and not It is necessary to store the ID in the memory.

(utilization of PUF)

(Authenticity) As shown in FIG. 4, as long as the output (R) from the wafer is different from any other wafer, this output can be regarded as the ID number of the wafer.

(Copy Protection) It is possible to create a general encryption key (key-A) from the output of the chip-A (R-A). It is also possible to create another general encryption key (key-B) from the output of the chip-B (R-B). As shown in FIG. 4, the key-B must be different from the key-A with respect to the same input (C). Once a program is encrypted with the key A, the program cannot be executed by any other LSI (LSI-B) because the key-B is different from the key-A.

(requirements for PUF)

a) (unpredictability) The combination of the input (C1) and the output (R1) is predicted from the other input-output combinations ((C2)-(R2), (C3)-(R3)...)). Impossible or very difficult. In Fig. 5, it is assumed that a combination of (C1) - (R1), (C2) - (R2) ... (Cn) - (Rn) is known. In this case, the combination of predictions (Cn+1)-(Rn+1) must be impossible or very difficult. b) (Ingenuity) As shown in Figure 4, any two wafers must return different return values (R1 and R2, where R1 ≠ R2) for the same input (C). c) (Reproducibility) In general, noise causes the output from the device to fluctuate around the average (R). As shown in Figure 6, the fluctuation (ΔR) must be less than the difference between any two outputs (for with , |ΔR|<|R1-Rm|).

(Advantages of PUF)

a) (Invisible Labels) The return value from the PUF can be treated as an invisible label that is randomly and independently attached to each LSI wafer without any additional design. As shown in Figure 7, it is beneficial for distinguishing whether it is authenticated. It should be noted that the return value from the PUF does not have to be stored in the memory, which means "not visible". b) (Copy Protection) An encryption key can be created from the backhaul value from the PUF. As shown in Figure 8, once a program is encrypted with a key created by a PUF in the wafer, the program cannot be executed using any other wafer as long as the PUF is functioning properly.

However, nothing in this document should be construed as an admission that the knowledge in the prior art of any part of the invention. In addition, citation or citation of any document in this application is not an admission that such document may be used as a prior art of the present invention or as a part of the ordinary knowledge in the art.

Accordingly, the present invention is directed to an integrated circuit and a method of generating a password that enables physical non-reproducible identification on a wafer.

According to an exemplary embodiment, an integrated circuit is provided. The integrated circuit includes at least one first input/output terminal, at least one current path connected to the first input/output terminal, is disposed on the at least one current path, and is configured to apply a plurality of control terminal voltages At least one control terminal on the at least one current path, and at least one second current input/output terminal connected to the current path. At least one current adjustment component is disposed on the at least one current path to adjust current. In some real In an embodiment, the at least one current adjustment component comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to a DeBloyd Length (DBL), and the length of the current path is longer than the The width of the current path. In other embodiments, the at least one current adjustment element comprises at least one grain boundary.

According to an exemplary embodiment, another integrated circuit is provided. The integrated circuit includes a plurality of semiconductor elements, a plurality of sense amplifiers, and a processing circuit. Each semiconductor component is used to represent a bit address in a mapping table and includes a first input/output terminal, a second input/output terminal, a current path, and a control terminal. At least one current adjustment component is disposed in the at least one current path to adjust the current. Each of the sense amplifiers is coupled to the second input/output terminal and is configured to sense current from the second input/output terminal and determine a threshold voltage of the respective semiconductor unit. The processing circuit is configured to classify each of the threshold voltages determined by the respective sense amplifiers into a first state and a second state, and mark each of the corresponding addresses in the mapping table The state of one of the threshold voltages. In some embodiments, the at least one current adjustment element comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL), and the length of the current path Longer than the width of the current path. In other embodiments, the at least one current adjustment component comprises at least one grain boundary.

According to an exemplary embodiment, a method of password generation is provided. The method of generating a password is applied to an integrated circuit having a plurality of semiconductor elements, each of which includes a first input/output terminal, a second input/output terminal, and a current path. The method includes: determining a first read voltage and a reference current; Sensing a current from the second input/output terminal and confirming a threshold voltage of the corresponding semiconductor component, wherein at least one current regulating component is disposed in the at least one current path to adjust the current; classifying each threshold voltage into a first state and a second state; and marking the address of each of the semiconductor elements in the corresponding mapping table according to the state of the threshold voltage. In some embodiments, the at least one current adjustment element comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL), and the length of the current path Longer than the width of the current path. In other embodiments, the at least one current adjustment component comprises at least one grain boundary.

According to an exemplary embodiment, the step of classifying each of the identified threshold voltages into the first state and the second state further comprises classifying the respective threshold voltages into a first state, a second state, and a third state.

According to an exemplary embodiment, a method of data exchange is provided. The method exchanges data between the first device and the second device. The second device has a plurality of semiconductor elements, each of which includes a first input/output terminal, a second input/output terminal, a current path, and a control terminal. The method includes: providing a first group of packets to the first device for transmission to a second device via a network, wherein the first group of the packets includes an order of reading voltages; and reacting by using the second device Generating a second group of the packets and transmitting a second group of the packets of the packet to the first device; comparing the first group of the packets with the identification management unit in the first device The second group of the packets and generating a comparison result; determining, based on the comparison result, whether the second device allows communication with the first device. Additionally, the packet is generated by using the second device to react to the first group of the packet The second group of steps includes: configuring each semiconductor component to indicate an address in a mapping table; determining a first read voltage and a reference current; sensing a current from the second input/output terminal and confirming the corresponding semiconductor a threshold voltage of the component, wherein at least one current adjustment component is disposed in the at least one current path to adjust the current; classifying each threshold voltage into a first state and a second state; and marking each semiconductor component according to a state of the threshold voltage The address corresponding to the mapping table. In some embodiments, the at least one current adjustment element comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL), and the length of the current path Longer than the width of the current path. In other embodiments, the at least one current adjustment component comprises at least one grain boundary.

In summary, the integrated circuit, the cryptographic generation method, and the data exchange method described in the embodiments of the present invention can produce a physical non-reproducible recognition effect on the wafer.

However, it is to be understood that the summary is not intended to be inclusive of It is understood that it includes significant improvements and modifications.

The above described features and advantages of the invention will be apparent from the following description.

610‧‧‧ first device

620‧‧‧second device

630‧‧‧Identification Management Unit

640‧‧‧ integrated circuit

650‧‧‧Network

700‧‧‧Integrated circuit

750‧‧‧Processing circuit

WL‧‧‧Common word line

SL‧‧‧Shared source line

S‧‧‧ source

D‧‧‧汲

L‧‧‧ length

Z‧‧‧ channel thickness

S700-S730‧‧‧Steps

1 illustrates a key maintenance module in the prior art without PUF An example.

Figure 2 illustrates a wafer with an embedded PUF.

Figure 3 illustrates the concept of a PUF.

4, 5, and 6 illustrate the originality, unpredictability, and resettability of the PUF, respectively.

Figure 7 illustrates the management of a wafer with a PUF.

Figure 8 illustrates the copy protection effect achieved by PUF.

FIG. 9 illustrates a fin transistor having a channel width W in the vicinity of DBL, in accordance with an exemplary embodiment.

Figure 10 illustrates the conduction state of the fin transistor of Figure 9 when negative ions are present in the source-channel interface, in accordance with an exemplary embodiment.

Figure 11 illustrates the structure of an integrated circuit according to a first embodiment of the present invention.

Figure 12 illustrates the relationship between the address data in an example of the present invention and the sensed threshold voltage Vt of the corresponding semiconductor unit, showing the threshold voltage Vt due to random dopant fluctuations. fluctuation.

Figure 13 illustrates addressing on a two-dimensional (2D) plane region in which address 1, address 2, ... and address 2N are arranged in a mapping table having a checkerboard pattern, according to an exemplary embodiment.

FIG. 14 illustrates a distribution of threshold voltage Vt values of a semiconductor unit sensed in the case of random doping of negative ions, according to an exemplary embodiment.

FIG. 15 illustrates a distribution of threshold voltages Vt values of semiconductor cells induced in the case of random doping of positive ions, according to an exemplary embodiment.

FIG. 16 illustrates an example of a black and white distribution on a checkerboard pattern representing a threshold voltage Vt distribution of a semiconductor unit, according to an exemplary embodiment.

Figure 17 illustrates an exemplary element structure having a common word line (WL) as a unique gate in accordance with a second embodiment of the present invention.

Figure 18 illustrates another exemplary element structure having a common WL that wraps fins to form a plurality of three-gate semiconductor cells in accordance with a third embodiment of the present invention.

19 illustrates the relationship between the read voltage in the threshold voltage Vt distribution and the lower threshold voltage Vt peak (W) and the higher threshold voltage Vt peak (BL), according to an exemplary embodiment.

Figure 20 illustrates the relationship between a fluctuating read voltage, a lower threshold voltage Vt peak (W), and a higher threshold voltage Vt peak (BL) in accordance with a fourth embodiment of the present invention.

FIG. 21 illustrates the cause of causing random-telegraph noise (RTN), according to an exemplary embodiment.

FIG. 22 illustrates an energy band diagram when electrons are captured by an interface trap, according to an exemplary embodiment.

23 illustrates a case where a semiconductor unit transitions from a peak value of W to a gap window between W and BL due to random telegraph noise (RTN), according to an exemplary embodiment.

24 illustrates a transition of a semiconductor cell from a spacer window between W and BL to a peak due to random telegraph noise (RTN), according to an exemplary embodiment. The case of value.

FIG. 25 illustrates a case where a semiconductor cell transitions from a peak of BL to a spacer window between W and BL due to random telegraph noise (RTN), according to an exemplary embodiment.

FIG. 26 illustrates a case where a semiconductor cell transitions from a spacing window between W and BL to a peak of BL due to random telegraph noise (RTN), according to an exemplary embodiment.

FIG. 27 illustrates a case where the threshold voltage Vt is changed from the voltage in W to the voltage in the interval window which is lower than the read voltage due to the RTN and is returned toward W, according to an exemplary embodiment.

FIG. 28 illustrates a case where the threshold voltage Vt is changed from a voltage in W to a voltage in a spacer window higher than a read voltage and is returned toward W, according to an exemplary embodiment.

FIG. 29 illustrates several cases in which the threshold voltage Vt changes from inside W to toward a spacer window, according to an exemplary embodiment.

FIG. 30 illustrates several cases in which the threshold voltage Vt changes from inside the spacer window to W, according to an exemplary embodiment.

FIG. 31 illustrates several cases in which the threshold voltage Vt changes from inside the BL toward the spacer window, according to an exemplary embodiment.

FIG. 32 illustrates several cases in which the threshold voltage Vt changes from inside the spacer window to BL, according to an exemplary embodiment.

Figure 33 illustrates a semiconductor unit transistor (bit) in accordance with one embodiment of the present invention. Meta-steps of the iterative induction.

Figure 34 illustrates a threshold voltage Vt distribution of a semiconductor unit after the semiconductor unit is subjected to random doping of negative ions and positive ions in accordance with a fifth embodiment of the present invention.

35, 36, 37, and 38 illustrate a case where positive ions or negative ions are away from the source edge on the surface of the substrate, according to an exemplary embodiment.

39 and 40 illustrate two cases in which positive ions and negative ions also cancel each other, even when positive ions and negative ions are present in the source-channel interface, according to an exemplary embodiment.

Figure 41 illustrates an RGB checkerboard pattern showing a 2D map of threshold voltage Vt distributions, where R, G, and B represent different threshold voltages Vt as shown in Figure 36, in accordance with another embodiment of the present invention. range.

Figure 42 illustrates the relationship between the threshold voltages Vt distribution peaks R, G, and B and the two read voltages (1) and (2) according to the sixth embodiment of the present invention.

43 and 44 illustrate a method for removing random telegraph noise (RTN) according to a sixth embodiment of the present invention.

Figure 45 is a view schematically showing the structure of a nanowire FET type semiconductor unit useful in the present invention and the same drain current according to an eighth embodiment of the present invention.

Figure 46 illustrates the conduction state of a nanowire FET type semiconductor cell when negative ions are present in the source-channel interface, according to an exemplary embodiment.

Figure 47 illustrates a bird's eye view of a nanowire FET type semiconductor unit, in accordance with an exemplary embodiment.

Figure 48 illustrates a form of a nanowire FET for forming a nanowire according to an exemplary embodiment. A bird's eye view of a nanowire array of semiconductor cell arrays.

Figure 49 illustrates a bird's eye view of a nanowire FET type semiconductor cell array, in accordance with an exemplary embodiment.

FIG. 50 illustrates a case where all gates of a nanowire FET type semiconductor unit are connected to a sheet type common word line (WL), according to an exemplary embodiment.

FIG. 51 illustrates a case where the gate of the nanowire FET type semiconductor unit is replaced by a sheet type common word line (WL), according to an exemplary embodiment.

Figure 52 illustrates a bird's eye view of a three-gate nanowire unit semiconductor unit in accordance with a ninth embodiment of the present invention.

Figure 53 illustrates an array of the three-gate nanowire semiconductor unit of Figure 52.

FIG. 54 illustrates a case where all gates of a three-gate nanowire semiconductor unit are connected to a sheet type common word line (WL), according to an exemplary embodiment.

FIG. 55 illustrates a case where the gate of the three-gate nanowire semiconductor unit is replaced by a sheet type common word line (WL), according to an exemplary embodiment.

Figure 56 illustrates a bird's eye view of a wraparound gate nanowire semiconductor unit, in accordance with an exemplary embodiment.

Figure 57 illustrates an array of the wraparound gate nanowire semiconductor cells of Figure 56.

Figure 58 illustrates a bird's eye view of a post-type semiconductor unit, in accordance with an exemplary embodiment.

Figure 59 illustrates an array of pillar-type semiconductor cells as shown in Figure 58 in accordance with an exemplary embodiment.

Figure 60 illustrates a cylindrical semi-conductor that does not include a gate, in accordance with an exemplary embodiment. The structure of the body cell array.

Figure 61 is a schematic view of a grain boundary of a channel.

Figure 62 illustrates the distribution of sense threshold voltage Vt values for a transistor element having grain boundaries and a transistor element having no grain boundaries.

Figure 63 illustrates a fin transistor without a grain boundary.

Figure 64 illustrates the conductive state of a fin transistor having a grain boundary at the source terminal of the channel.

Figure 65 illustrates the conductive state of a fin transistor having a grain boundary located at the center of the channel.

Figure 66 illustrates the conductive state of a fin transistor having a grain boundary at the 汲 extreme of the channel.

Figure 67 is a block diagram of a data exchange system in accordance with an exemplary embodiment of the present invention.

Figure 68 is a flow diagram of a method of data exchange in accordance with an exemplary embodiment of the present invention.

Specific embodiments and examples of the invention are now described with reference to the drawings. In the drawings and the description, the same reference numerals are used to the

(Random-Dopant Fluctuation (RDF) in the following disclosure illustrates the use of random doping waves for physical non-reproducible functions Action (RDF). It must be noted that in the following exemplary embodiments, a field effect transistor is used as an example to illustrate the concept of the present invention, and thus the first input/output terminal may represent the source and the second input/output terminal may represent 汲The poles, current paths may represent the channels, and the control terminals may represent the gates; however, the foregoing embodiments are merely illustrative of the embodiments and are not intended to limit the scope of the invention. In fact, the invention can also be implemented on several other CMOS compatible semiconductor devices, such as bipolar junction transistors (BJTs) and the like.

In order to make the variation of the threshold voltage Vt by means of ions more significant than the prior art, the channel width W can be reduced, and the channel length L can be reduced. The typical length of the channel width W is comparable to the DeBloyd length (DBL), which is typically about 9 nm in the tantalum material, while the typical length of the channel length L is much larger than the DBL, for example, 100nm.

Several cases where the channel width W is approximately DBL will be discussed below. As illustrated in Figure 9, the electron flow flows from the source through the channel without ions to the drain.

As shown in Figure 10, if negative ions are present in the source-channel interface, the electron flow will be reflected by the peak potential of the negative ions without current flowing because the electrons cannot circumvent the ions due to the narrow channel (Si).

As described above, the threshold voltage (Vt) is significantly affected only when the ions are located on the interface between the source and the drain on the surface of the substrate. This feature becomes remarkable by the semiconductor unit structure proposed in the present invention, in which the channel length is larger than DBL and the channel width is about DBL.

In an exemplary embodiment of the invention, the basic charge is for potential distribution The effect is approximately 100 mV and the typical electric field across the channel layer is approximately 0.1 MV/cm, indicating that the effect of the basic charge can disappear from the interface of 10 nm. This happens to be DBL. In addition, the grain boundaries can store a plurality of ions, and thus the influence of grain boundaries may disappear below several 10 nm. Therefore, when the position of the ions of the channel is closer to the drain than the source, the ion affects the distribution of the threshold voltage Vt more; more specifically, the ion located in the channel is about 10 nm from the source/channel interface. Inside. However, it should be noted that the present invention is not limited to the above examples.

<First Embodiment>

Figure 11 illustrates an integrated circuit in accordance with a first exemplary embodiment of the present invention. In FIG. 11, integrated circuit 700 includes a plurality of field effect transistors and a plurality of sense amplifiers, wherein each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel, and a gate. pole. In some exemplary embodiments, to minimize source contact as much as possible, one source is shared by two semiconductor cells and all sources are connected to a common source line (SL), as shown in FIG. The two drains (D) of the tandem semiconductor unit (sources shared by the plurality of semiconductor units) are independently connected to a sense amplifier (S/A). In this example, each sense amplifier S/A is assigned to address data (address 1, address 2, address 3... and address 2N). The number of semiconductor cells is 2N and the number of stacked semiconductor cells is N. These sense amplifiers S/A sense the threshold voltage of each semiconductor unit, that is, the threshold voltages Vt(1), Vt(2), Vt(3), ..., and Vt(2N). All gates are connected to a common word line (WL). In another exemplary embodiment, integrated circuit 700 can also include processing circuit 750 that is configured to be used by a corresponding sense amplifier S/A Each of the determined threshold voltages Vt(1), Vt(2), Vt(3), ..., and Vt(2N) is classified into a first state and a second state, and is in a mapping table (for example, FIG. 13 or The state of each of the threshold voltages Vt(1), Vt(2), Vt(3), ..., and Vt(2N) is marked on the corresponding address in the map of the checkerboard pattern shown in FIG. However, it should be noted that the processing circuit 750 is not limited to classifying the threshold voltage into two states, and the processing circuit 750 can also classify the threshold voltage into three states according to different applications.

Figure 12 shows the address data on the left and the sensed threshold voltages of the respective semiconductor cells on the right. In this exemplary embodiment, it is assumed to be an n-type MOSFET (p-type channel) whose threshold voltage fluctuates around 0.5V to 0.8V. This difference is due to negative ions that are present around the edge of the source on the surface of the germanium substrate. It is generally considered that 0.5 V corresponds to the case where negative ions are not present around the source edge on the surface of the germanium substrate, and 0.8 V corresponds to the case where negative ions exist around the source edge on the surface of the germanium substrate.

Figure 13 illustrates addressing (i.e., mapping table) on a two-dimensional planar area in which address 1, address 2, and address 2N are mapped in a checkerboard pattern.

Figure 14 illustrates the distribution of the sensed threshold voltage. The peak on the right corresponds to the case where negative ions are present around the edge of the source on the surface of the germanium substrate. The tail with a higher threshold voltage Vt is derived from a second or more negative ions present around the edge of the source on the surface of the tantalum substrate. Other peaks correspond to the case where negative ions are not present around the edge of the source on the surface of the germanium substrate. The semiconductor cells belonging to the peak on the right are shown as black on the board (BL), while the other semiconductor units are shown as white on the board (W).

Figure 16 illustrates an example of black and white distribution on a checkerboard. The black and white arrangement on the checkerboard pattern (ie, the mapping table) is determined by the sensed distribution of threshold voltages. Since the position of the negative ions in the device fluctuates between the semiconductor units, the checkerboard pattern fluctuates with respect to random doping fluctuations.

In this embodiment, the negative ions may be replaced by positive ions. As illustrated in Fig. 15, even in this case, the peak on the right side is black (BL) and the other peak is white (W). The following embodiments are substantially unchanged as long as the black and white checkerboard pattern (described in Figure 16) is formed in a similar manner by random doping fluctuations (RDF).

It is also possible to replace an n-type FET (p channel) with a p-type FET (n channel). Here "FET" means "field effect transistor". As illustrated in Fig. 16, even in this case, the peak on the right side is black (BL) and the other peak is white (W). The following embodiments are substantially unchanged as long as the black and white checkerboard pattern (Fig. 16) is made in a similar manner by random doping fluctuations (RDF).

<Second Embodiment: Element Structure>

Figure 17 is a diagram showing the structure of an element in accordance with a second exemplary embodiment of the present invention. Connected to a plurality of finned FETs on a common word line (WL), the word lines are in the shape of a plate, and each fin FET can satisfy the channel width (W) (that is, the Debrois length (DBL) A condition of about 10 nm, and the channel length (L) is much larger than 10 nm. It should be noted that the word lines can be independent in a typical fin FET system. There is a gate insulating layer between the word line and the channel.

<Third Embodiment: Three Gate Type>

Figure 18 is another element structure in accordance with a third exemplary embodiment of the present invention. presence A plurality of fin FETs connected to a common gate. WL wraps the fins as shown to make the element structure a three-gate. Each fin FET can satisfy the channel width (W) (that is, the Debroy length (DBL)) condition around 10 nm, and the channel length (L) is much larger than 10 nm. The gate insulating layer also surrounds the fin layer and is surrounded by a word line (WL). It should be noted that the word lines can be independent in a typical fin FET system.

Each of the sense amplifiers S/A in Fig. 11 reads the threshold voltage (Vt) of the corresponding semiconductor unit as shown in Fig. 11. 2N semiconductor units and 2N sense amplifiers S/A are grouped by a common word line (WL), as shown in FIGS. 12, 17, and 18, and are also grouped by a common source line (SL), as shown in FIG. Shown in 11. The sensed threshold voltages of the semiconductor cells in the group are labeled Vt(1), Vt(2), ..., Vt(2N), where each Vt(n) corresponds to the address n, as in FIG. Shown where n is from 1 to 2N. This correspondence is shown in Figure 12, and the distribution of the threshold voltage is divided into two peaks, that is, a higher threshold voltage Vt peak (black, BL) and a lower threshold voltage Vt peak (white, W), as shown in the figure. Shown in 14. If the addresses shown in FIGS. 11 and 12 are mapped over the 2D area, as shown in FIG. 13, a white black checkerboard pattern with respect to random doping fluctuations is obtained, as shown in FIG.

In order to read the threshold voltage, as shown in FIGS. 11, 17, and 18, the read voltage is applied by the common word line (WL). This read voltage may be higher than the higher tail of the lower threshold voltage Vt peak (W) and lower than the lower tail of the higher threshold voltage Vt peak (BL), as shown in FIG.

Due to the fluctuation of the word line offset resistance, it may be necessary to pay attention to the wave of the read voltage. Move as shown in Figure 20. However, in an exemplary embodiment of the invention, the word lines are common word lines (WL) as shown in FIGS. 11, 17, and 18. And the offset resistance is very small.

A more important inductive subject is random telegraph noise (RTN) as described below, which is schematically illustrated in FIG. If there is an interface shallow trap, the electrons will be captured by these traps or emitted from these traps. This trap-detrap phenomenon occurs quickly and randomly, and thus the sensed threshold voltage is fluctuating. In this exemplary embodiment of the invention, the amplitude of the fluctuation is detectable (about 200 mV) but much less than the threshold voltage shift caused by the ions present on the source side.

In Figure 22, the electrons are captured by the interface trap. It should be noted that this trap is close to the interface but still in the oxide. The accumulation of peak barrier around the source edge is reduced compared to the effect of ions on the source edge inside the channel. Therefore, the effect of this trap on the current transfer through the channel is less than the effect of the ion pair on the source side inside the channel as described in FIG. 10 by the current transfer of the channel.

As illustrated in FIG. 23, the semiconductor unit may transition from the peak value of W to the interval window between the peak value W and the peak value BL, but because the magnitude of the threshold voltage Vt shift caused by random telegraph noise (RTN) is small. It is not possible to transfer directly from the W peak to the BL peak.

As illustrated in FIG. 24, the random telegraph noise (RTN) semiconductor unit may transition from the interval window between the W peak to the BL peak to the peak W. This can be considered as the reverse process of Figure 23.

As illustrated in FIG. 25, the semiconductor unit may transition from the peak BL to the interval window between the peak W and the peak BL, but the amplitude of the threshold voltage Vt caused by random telegraph noise (RTN) is small and cannot be Transfer directly from peak BL to peak W.

As illustrated in FIG. 26, the random telegraph noise (RTN) semiconductor unit may transition from the interval window between the peak W and the peak BL to the peak BL. This can be considered as the reverse process of Figure 25.

Another important feature of the RTN is that the threshold voltage Vt changes over and over again, as shown in Figures 27 and 28. Fig. 27 illustrates a case where the threshold voltage Vt is changed from the voltage inside the peak W to the voltage in the interval window lower than the read voltage and is returned toward the peak W. It should be noted that the magnitude of the return value is generally different from the magnitude of the change of the first threshold voltage Vt. FIG. 28 illustrates a case where the threshold voltage Vt is changed from the voltage inside the peak W to a voltage higher than the voltage in the interval window of the read voltage and is returned toward the peak W. It should be noted that the magnitude of the return value is generally different from the magnitude of the change of the first threshold voltage Vt.

Further, Fig. 29 illustrates several cases in which the threshold voltage Vt changes from inside the peak W toward the interval window. The magnitude of the threshold voltage Vt offset is generally different from each other. Fig. 30 illustrates several cases in which the threshold voltage Vt changes from inside the spacer window toward the peak value W. Fig. 31 illustrates several cases in which the threshold voltage Vt changes from inside the peak BL toward the spacer window. Fig. 32 illustrates several cases in which the threshold voltage Vt changes from inside the spacer window toward the peak BL. In the above figures (Figs. 29 to 32), the magnitudes of the threshold voltages Vt are generally different from each other and the threshold voltage Vt caused by the RTN is shifted more than the lower thin layer by the common word line (WL). Read bias caused by resistance fluctuation.

Therefore, fluctuations in the threshold voltage Vt caused by random telegraph noise are alleviated. In the present invention, the basic idea for removing the effects of random telegraph noise (RTN) is by repeatedly reading the threshold voltage. Since the threshold voltage Vt offset due to the RTN changes in each induction, as shown in FIGS. 27 and 28, the reverse sensing can remove the influence of the RTN. This step of repetitive sensing can be performed in all of the semiconductor cell transistors.

The iterative sensing step of the semiconductor unit transistor (bit) is illustrated in FIG. First, the semiconductor unit transistor to be sensed is selected. Subsequently, the number of successively induced iterations (N) is given, where N typically exceeds 10. The read voltage and reference current (Ir) are also given. The read voltage may be higher than the right tail value of the peak W and lower than the left tail value of the peak BL, as shown in FIGS. 27 to 32. The reference current can generally be determined by considering the technology node (ie, the channel length (L)). The iteration counts (i, j, and k) are set to zero under initial conditions. Next, the gate current (Id) of the illustrated semiconductor cell transistor (bit) is sensed, and the first iteration count (i) is increased by one, that is, i=i+1. Subsequently, the drain current (Id) is compared with the reference current (Ir). If the absolute value of Id is greater than the absolute value of Ir, the second iteration count (j) is increased by one. Otherwise, the third iteration count (k) is increased by one. Subsequently, the first iteration count (i) is compared to the number (N) of successively induced iterations. If i < N, the step returns to the induction of the drain current and the first iteration count (i) is incremented by one again. Otherwise, the second iteration count (j) is compared to the third iteration count (k). If j>k, the threshold voltage of the sensed semiconductor unit belongs to FIG. 14, FIG. 19, FIG. 20, and FIG. Go to the peak W (white) shown in FIG. Otherwise, the threshold voltage of the sensed semiconductor unit belongs to the peaks BL (black) shown in FIGS. 14, 19, 20, and 23 to 32. Thereafter, another semiconductor unit transistor is selected, and then the above steps after the first step of selecting the semiconductor unit transistor to be sensed are repeated until all of the semiconductor unit transistors (bits) are performed according to the above steps Iterations are sensed.

<Fifth Embodiment: Extension of RGB Board>

As described above, the positive ions at the source edge can also change the threshold voltage (Vt), as illustrated in Figure 15, while the direction in which the threshold voltage Vt shifts becomes a valve caused by negative ions at the source edge. The value voltage Vt is offset by the opposite. In the disclosure below, the higher threshold voltage Vt peak in the threshold voltage Vt distribution (due to negative ions at the source edge) is redesignated as blue (B), as described in the previous embodiment. The peak value of the high threshold voltage Vt is the peak value BL (black). The lower threshold voltage Vt peak in the threshold voltage Vt distribution (due to positive ions at the source edge) is redesignated as red (R), and in the previous embodiment is the peak W (white) A peak is redesignated as green (G), as shown in Figure 34. The peak R has a tail on the left due to 2 or more positive ions on the source side. Peak B has a tail on the right due to 2 or more negative ions on the source side. The peak G is formed by other cases, including the case where the positive or negative ions as shown in FIGS. 35, 36, 37, and 38 are away from the source edge on the surface of the substrate, and having the RTN as shown in FIG. The case, and if positive ions and negative ions are present on the source edge on the surface of the substrate as shown in FIGS. 39 and 40, they will cancel each other. Using the same mapping method as illustrated in FIGS. 12 and 13, an RGB checkerboard pattern as shown in FIG. 41 is obtained. The RGB checkerboard pattern has more fluctuations on the checkerboard pattern than the white black checkerboard pattern. This means that an RGB checkerboard pattern may be preferred even when another doping process is added.

<Sixth Embodiment: Measurement of RGB type random telegraph noise>

As illustrated in Figure 42, to distinguish between R and G, a first read voltage (1) is applied. It should be noted that the read voltage (1) is in the interval window between the peak R and the peak G. As illustrated in Figure 42, to distinguish between G and B, a second read voltage (2) is applied. It should be noted that the second read voltage (2) is in the interval window between the peak G and the peak B. If the "R" and "G" are respectively returned by the first sensing of the first read voltage (1) and the second sensing of the second read voltage (2), the semiconductor unit is marked as "R" ". If the "G" and "G" are respectively returned by the first sensing of the first read voltage (1) and the second sensing of the second read voltage (2), the semiconductor unit is marked as "G" ". If the "G" and "B" are respectively returned by the first sensing of the first read voltage (1) and the second sensing of the second read voltage (2), the semiconductor unit is marked as "B" ".

The steps of distinguishing between R and G are illustrated in FIG. First, the semiconductor unit transistor (bit) to be sensed is selected. Subsequently, the number of successively induced iterations (N) is given. The first read voltage (1) and the reference current (Ir) are also given. The first read voltage (1) may be higher than the right tail of the peak R and lower than the left tail of the peak G, as illustrated in FIG. The reference current is typically determined by the technology node (ie, the channel length (L)). The iteration counts (i, j, and k) are set to zero under initial conditions. Then, the drain current (Id) is sensed, and the first iteration count (i) is increased by one, also That is i=i+1. Subsequently, the drain current (Id) is compared with the reference current (Ir). If the absolute value of Id is greater than the absolute value of Ir, the second iteration count (j) is incremented by one. Otherwise, the third iteration count (k) is increased by one. Subsequently, the first iteration count (i) is compared to N. If i < N, the step returns to the step of sensing the drain current, and the first iteration count (i) is incremented by one again. Otherwise, the second iteration count (j) is compared to the third iteration count (k). If j>k, the threshold voltage of the sensed semiconductor cell belongs to the red peak (R), as shown in FIGS. 38 and 42. Otherwise, the threshold voltage of the sensed semiconductor unit belongs to the green peak (G) shown in FIGS. 38 and 42.

Subsequent steps for distinguishing between G and B are illustrated in FIG. First, the semiconductor unit transistor (bit) to be sensed is selected. The read voltage and the reference current (Ir) are also given given the number (N) of successively induced iterations. The second read voltage (2) may be higher than the right tail of the peak G and lower than the left tail of the peak B, as illustrated in FIG. The iteration counts (i, j, and k) are set to zero under initial conditions. Next, a drain current (Id) is sensed, and the first iteration count (i) is increased by one, that is, i=i+1. The drain current (Id) is then compared to the reference current (Ir). If the absolute value of Id is greater than the absolute value of Ir, the second iteration count (j) is incremented by one. Otherwise, the third iteration count (k) is increased by one. Subsequently, the first iteration count (i) is compared to N. If i < N, the step returns to the step of sensing the drain current, and the first iteration count (i) is incremented by one again. Otherwise, the second iteration count (j) is compared to the third iteration count (k). If j>k, the threshold voltage of the sensed semiconductor cell belongs to the green peak (G), as shown in FIGS. 38 and 42. Otherwise, the threshold voltage of the sensed semiconductor unit belongs to the blue peak (B) shown in FIGS. 38 and 42.

According to the foregoing steps, if the "R" and the "G" are respectively returned by the first sensing of the first read voltage (1) and the second sensing of the second read voltage (2), the semiconductor unit is Marked as "R". If the "G" and "G" are respectively returned by the first sensing of the first read voltage (1) and the second sensing of the second read voltage (2), the semiconductor unit is marked as "G" ". If the "G" and "B" are respectively returned by the first sensing of the first read voltage (1) and the second sensing of the second read voltage (2), the semiconductor unit is marked as "B" ". Similarly, it can be inferred that if R→G, then return R. If G→G, G is returned. If G→B, return B.

Thereafter, another semiconductor unit transistor is selected, and then the above steps after the first step of selecting the unit to be sensed are repeated until all of the semiconductor unit transistors (bits) are subjected to iterative sensing according to the above steps. So far, as shown in FIGS. 43 and 44.

<Seventh Embodiment: Finned FET Semiconductor Unit>

In the above embodiment, the fin FET type semiconductor unit is used to make the channel length equivalent to the Debrois length (DBL), although other embodiments of the present invention are not limited thereto.

<Eighth Embodiment: Nanowire Semiconductor Unit>

Next, the use of the nanowire FET type semiconductor unit in the semiconductor device system of the exemplary embodiment of the present invention will be described hereinafter, as illustrated in FIGS. 45 and 46. The cross-sectional view in the XY plane is the same as in Figures 9 and 10, where the channel width (W) is comparable to the DeBloyd length (DBL).

Figure 45 illustrates the case when no ions are present in the channel between the source (S) and the drain (D). The channel length is greater than DBL, and the channel width (W) and channel thickness (Z) are comparable to DBL.

When a negative ion is present on the source edge in the channel, as shown in FIG. 46, the electron flow is reflected by the ion because there is no bypass, which is similar to the description of FIG.

Since the ions cannot exist deep in the vertical direction due to the fine nanowires, the influence of ions at the source end of the channel is more frequent.

Similarly, it is possible to group multiple nanowires together, each nanowire containing a source (S), a drain (D), and a channel between the source and the drain, as in Figure 48. Explained. It should be noted that the channel width (W) and the channel thickness (Z) are comparable to the Debrois length (DBL), while the channel length (L) is much longer than the DeBroy length (DBL).

Similarly, gates can be attached to these nanowires as illustrated in FIG. The unit semiconductor unit transistor is illustrated in FIG. In order to configure the wiring network shown in Figure 11, all gates should be shared. There may be a gate insulating layer between the gate and the channel. This is used as an element in the structure of Figs. 50 and 51. In Fig. 50, a lamellae common word line (WL) is connected to all of the gates. In Fig. 51, all the gates are replaced by a lamellae common word line (WL).

<Ninth Embodiment: Three-gate nanowire semiconductor unit>

The unit semiconductor unit transistor of the three-gate nanowire semiconductor unit is illustrated in FIG. The gate insulating layer covering the nanowire is covered by the gate. Figure 53 illustrates an array of triple gate nanowire semiconductor cells. In order to make a wiring network that may be as illustrated in FIG. Road, all gates should be shared. This is achieved in the structure illustrated in Figures 54 and 55. In Fig. 54, the lamellae common word line (WL) is connected to all the gates. In Fig. 55, all the gates are replaced by lamellae common word lines (WL). Further, as shown in Fig. 57, it is possible to cover other planes of the semiconductor unit with another sheet-like conductor. Most preferably, the sheet-like conductor referred to herein is a film of polycrystalline germanium. The unit semiconductor unit transistor is illustrated in FIG. The gate insulating layer surrounding the nanowire is surrounded by a gate.

It should be noted that the fabrication process of semiconductor cells similar to these is applicable to three-dimensional (3D) integration of a common word line having a nanowire channel and a wire-all-around. Therefore, device level wafer identification can also be proposed in a manner compatible with 3D LSI.

<Tenth Embodiment: Column Type Semiconductor Unit>

As illustrated in Figure 58, the above-described nanowire semiconductor unit can be replaced by a cylindrical semiconductor unit. The pillar is surrounded by a gate insulating layer, which is further surrounded by a gate. A corresponding array of semiconductor cells is illustrated in FIG. It should be noted that there is a common word line (WL) which forms a gate structure of each of the semiconductor cells (pillars). Figure 60 illustrates a structure of this exemplary embodiment that does not include a common word line (WL). The diameter of the column should be comparable to DBL. The source is extremely substrate, all the pillars are terminated at the substrate, and thus the source level is common to all semiconductor cells (pillars). The other end of each column is the drain of the semiconductor unit. There is a channel between the source and the drain in each of the columns, and in addition the channel length should be greater than DBL. A manufacturing process of a semiconductor unit similar to this is applicable to a stand having a column type channel and a sheet-like common word line Body (3D) integration. Therefore, component level wafer identification can also be proposed in a manner compatible with the three-dimensional LSI.

Most preferably, the channel length mentioned above is sufficiently long to stabilize the drain current when no ions are present on the source edge in the channel. In general, the channel length is more than three times the DBL; that is, 30 nm.

<Eleventh Embodiment: Grain Boundary>

Figure 61 is a schematic view of a grain boundary of a channel. The channel illustrated in FIG. 61 can be, for example, fabricated in the integrated circuit shown in FIG. 11, and the channel can be made of polysilicon. The polysilicon in the channel can be composed of the grains and grain boundaries shown in Fig. 61, and the grains can be formed in a direction perpendicular to the substrate surface during process heating. The size of the grains (the width Wgr of the grains) is therefore sensitive to temperature and the heating process. The average grain width is generally, for example, from several tens of nanometers to several hundred nanometers. On the other hand, the width Wgb of the grain boundary is generally several nanometers.

Figure 62 illustrates the distribution of sense threshold voltage Vt values for a transistor element having grain boundaries and a transistor element having no grain boundaries. As shown in Fig. 62, the distribution of the sense threshold voltage Vt can be divided into two peaks, which are caused by positive ions isolated at the grain boundary, and the peak on the right is sensitive to the dispersion of the gate width and the dispersion of the gate length. Sex, word line resistance dispersion, bit line resistance dispersion, and so on. These dispersities are not only seen on the right side of the peak, but also on the left peak. Since the position and number of grain boundaries can be probabilistic, the threshold voltage of the left peak is dispersed. For example, the number of grains can be described by a Poisson distribution. Thereafter, in the description of the embodiment, the source and the drain are p-type regions and the conductive carrier is a hole. However, the invention is not limited to this example.

It should be noted that the threshold voltage Vt is lowered by the positive ions at the source end of the channel, partially reduced by the positive ions located at the center of the channel, and slightly reduced by the positive ions located at the 汲 extreme. Figure 63 illustrates a fin transistor without a grain boundary, Figure 64 illustrates the conductive state of a fin transistor having a grain boundary at the source terminal of the channel, and Figure 65 illustrates a fin transistor having a grain boundary at the center of the channel The conductive state, and Figure 66 illustrates the conductive state of the fin transistor having a grain boundary at the 汲 extreme of the channel. The channel between the source (S) and the drain (D) may be implemented in a nanowire structure or a pillar structure of the semiconductor unit, wherein the channel has a length L and a thickness Z.

In an exemplary embodiment of the invention, the effect of the basic charge on the potential distribution is about 100 mV, and the typical electric field across the channel layer is about 0.1 MV/cm, which means that the effect of the basic charge can disappear from the interface of 10 nm. . This happens to be DBL. In addition, the grain boundaries can store a plurality of ions, and thus the influence of grain boundaries may disappear below several 10 nm. Therefore, when the position of the grain boundary in the channel is closer to the source than the drain, the grain boundary affects the distribution of the threshold voltage Vt. However, it should be noted that the present invention is not limited to the above examples.

In Fig. 63, the current without holes is reflected by the absence of grain boundaries in the transistor. When a grain boundary exists at the source terminal, as shown in FIG. 64, the hole flow is reflected at the source terminal of the channel due to a segregated positive charge at the grain boundary of the source terminal. When a grain boundary exists at the center of the channel, as shown in Fig. 65, the hole flow is partially reflected by the positive charge deposited at the grain boundary. Further, when the grain boundary exists at the 汲 extreme of the channel, as shown in Fig. 66, the hole flow is slightly reflected by the positive charge deposited at the grain boundary. should It is more noted that the number of grain boundaries is not limited to the examples described. In addition to the channel having no grain boundaries or having a grain boundary, as shown in Figures 63-66, more than one grain boundary may be present in the channel.

In some embodiments, the grain width Wgr shown in FIG. 61 varies along a vertical axis of the generation channel perpendicular to the surface of the substrate. Therefore, the thickness of the channel should be adjusted to control the average grain width to be more suitable in the channel layer. In some embodiments, the length L of the channel is between the average grain width and the triple average grain width. Furthermore, the thickness of the channel layer can be less than the average grain width of the channel. In addition, in some embodiments, the channel is part of a nanowire structure and the diameter of the nanowire can be less than the average grain width of the channel. On the other hand, when the channel is part of the columnar structure, the diameter of the columnar structure may be smaller than the average grain width of the channel.

<Twelfth Embodiment: Data Exchange Method>

Figure 67 is a block diagram of a data exchange system in accordance with an exemplary embodiment of the present invention. Figure 68 is a flow diagram of a method of data exchange in accordance with an exemplary embodiment of the present invention. Referring to FIG. 67, the data exchange system includes a first device 610, a second device 620, and a network 650. The first device 610 can include an identification management unit 630 and the second device includes an integrated circuit 640. Further, the integrated circuit 640 can be, for example, the integrated circuit 700 shown in FIG. Alternatively, the first device 610 can be, for example, a data center that determines whether the communication session with the second device 610 is secure. It should be noted that the number of the first device 610, that is, the second device 620 is not limited to that shown in FIG. Referring to Figures 67 and 68, the system shown in Figure 67 can be used to perform a data exchange method between the first device 610 and the second device 620. In step S700, the first A device 610 provides a first set P1 of packets for transmission to the second device 620 via the network 650. The first group of packets may include the order in which the voltages are read, such as the gate voltage. It should be emphasized that the network 650 can be any wired or wireless network that is capable of delivering data packets and is suitable. In step S710, the integrated circuit 640 of the second device 620 reacts with the first group of packets to generate a second group P2 of packets. The method of generating the second set P2 of packets may be, for example, the method shown in FIG. 33 and FIGS. 43-44. The second set P2 of packets is then passed to the first device 610. In an embodiment, the first device 610 can send the sequence of the gate voltages in the first group P1 of the packets, and the second device 620 can output a plurality of gates corresponding to the gates in the second group P2 of the packets. Voltage mapping table. In other words, the second device 620 can generate a mapping table based on a gate voltage sent by the first device 610 using the cryptographic generation method described above. The first group P1 of the packet and the second group P2 of the packet may be divided into a plurality of packets, but the invention is not limited thereto. In step S720, the identification management unit 630 in the first device 610 compares the first group P1 of packets with the second group P2 of packets and generates a comparison result. In step S730, the first device 610 then determines, based on the comparison result, whether the second device 620 allows communication with the first device 610. In other words, different gate voltages cause different channel currents in the second device 620, and different second devices 620 have different channel conditions, such as different current adjustment components in the channel are disposed at different locations, and thus The first device 610 can perform authentication by recognizing the same feature between the mapping tables by the second group P2 of packets. It should be noted that the two packets (the first group P1 of the packet and the second group P2 of the packet) are independent. Moreover, the signal from the second device 620 does not pass any algorithms because it is the physics of the CMOS PUF. fluctuation. Therefore, as long as a large number of packets enter and leave the first device 610 through the network, it is difficult for the haker to detect the relationship between the first group P1 of the packet and the second group P2 of the packet.

The invention is disclosed by the preferred embodiments, but the invention is not limited to the preferred embodiments. It will be apparent to those skilled in the art that modifications and innovations may be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be defined by the scope of the above patent application.

700‧‧‧Integrated circuit

750‧‧‧Processing circuit

WL‧‧‧Common word line

SL‧‧‧Shared source line

Claims (45)

An integrated circuit comprising: at least one first input/output terminal; at least one current path, the at least one current path being connected to the at least one first input/output terminal; at least one control terminal, the control terminal Provided above the at least one current path, configured to apply a plurality of control terminal voltages on the at least one current path; and at least one second input/output terminal, the at least one second input/output terminal Connected to the at least one current path, wherein at least one current adjustment component is disposed on the at least one current path to adjust current. The integrated circuit of claim 1, wherein the at least one current adjustment element comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL) In one case, the length of the current path is longer than the width of the current path. The integrated circuit of claim 1, wherein the at least one current adjustment component comprises at least one grain boundary. The integrated circuit of claim 3, wherein the length of the current path is between an average grain width of the current path and three times an average grain width of the current path. The integrated circuit of claim 3, wherein the current path The thickness is less than the average grain width of the current path. The integrated circuit of claim 3, wherein the grain boundary is located adjacent to the at least one first input/output terminal and the at least one second input/output terminal. The integrated circuit of claim 1, further comprising: at least one sense amplifier coupled to the at least one second input/output terminal, configured to sense from the at least one a current at the input/output terminal, and determining a threshold voltage based on one of the control terminal voltages; and a processing circuit configured to determine each of the respective sense amplifiers The threshold voltage is classified into a first state and a second state, and the state of each threshold voltage is marked on an address in a mapping table. An integrated circuit comprising: a plurality of semiconductor units, each semiconductor unit configured to represent an address in a mapping table and including a first input/output terminal, a second input/output terminal, a current path, and a control terminal, wherein at least one current adjustment component is disposed in the at least one current path to adjust current; a plurality of sense amplifiers, each sense amplifier being coupled to the second input/output terminal and configured to sense from the second a current at the input/output terminal and determining a threshold voltage of the respective semiconductor unit; and a processing circuit configured to classify each of the threshold voltages determined by the respective sense amplifiers into a first a state and a second shape State, and marking the state of each of the threshold voltages on the corresponding address in the mapping table. The integrated circuit of claim 8, wherein the at least one current adjustment element comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL) In one case, the length of the current path is longer than the width of the current path. The integrated circuit of claim 8, wherein the at least one current adjustment element comprises at least one grain boundary. The integrated circuit of claim 10, wherein the length of the current path is between an average grain width of the current path and three times an average grain width of the current path. The integrated circuit of claim 10, wherein the thickness of the current path is less than an average grain width of the current path. The integrated circuit of claim 10, wherein the grain boundary is located adjacent to the at least one first input/output terminal and the at least one second input/output terminal. The integrated circuit of claim 10, further comprising: a common first input/output terminal line electrically connected to the first input/output terminal of the semiconductor component; and a common word line, electrical Connected to the control terminal of the semiconductor component. The integrated circuit of claim 10, wherein the semiconductor component comprises: a semiconductor substrate; a plurality of fin layers, the fin layer being vertically disposed on the semiconductor substrate, wherein the current path is formed at a top of the fin layer, and the first input/output terminal and the The second input/output terminals are respectively disposed at one end and the other end of the fin layer and connected to the current path; and a plurality of dielectric layers disposed on the plurality of fin layers Above, wherein the control terminal is above the dielectric layer. The integrated circuit of claim 15, wherein the dielectric layers extend further into a space between the fin layers, and the control terminals further surround the dielectric layers. The integrated circuit of claim 10, wherein the first input/output terminals, the current paths, and the second input/output terminals form a plurality of nanowires, more accompanied by A plurality of dielectric layers, and the control end further surrounds the nanowire. The integrated circuit of claim 17, wherein the diameter of the nanowires is smaller than the average grain width of the current path. The integrated circuit of claim 10, wherein the semiconductor device comprises: a semiconductor substrate configured to serve as the first input/output terminal; and a plurality of built on the semiconductor substrate a vertical column configured to function as the current path; a plurality of dielectric layers surrounding the plurality of vertical pillars, the second input/output terminal being disposed on the vertical pillars, with the dielectric layer interposed therebetween The control end surrounds the vertical column. The integrated circuit of claim 19, wherein the diameter of the vertical columns is smaller than the average grain width of the current path. A method for generating a password, which is applicable to an integrated circuit having a plurality of semiconductor elements, each of which includes a first input/output terminal, a second input/output terminal, and a current path, the method comprising: configuring each semiconductor The component is represented by a mapping table; determining a first read voltage and a reference current; sensing a current from the second input/output terminal and confirming a threshold voltage of the corresponding semiconductor component, wherein at least one current is adjusted The component is disposed in the at least one current path to adjust the current; classifying each threshold voltage into a first state and a second state; and marking the address of each semiconductor component in the corresponding mapping table according to the state of the threshold voltage. The cryptographic generating method according to claim 21, wherein the at least one current adjusting element comprises at least one doping ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL) In one case, the length of the current path is longer than the width of the current path. The cryptographic generating method of claim 21, wherein the at least one current adjusting component comprises at least one grain boundary. The method for generating a password according to claim 23, wherein the step of classifying the confirmed threshold voltage to the first state and the second state further comprises the step of: if the threshold voltage of the semiconductor component is lower than the first When the voltage is read, the classification threshold voltage is the first state; and if the threshold voltage of the semiconductor element is higher than the first read voltage, the classification threshold voltage is the second state. The method for generating a password according to claim 23, further comprising the step of: if the state of the threshold voltage is classified into the first state, marking the corresponding bit of the semiconductor component in the mapping table in white And if the state of the threshold voltage is classified into the second state, the corresponding address of the semiconductor component in the mapping table is marked in black. The method for generating a password according to claim 23, wherein the step of classifying each of the confirmed threshold voltages into the first state and the second state further comprises the step of comparing the first time from the first time a current of the two input/output terminals and a reference current; determining whether a first number is greater than a second number, wherein the first number indicates that the current from the second input/output terminal is greater than the reference current Number of times, and the second number indicates the number of times the current from the second input/output terminal is less than the reference current; If the first number is greater than the second number, classifying the corresponding threshold voltage into the first state; and if the first number is less than the second number, The respective threshold voltages are classified into the second state. The method for generating a password according to claim 23, wherein the step of classifying each of the confirmed threshold voltages into the first state and the second state further comprises the step of: determining a second read voltage, wherein The second read voltage is higher than the first read voltage; the respective threshold voltages are classified into the first state, the second state, and a third state. The method for generating a password according to claim 27, wherein the step of classifying each of the threshold voltages into the first state, the second state, and the third state further comprises: if the threshold voltage of the semiconductor unit Lower than the first read voltage, classifying the threshold voltage into the first state; if the threshold voltage of the semiconductor unit is higher than the first read voltage and lower than the second Reading the voltage, classifying the threshold voltage into the second state; and if the threshold voltage of the semiconductor unit is higher than the second read voltage, classifying the threshold voltage as the first Three states. The method for generating a password according to claim 27 of the patent application scope further includes: If the state of the threshold voltage is classified into the first state, the corresponding address of the semiconductor component in the mapping table is marked in red; if the state of the threshold voltage is classified into the second state, then Marking the corresponding address of the semiconductor component in the mapping table in green; and if the state of the threshold voltage is classified into the third state, marking the corresponding address of the semiconductor component in the mapping table in blue . The method for generating a password according to claim 27, the step of classifying each of the threshold voltages into the first state, the second state, and the third state further comprises: providing the first read voltage; a set time, comparing the current from the second input/output terminal with the reference voltage; determining whether a first number is greater than a second number, wherein the first number represents a location from the second input/output terminal The current is greater than the number of reference currents, and the second number represents the number of times the current from the second input/output is less than the reference current; and if the first number is greater than the first The two numbers classify the respective threshold voltages into the first state. The method for generating a password according to claim 30, if the first number is smaller than the second number, the method further comprises the steps of: applying the second read voltage; comparing the source The current at the second input/output terminal and the reference current a predetermined number of times; determining whether a third number is greater than a fourth number, wherein the third number indicates that the current from the second input/output terminal is greater than the number of reference currents, The fourth number represents the number of times the current from the second input/output terminal is less than the reference current; and if the third number is less than the fourth number, the corresponding threshold voltage is classified And being the second state; and if the third number is greater than the fourth number, classifying the corresponding threshold voltage into the third state. The cryptographic generation method of claim 23, wherein the length of the current path is between an average grain width of the current path and three times an average grain width of the current path. The cryptographic method of claim 23, wherein the thickness of the current path is less than an average grain width of the current path. The cryptographic generating method of claim 23, wherein the grain boundary is located adjacent to the at least one first input/output terminal and the at least one second input/output terminal. A method of data exchange between a first device and a second device, the second device having a plurality of semiconductor components, each semiconductor component comprising a first input/output terminal, a second input/output terminal, and a second a current path and a control terminal, the data exchange method includes: providing a first group of packets to the first device to transmit to a second device through the network And wherein the first group of the packets includes an order of reading voltages; generating a second group of the packets by using the second device in response to the first group of the packets, and transmitting the second group of packets of the packets to The first device: comparing the first group of the packet with the second group of the packet by using an identification management unit in the first device, and generating a comparison result; determining, according to the comparison result, whether the second device allows The first device is in communication, wherein the step of generating the second group of the packets by using the second device in response to the first group of the packets comprises: configuring the respective semiconductor elements to represent the address in a mapping table; a first read voltage and a reference current; sensing a current from the second input/output terminal and confirming a threshold voltage of the corresponding semiconductor component, wherein at least one current adjustment component is disposed in the at least one current path to adjust the current; Each of the threshold voltages is a first state and a second state; and the addresses of the respective semiconductor components in the corresponding mapping table are marked according to the state of the threshold voltage. The data exchange method of claim 35, wherein the at least one current adjustment element comprises at least one dopant ion, and any one of a width or a thickness of a current path defined according to DeBloyd Length (DBL) And the length of the current path is longer than the width of the current path. For example, the data exchange method described in claim 36, wherein the second The device further includes: a common first input/output terminal line electrically connected to the first input/output terminal of the semiconductor component; and a common word line electrically connected to the control terminal of the semiconductor component. The data exchange method of claim 35, wherein the at least one current adjustment element comprises at least one grain boundary. The data exchange method of claim 38, wherein the length of the current path is between the average grain width of the current path and three times the average grain width of the current path. The data exchange method of claim 38, wherein the thickness of the current path is less than an average grain width of the current path. The data exchange method of claim 35, wherein the step of classifying the confirmed threshold voltage to the first state and the second state further comprises the step of: if the threshold voltage of the semiconductor component is lower than the first read When the voltage is taken, the classification threshold voltage is the first state; and if the threshold voltage of the semiconductor element is higher than the first read voltage, the classification threshold voltage is the second state. The data exchange method as claimed in claim 41, further comprising the step of: if the state of the threshold voltage is classified into the first state, marking the corresponding address of the semiconductor component in the mapping table in white ;as well as If the state of the threshold voltage is classified into the second state, the corresponding address of the semiconductor component in the mapping table is marked in black. The data exchange method of claim 35, wherein the step of classifying each confirmed threshold voltage into the first state and the second state further comprises the steps of: determining a second read voltage, wherein the The second read voltage is higher than the first read voltage; the respective threshold voltages are classified into the first state, the second state, and a third state. The data exchange method of claim 43, wherein the step of classifying each of the threshold voltages into the first state, the second state, and the third state further comprises: if the threshold voltage of the semiconductor unit is low And at the first read voltage, classifying the threshold voltage into the first state; if the threshold voltage of the semiconductor unit is higher than the first read voltage and lower than the second read Taking the voltage, classifying the threshold voltage into the second state; and if the threshold voltage of the semiconductor unit is higher than the second read voltage, classifying the threshold voltage into the third status. The method for exchanging data according to claim 43 further includes: if the state of the threshold voltage is classified into the first state, marking the corresponding address of the semiconductor component in the mapping table in red; If the state of the threshold voltage is classified into the second state, the corresponding address of the semiconductor component in the mapping table is marked in green; and if the state of the threshold voltage is classified into the third state, The corresponding address of the semiconductor component in the mapping table is then marked in blue.