TWI520298B - Electrostatic discharge protection against latch-up - Google Patents

Description

Electrostatic discharge protection against latch-up

The present invention relates to an electrostatic discharge protection that is free of latch-up.

Electrostatic discharge (ESD), which is generated by static electricity, is typically characterized by a high-voltage discharge at a rapid instant. ESD events can occur in electrical and electronic circuits, such as integrated circuits (ICs). It can generate a high voltage sufficient to cause destructive breakdown of devices connected to, for example, input and/or output of integrated circuits.

The way to protect ICs from ESD is to use a controlled voltage rectifier (SCR). However, conventional SCR circuits are subject to latch-up during normal IC operation. The latch affects the operation of the IC and causes defects.

Therefore, ESD protection circuits that can be quickly triggered to avoid damaging internal circuitry and are not affected by latch-up during normal operation are desirable.

Presented is an electrostatic discharge module. The electrostatic discharge module includes: an electrostatic discharge circuit having a pad end and a low potential power terminal; and a latch control circuit including a first latch end coupled to the high potential power source and coupled Connecting to a latch output of the electrostatic discharge circuit; and a first mode of operation and a second mode of operation; wherein, in the first mode of operation, the latch control circuit is disabled and the electrostatic discharge circuit has less than 100 mA The first trigger current I _t1 , and in the second mode of operation, the latch control circuit is activated, and the electrostatic discharge circuit has a second trigger current I _t2 greater than 100 mA.

In another embodiment, an electrostatic discharge module is disclosed. The ESD module includes: an ESD circuit having a pad end and a low potential power terminal; and a latch control circuit including a first latch input coupled to the high potential power supply and a second coupled to the low potential power supply a latch input and a latch output coupled to the electrostatic discharge circuit; and a first mode of operation and a second mode of operation; wherein in the first mode of operation, the latch control circuit is deactivated and the electrostatic discharge The circuit has a first trigger current I _{t1 of} less than 100 mA, and in the second mode of operation, the latch control circuit is activated and the electrostatic discharge circuit has a second trigger current I _t2 greater than 100 mA.

In yet another embodiment, presented is a method of forming a device. The method includes: providing a substrate having an electrostatic discharge module, wherein the electrostatic discharge module includes an electrostatic discharge circuit having a pad end and a low potential power terminal, including a first latch input coupled to the high potential power source and coupled a latch control circuit at a latch output end of the electrostatic discharge circuit, and a first mode of operation and a second mode of operation for the electrostatic discharge module; wherein, in the first mode of operation, the latch control circuit is The electrostatic discharge circuit is deactivated and has a first trigger current I _{t1 of} less than 100 mA, while in the second mode of operation, the latch control circuit is activated and the electrostatic discharge circuit has a second trigger current I _t2 greater than 100 mA.

These and other advantages and features of the present invention will become apparent from the following description and appended claims. In addition, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can be various combinations and arrangements.

100‧‧‧ device

110‧‧‧Electrostatic discharge module

112‧‧‧First end, pad

116‧‧‧Second terminal, low potential power supply

118‧‧‧High potential power supply

120‧‧‧Electrostatic discharge circuit

124‧‧‧First part

128‧‧‧Second part

130‧‧‧First site well zone

134‧‧‧ first first part contact area

136‧‧‧Second first site contact area

140‧‧‧Second-site well zone

144‧‧‧ first second contact area

146‧‧‧Second second site contact area

160‧‧‧Latch control circuit

162‧‧‧First latch control input connector

164‧‧‧Second latch control input connector

168‧‧‧Latch control output

170‧‧‧Internal circuits

192‧‧‧Latch current path

220‧‧‧ Parasitic circuit

292‧‧‧ Current path

361‧‧‧ latch control input (LU _i)

364‧‧‧Latch output (LU _o )

366‧‧‧LU _i output

371‧‧‧LU _o input

372‧‧‧First LU _o connector

374‧‧‧Second LU _o connector

396‧‧‧Second latch current path

B1‧‧‧ first base extreme

B2‧‧‧ second base extreme

C1‧‧‧ first episode extreme

C2‧‧‧ Second episode extreme

D1‧‧‧First parasitic diode

D2‧‧‧Second parasitic diode

E1‧‧‧first emitter

E2‧‧‧second emitter

Inv ₁ ‧‧‧First Inverter

Inv ₂ ‧‧‧Secondary reverser

N _con1 , N _con2 , N _con3 ‧‧‧ nodes

Q1‧‧‧First bipolar junction transistor (BJT), first parasitic transistor

Q2‧‧‧Second bipolar junction transistor (BJT), second parasitic transistor

R _C ‧‧‧Resistors

Rp‧‧‧second resistor

In the drawings, the same component symbols generally refer to the same components throughout the drawings. Also, the drawings are not necessarily drawn to scale, and emphasis is often placed in describing the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, wherein: FIG. 1 shows a specific embodiment of a device having an electrostatic discharge module; and FIG. 2 shows a parasitic circuit. A specific embodiment of the electrostatic discharge module; FIG. 3 shows a specific embodiment of the latch control circuit; and FIGS. 4a to 4b show a specific embodiment of the electrostatic discharge module in the electrostatic discharge and latch mode; and 5a to Figure 5b shows the current-voltage (IV) curve for a particular embodiment of the electrostatic discharge module in electrostatic discharge mode and latch mode.

Particular embodiments are generally associated with semiconductor devices. In a specific embodiment, the device includes an ESD circuit. For example, an ESD circuit is activated during an ESD event to dissipate a pulse (TLP) current of a transmission line. Examples of devices can be any type of semiconductor device, such as integrated circuits (ICs). ICs can be combined or used with, for example, electronics, computers, displays, mobile phones, and personal digital assistants (PDAs). FIG. 1 shows a specific embodiment of a portion of device 100. This device is formed in the semiconductor substrate 105. In a specific embodiment, the substrate is a germanium substrate. Other types of semiconductor substrates may also function, including on-insulator semiconductor substrates. In a specific embodiment, the substrate is a lightly doped p-type germanium substrate. For example, a lightly doped p-type substrate has a dopant concentration of about 1.7e15 cm" ³ . Other doping concentrations can also be useful. In other embodiments, the substrate can be doped with n-type dopants and/or other dopant concentrations. For example, a P-type dopant including boron (B), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. .

The device includes an ESD module 110. In one embodiment, the ESD module includes an ESD circuit 120 and a latch (latch) control circuit 160. As shown, the ESD circuit is placed in the substrate. The ESD circuit can include an isolation region (not shown) for isolating the ESD circuit. For example, an ESD isolation region can surround an ESD circuit. The ESD isolation region can be a trench isolation region. The ESD isolation region is, for example, a shallow trench isolation (STI) region. The ESD isolation area can be the same as those used to isolate the active area of the device. Other types of isolated area configurations can also be useful. In other embodiments, the ESD isolation region is not set.

In one embodiment, the ESD circuit is a Voltage Controlled Rectifier (SCR) ESD circuit. The ESD circuit includes a first portion (first portion) 124 and a second portion (second portion) 128. These parts are the terminals that act as ESD circuits. For example, the first terminal 112 and the second terminal 116 are coupled to the first portion and the second portion. In a specific embodiment, the first terminal is coupled to the pad. For example, the pads are I/O pads of the device. The second terminal is coupled to the low potential power source. The low potential power supply is exemplified by a ground or common ground voltage (V _SS ). Other types of terminal coupling configurations may also be useful.

The internal circuit 170 is coupled to the pad. For example, the internal circuit is an I/O circuit such as an inverter. Other types of internal circuits can also be coupled to the pads. The internal circuit is coupled between the high potential power source 118 and the low potential power source 116. For example, a high potential power supply can be V _DD and a low potential power supply can be a common ground voltage. Other high and low potential power supplies can also be useful.

In a specific embodiment, the first portion includes a first portion well region 130. The first portion well region is doped with a second polarity type dopant. The second portion includes a second portion well region 140. The second portion well region is doped with a first polarity type dopant. In a specific embodiment, the first polarity is p-type and the second polarity type is n-type. Other polarity type configurations can also be useful. In a particular embodiment, one of the well regions can be disposed by a substrate. The substrate can be considered as a well region of one of the ESD sites with proper doping. For example, if the substrate is suitably doped with a first polarity type dopant, it can act as a second portion well region. Other well zone configurations can also be useful.

The first portion and the second portion may be separated by an intermediate isolation region (not shown). An example of an intermediate isolation region can be a portion of the ESD isolation region. Other isolated area configurations can also be useful.

The first portion includes a first contact region 134 and a second first portion contact region 136. The first first part contact area is the first The polarity type contact area, and the second first part contact area is the second polarity type contact area. The first and second first portion contact regions act as contact regions for the first terminal. For example, the first and second first portion contact regions are commonly coupled to the pads. In a specific embodiment, a first portion isolation region (not shown) for separating the first portion contact region may be disposed. In other embodiments, a first portion isolation region for separating the first portion contact area is not provided. For example, the first portion contact area is a docking contact area. The second portion includes a first contact region 144 and a second second portion contact region 146. The first second portion contact area is a first polarity type contact area, and the second second part contact area is a second polarity type contact area. The first and second second portion contact regions act as contact regions for the second terminal. For example, the first and second second portion contact regions are coupled to a low potential power source, such as a common ground terminal voltage. A second portion isolation region (not shown) for separating the first and second second portion contact regions may be provided. In other embodiments, a second portion isolation region for separating the first and second second portion contact regions is not provided. For example, the first and second second portion contact areas are butt contact areas.

In a specific embodiment, the contact area is a heavily doped region. It is also useful to set the contact area of other dopants with a rich concentration. In addition, a metal telluride contact portion may be provided on the surface of the contact region. For example, the telluride contact can reduce the contact resistance. As shown, the first and second contact regions of the first portion and the second portion are arranged such that the second contact regions are adjacent to each other. It is to be understood that the first and second contact areas are other Configuration can also be useful. For example, the first contact regions that are adjacent to each other or a portion of the first contact regions and the second contact regions of the other portion are adjacent to each other.

The ESD circuit generates a current path for dissipating ESD current from the pad to ground in an ESD condition. For example, sufficient ESD current can be initiated or triggered by the ESD circuit to generate a current path. The value of the current that starts the ESD circuit is called the trigger current I _t .

In a specific embodiment, a latch (LU) control circuit 160 is provided. As shown, the latch control circuit includes a first latch control input terminal 162 and a second latch control input terminal 164 and a latch control output 168. The first latch control input is coupled to the high potential power source 118 and the second latch control input is coupled to the low potential power source 116. For example, the high potential power supply is V _DD and the low potential power supply is the common ground voltage. Setting other high and/or low potential power supplies can also be useful. In a specific embodiment, the control output is coupled to the second first portion contact area.

The ESD module has first and second modes of operation. One of the modes of operation is the ESD mode and the other mode of operation is the latch mode. For example, the first mode is the ESD mode; the second mode is the latch (latch) mode. The latch control circuit is deactivated in ESD mode and is activated in latch mode. In the latch mode, the power supply (e.g., V _DD) on the device or apparatus is supplied to. As such, the device is operating under normal conditions, but has a higher positive or negative direct current (DC) voltage to drive current to the pads. The power supply is floating for the ESD mode.

In a specific embodiment, the ESD circuit has a first trigger current I _t1 in the first mode of operation and a second trigger current I _t2 in the second mode of operation. For example, in the ESD circuit having ESD mode I _t1, I _t2 having the latch mode. In a specific embodiment, I _t1 <I _t2 . In one specific embodiment, I _t1 less than the trigger current threshold and I _t2 is greater than I _tt I _tt. The trigger current threshold I _tt is 100 mA. According to Solid State Technology Association JEDEC, I _t able to avoid latch greater than 100mA. Preferably, I _t1 is low enough to quickly trigger the ESD circuit to avoid damaging internal circuitry.

The ESD circuit generates parasitic circuits. Fig. 2 shows a parasitic circuit 220 of the ESD circuit 120 of Fig. 1. Referring to FIGS. 1 to 2, the parasitic circuit includes a first bipolar junction type transistor (BJT) Q1 and a second bipolar junction type transistor (BJT) Q2 between the pad 112 and the low potential power source 116. . In a specific embodiment, Q1 is a pnp type transistor and Q2 is an npn type transistor.

The first transistor Q1 includes a first emitter terminal E1, a first base terminal B1, and a first collector terminal C1. Similarly, Q2 includes a second emitter extreme E2, a second base extreme B2, and a second set extreme C2. In a specific embodiment, Q1 is a pnp transistor and Q2 is an npn transistor.

In a specific embodiment, the first emitter extreme E1 is formed by the first first portion contact region. For example, the first emitter extreme E1 is a heavily doped p-type first first site contact region. The P-type substrate forms the first collector C1 and the first base terminal B1 is formed by n-doping the first portion well region. This produces a first vertical pnp transistor. For example, a vertical pnp transistor is formed along a direction perpendicular to the surface of the substrate. The pad is coupled to the first emitter terminal E1, and the first collector terminal C1 is coupled to the low potential power source by a second resistor R _p formed by p-doping the second portion well region. The connection of the first set of extremes C1 to the second resistor _Rp forms a second node N2. The base of Q1 is coupled to the contact area of the second first portion and the output of the control circuit. The connection between the first base end B1 and the second first portion contact area forms the first node N1.

As shown, the second bipolar junction transistor Q2 is coupled between the first node N1 and the low potential power supply. For example, the second set terminal C2 is coupled to the first node N1 and the second emitter terminal E2 is coupled to the low potential power source. The base of the second bipolar junction type transistor Q2 is coupled to the second node N2. For example, the second bipolar junction transistor Q2 is coupled to the first collector terminal C1 and the low potential power source at the second node N2. This forms a second lateral npn transistor. For example, the second lateral transistor is parallel to the surface of the substrate. The second set of extreme C2 is formed by n-doping the first portion well region, the second base terminal B2 is formed by the p-type doped second portion well region, and the second emitter terminal E2 is formed by the n-type doping second. A second portion of the contact area is formed. When the ESD circuit is triggered, a current path 292 is created between the pads and a low potential source such as a common ground terminal voltage. As shown, the current path between the pads and the common ground terminal voltage flows through the first emitter terminal E1, the first base terminal B1, the second collector terminal C2, the second base terminal B2, and the second emitter terminal E2. This current path is called the latch current path of the ESD circuit. When sufficient substrate current, such as I _t , is turned on via the first base terminal B1 and the first collector terminal C1, the ESD circuit is triggered to generate a latch current path. In a specific embodiment, in the ESD mode, I _t is equal to I _t1 .

Figure 3 shows a specific embodiment of a latch control circuit 160 that may include a common component as shown in Figure 1. As such, common elements may not be described or detailed. The latch control circuit includes a latch control input (LU _i) and an output portion 361 (LU _o) portion 364. The LU _i portion has an LU _i output 366 and is coupled to inputs 162 and 164 of the latch control circuit. The LU _o portion includes a LU _o input 371 and a first LU _o terminal 372 and a second LU _o terminal 374. The LU _o input is coupled to the LU _i output, and the first LU _o terminal is coupled to the high potential power supply, and the second LU _o terminal is coupled to the latch control output 168 of the ESD circuit. . For example, the latch control output is coupled to the first node N1 of the ESD circuit.

In one embodiment, if no power is supplied to the device, the LU _i portion is located at the LU _i output to generate a non-operating LU _i output signal. On the other hand, when the electric power is supplied to the apparatus, the LU _i located LU _i LU _i generated at the output signal has an output operation. For example, LU _i produces a non-operating LU _i output signal when V _DD =0 V, and LU _i produces an action LU _i output signal when V _DD = V _DD . In one embodiment, the inactive LU _i output signal disables the LU _o portion, causing the ESD module to operate in the ESD mode; the action LU _i output signal activates the LU _o portion, causing the ESD module to be in the latch mode operating.

The second latch current path 396 is generated when the LU _o portion is activated. The second latch current path is from the pad to the high potential supply through N1. When LU _o does not operate, no second latch current path is generated. For example, the second current path is generated in the latch mode, but there is no current path in the ESD mode. In a specific embodiment, the second current path includes a first bipolar junction type transistor D1 between the pad and the first node N1, and a second bipolar junction from the first node N1 to the high potential power source. Type transistor D2. The diodes are coupled in series, wherein the first anode of the first bipolar junction transistor D1 is coupled to the pad, and the first cathode of the first bipolar junction transistor D1 is coupled to the first node. N1, the second anode of the second bipolar junction transistor D2 is coupled to the first node N1, and the second cathode of the second bipolar junction transistor D2 is coupled to the high potential power source.

In a specific embodiment, the LU _o site comprises a LU _o transistor. LU _o transistor is a p-type MOSFET (the pFET) in a particular embodiment. LU _o comprises a first transistor and a second source / drain (S / D) terminal and gate terminal. The source/germanium is a p-type doped region. The body of the transistor formed by the n-type transistor well region is coupled to the first source/deuterium terminal.

The active LU _i signal is a logic 1 signal in one embodiment, while the LU _i signal is a logic 0 signal. Other configurations with action and no action LU _i signals can also be useful. The action LU _i signal turns off the LU _o transistor in one embodiment. This results in the formation of a second current path comprising the first bipolar junction type transistor D1 and the second bipolar junction type transistor D2. The first diode D1 is formed by a first portion with a first contact region portion the well region and the first source by the transistor well region D2 and the transistor LU _o / drain terminal is formed. The no-action LU _i signal turns on the LU _o transistor to create a path between the first and second source/deuterium terminals. This allows the ESD circuit to operate in ESD mode.

In a specific embodiment, the LU _i portion includes first and second inverters Inv ₁ and Inv ₂ coupled in series. The resistor R _C is coupled to the first inverter input of Inv ₁ . In a specific embodiment, the resistor R _C is a poly resistor. An example of a resistor can be a non-deuterated resistor. Which prevents inverter when V _DD high current gate oxide breakdown. The first inverter output of Inv ₁ is coupled to the second inverter input of Inv ₂ . The second inverter output acts as an LU _i output coupled to the LU _o input. When power is supplied to the device, node N _con1 is equal to logic 1, N _con2 is equal to logic 0, and N _con3 is equal to logic 1. This produces an action LU _i output signal that causes the LU _o portion to act to generate a second current path. When power is not supplied to the device, V _DD is floating (zero potential). Thus, node N _con1 is equal to logic 0, N _con2 is equal to logic 1 and N _con3 is equal to logic 0. This produces a non-operating LU _i output signal, causing the LU _o portion to not operate.

By setting the second current path in the latch mode, the current required to trigger the ESD circuit (eg, I _t2 ) is divided by two. In such a situation, a higher current is required to maintain the substrate potential required to start the ESD circuit. In a specific embodiment, I _{t2 is} greater than the threshold and latch-up is prevented in the latch mode. On the other hand, the trigger current (eg, I _t1 ) is less than the threshold, causing the ESD circuit to be quickly triggered in the ESD mode to avoid damaging the internal circuitry.

Figures 4a through 4b illustrate a particular embodiment of the operation of the ESD module in ESD and latch mode. The ESD module includes a latch control circuit 160 coupled to the ESD circuit 120. The ESD module can include common components as described in Figures 1 through 3. For example, the latch control circuit and the ESD circuit are similar to those described in FIGS. 1 to 3. As such, common components may not be described or detailed.

Referring to Figures 4a to 4b, the ESD circuit forms a first bipolar junction transistor Q1 and a second bipolar junction transistor Q2. The first bipolar junction type transistor Q1 is a pnp transistor and the second bipolar junction type transistor Q2 is an npn transistor. As for the latch control circuit, the first latch terminal 162 and the second latch terminal 164 are coupled to the high potential power source 118 and the low potential power source 116. The high potential power supply is exemplified as V _DD and the low potential power supply can be a common ground voltage. The latch output is coupled to the first node N1 of the ESD circuit.

Referring to Figure 4a, when V _{DD is} not supplied to the device or IC, the high potential power supply is floating or at zero potential. As such, the latch control circuitry is disabled, causing the ESD circuitry to operate in ESD mode. In an ESD condition, for example, the ESD is placed on a (zap) pad and current is passed through the substrate _Rp through the first bipolar junction transistor Q1 to ground. When there is sufficient current to pass through the second resistor _Rp , the second bipolar junction transistor Q2 is turned on, creating a latch current path 192 in the ESD circuit. For example, the latch current path is generated when the current flowing through the second resistor _Rp reaches the trigger current _It1 .

Figure 5a shows the IV curve of the ESD module in ESD mode. The trigger current I _{t1 is} much less than 100 mA. This causes the ESD circuit to quickly trigger to create a latched current path that avoids damage to the internal circuitry it is protecting.

Referring to Figure 4b, when power is supplied to the device, the high potential power supply is equal to V _DD . As such, the latch control circuit is activated, causing the ESD circuit to operate in the latch mode. In the latched mode, the ESD circuit has a second current path 396 along the latch current path 292. The second current path is from the pad to the first node N1 to the high potential power source. The second current path is formed by the first and second bipolar junction transistors D ₁ and D ₂ . Due to the ESD circuit with two current paths, the trigger current I _t2 in the latch mode is greater than 100 mA, as shown in Figure 5b. This prevents the ESD circuit from latching in the latch mode.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics. Therefore, the foregoing specific embodiments are to be considered in all respect The scope of the present invention is intended to be in the scope of the appended claims, and is not intended to

100‧‧‧ device

110‧‧‧Electrostatic discharge module

112‧‧‧First end, pad

116‧‧‧Second terminal, low potential power supply

118‧‧‧High potential power supply

120‧‧‧Electrostatic discharge circuit

124‧‧‧First part

128‧‧‧Second part

130‧‧‧First site well zone

134‧‧‧ first first part contact area

136‧‧‧Second first site contact area

140‧‧‧Second-site well zone

144‧‧‧ first second contact area

146‧‧‧Second second site contact area

160‧‧‧Latch control circuit

162‧‧‧First latch control input connector

164‧‧‧Second latch control input connector

168‧‧‧Latch control output

170‧‧‧Internal circuits

Claims (20)

An electrostatic discharge module comprising: an electrostatic discharge circuit having a pad end and a low potential power terminal; a latch control circuit including a first latch input coupled to the high potential power supply And a latch output coupled to the electrostatic discharge circuit; and a first mode of operation and a second mode of operation for the electrostatic discharge module; wherein, in the first mode of operation, the latch control circuit is stopped used, and the ESD trigger circuit having a first current I _t1 is less than 100mA, in the second mode of operation, the latch control circuit is activated, and the ESD circuit having a second triggering current I _t2 greater than 100mA at Avoiding latching, and wherein the latch control circuit includes: a latch control input portion having first and second inverters coupled in series, the second inverter output acting as the latch control input The output end of the portion, the latch control output portion, has a transistor, the first terminal is coupled to the high potential power source, the second terminal is coupled to the latch output terminal, and the gate terminal is coupled Coupling At the output of the latch control input location, and in the second mode of operation, a second operational mode current path is generated between the pad terminal, the latch output, and the high potential power source. The electrostatic discharge module of claim 1, wherein the second operational mode current path comprises a first parasitic diode between the pad end and the latch output and at the latch A second parasitic diode between the output and the high potential power source. The electrostatic discharge module of claim 2, wherein the electrostatic discharge circuit comprises a first portion and a second portion, wherein the first portion comprises a first portion well doped with a second polarity type dopant The region, and the second portion, comprises a second portion well region doped with a first polarity type dopant. The electrostatic discharge module of claim 3, wherein the first portion comprises a first first portion contact region doped with a first type of polar dopant and a second dopant doped with a second type The first first part contact area and the second first part contact area are coupled to the pad end. The electrostatic discharge module of claim 4, wherein the second portion comprises a first second portion contact region doped with a first type of polar dopant and a second dopant doped with a second type The two second portion contact regions, the first second portion contact region and the second second portion contact region are coupled to the low potential power source. The electrostatic discharge module of claim 5, wherein the second first portion contact region and the second second portion contact region are adjacent to each other. The electrostatic discharge module of claim 6, wherein the contact regions are heavily doped. The electrostatic discharge module of claim 7, wherein the electrostatic discharge circuit generates a current path from the pad end to the low potential power terminal to dissipate the electrostatic discharge current under an electrostatic discharge condition. The electrostatic discharge module of claim 1, wherein the electrostatic discharge circuit comprises an electrostatic discharge circuit based on a controlled rectifier. The electrostatic discharge module of claim 1, wherein the latch control circuit includes a second latch input coupled to the low potential power source. The electrostatic discharge module of claim 1, wherein the electrostatic discharge circuit comprises a first bipolar junction type transistor and a second bipolar junction type transistor, wherein the first bipolar junction The type transistor is a pnp transistor and the second bipolar junction type transistor is an npn transistor. The electrostatic discharge module of claim 11, wherein the first bipolar junction type transistor comprises: a first emitter coupled to the pad end; and a first base coupled to The latch output terminal; and the first collector are coupled to the low potential power source. The electrostatic discharge module of claim 12, wherein the first emitter is formed by the first first portion contact region, and the first base is formed by the first portion well region. And the first collector is formed by the substrate, and the first base is connected to the second first portion The contact regions are connected to form a first node, and the first collector formed by the second portion well region is connected to the resistor to form a second node. The electrostatic discharge module of claim 13, wherein the second bipolar junction type transistor comprises: a second emitter directly coupled to the low potential power source; and a second base coupled And the second node is coupled to the first node. The electrostatic discharge module of claim 14, wherein the second emitter is formed by the second second portion contact region, and the second base is formed by the second portion well region. And the second collector is formed by the well portion of the first portion. An electrostatic discharge module comprising: an electrostatic discharge circuit having a pad end and a low potential power terminal; a latch control circuit including a first latch input coupled to the high potential power supply a second latch input coupled to the low potential power source and a latch output coupled to the electrostatic discharge circuit; and a first mode of operation and a second mode of operation for the electrostatic discharge module; In the first mode of operation, the latch control circuit is deactivated, and the electrostatic discharge circuit has a first trigger current I _{t1 of} less than 100 mA, and in the second mode of operation, the latch control circuit is activated, the electrostatic discharge circuit and having a second greater than 100mA to avoid triggering current I _t2 latch and wherein the latch control circuit comprises: a latch input control portion, having first and second reverse coupled in series The second inverter output acts as an output of the latch control input portion, and the latch control output portion has a transistor coupled to the high potential power source with the first terminal, and the second The terminal is coupled to the latch output end, and the output terminal coupled to the latch control input portion with the gate terminal, and in the second operation mode, the latch output is at the pad end A second operational mode current path is generated between the terminal and the high potential power supply. The electrostatic discharge module of claim 16, wherein the electrostatic discharge circuit comprises a first portion and a second portion, wherein the first portion comprises a first portion well doped with a second polarity type dopant The region, and the second portion, comprises a second portion well region doped with a first polarity type dopant. The electrostatic discharge module of claim 17, wherein the first portion comprises a first first portion contact region doped with a first type of polar dopant and a second dopant doped with a second type The first first part contact area and the second first part contact area are coupled to the pad end. The electrostatic discharge module of claim 16, wherein the second operational mode current path comprises a first parasitic diode between the pad end and the latch output and at the latch A second parasitic diode between the output and the high potential power source. A method for forming a device, comprising: disposing a substrate prepared with an electrostatic discharge module, wherein the electrostatic discharge module comprises: an electrostatic discharge circuit having an electrostatic discharge circuit at a pad end and a low potential power terminal, latching a control circuit, the latch control circuit includes a first latch input coupled to the high potential power source, a second latch input coupled to the low potential power source, and a latch output coupled to the electrostatic discharge circuit And wherein the latch control circuit includes a latch control input portion having first and second inverters coupled in series, the second inverter output acting as an output of the latch control input portion And a latch control output portion having a transistor coupled to the high potential power source with a first terminal and a second terminal coupled to the latch output terminal, the gate terminal being coupled to the gate terminal The output terminal of the latch control input portion, and the body coupled to the first terminal, and the first operation mode and the second operation mode, for the electrostatic discharge module; wherein, in the first operation mode , The latch control circuit is disabled and the ESD trigger circuit having a first current I _t1 is less than 100mA, and the second mode of operation, the latch control circuit is activated, and the electrostatic discharge circuit is greater than 100mA The second trigger current I _t2 avoids latching, wherein a second operational mode current path is generated between the pad terminal, the latch output, and the high potential power source.