TWI515827B - Internal connection structure with improved reliability and its forming method - Google Patents

Description

Internal connection structure with improved reliability and its forming method

The present invention relates to an interconnect structure and a method of fabricating the same. In particular, the present invention relates to interconnect structures having enhanced electromigration (EM) and time dependent dielectric breakdown (TDDB) reliability. The invention also provides a method of forming the interconnect structure.

A semiconductor device generally includes a plurality of circuits forming an integrated circuit fabricated on a semiconductor substrate. In order to improve the performance of the circuit, a low-k dielectric material having a dielectric constant lower than that of cerium oxide, such as a porous dielectric material, is used as an inter-layer dielectric (ILD) to further reduce the electrostatic capacity. . An interconnect structure made of metal lines or vias is typically formed within or around the porous dielectric material ILD to connect the circuit components. An interconnect structure can be formed by a multi-level or multi-layer plan, such as, for example, a single or dual damascene wiring structure. In a conventional interconnect structure, the metal lines are parallel to the semiconductor substrate, and the metal vias are perpendicular to the semiconductor substrate.

Electro-induced migration (EM) and time dependent dielectric collapse (TDDB) are two major reliability considerations for copper (Cu) interconnects. EM is the transfer of kinetic energy between conducting electrons and diffusing metal atoms, causing material movement caused by the gradual movement of ions in the conductor. TDDB occurs when adjacent interconnects are subjected to different bias voltages for a long time, resulting in increased leakage and eventually short circuit. Both EM and TDDB reduce the reliability of metal interconnects.

In order to reduce the EM and TDDB of the metal interconnects, a dielectric cap layer is deposited directly on the metal. The dielectric cap layer mitigates the EM of the metal interconnect by atomic bonding to the uppermost surface of the underlying metal. In order to deposit a dielectric coating to the metal, a non-metallic material, such as a metal oxide of the underlying metal, must be removed from the metal surface. A "pre-cleaning" process such as plasma treatment is typically required to remove the metal oxide material from the metal. This pre-cleaning process can cause damage to the dielectric material surrounding the metal within the metal interconnect structure, which damage is even greater when the dielectric material is a low dielectric material (low-k) material.

Other types of cover layers include a metal cover layer. Compared to the dielectric cap layer, the metal cap layer generally has a better adhesion strength to the underlying metal. The increased adhesion strength results in better EM resistance for the metal interconnect. For example, a Cu interconnect with a Co alloy overlay exhibits a 10-fold higher adhesion than a Cu interconnect with a standard dielectric cap. EM resistance. Although the EM resistance is improved, the use of a metal coating leaves metal residue on the surface of the dielectric material between the metal components within the metal interconnect. The presence of metal residues reduces the reliability of the metal interconnects.

In view of the above, it is desirable to provide a metal interconnect structure having enhanced EM and TDDB reliability, and a method of fabricating such a metal interconnect structure.

The present invention provides an interconnect structure having a metal cap layer directly on a conductive layer embedded in a dielectric layer and a dielectric cap layer directly on the dielectric layer. The dielectric cap layer is thicker than the metal cap layer and has a bottom surface that is substantially coplanar with a bottom surface of the metal cap layer. The interconnect structure of the present invention provides improved EM and TDDB reliability compared to the conventional interconnect structure described above. The invention also provides a method of forming the interconnect structure.

The first embodiment introduces an interconnect structure comprising: a dielectric layer having a conductive member embedded therein, the conductive member having a first top end surface, substantially one of the dielectric layers The second top surface is coplanar; a metal cover layer directly on the first top end surface, wherein the metal cover layer does not extend substantially above the second top end surface; a first dielectric cover layer directly Located on the second top surface, wherein the first dielectric cover layer does not extend substantially above the first top end surface, and the first dielectric cover layer is thicker than the metal cover layer; and a second dielectric layer a cover layer on the metal cover layer and the first dielectric cover layer.

A second embodiment is directed to a method of forming an interconnect structure, the method comprising: providing a dielectric layer having a conductive member embedded therein, the conductive member having a first top end surface substantially associated with the dielectric layer a second top surface is coplanar; a first dielectric cap layer is formed on the dielectric layer; a portion of the first dielectric cap layer is removed to expose the first top end surface of the conductive member; Selectively forming a metal cap layer on the first top surface, wherein the metal cap layer is thinner than the first dielectric cap layer and does not substantially extend above the second top end surface; and in the first dielectric cap A second dielectric cap layer is formed on the layer and the metal cap layer.

The invention will be described in detail hereinafter with reference to the drawings in which preferred embodiments of the invention are shown. The invention may, however, be modified in many different forms and is not limited to the specific embodiments disclosed herein. Rather, these specific embodiments are provided so that the scope of the disclosure is more complete and the scope of the invention is fully disclosed to those skilled in the art. Where the same numbers represent the same components.

It can be understood that when an element such as a layer is referred to as being "above" the other element, it can be directly on the other element or the intermediate element. In contrast, when an element is referred to as being "directly above" or "directly above" another element, there is no intermediate element.

As noted above, although the EM resistance is improved over the dielectric cap layer, the use of a metal cap layer typically results in residual metal on the surface of the dielectric material between the metal features within the metal interconnect structure. The problem of prior art interconnect structures with metal overlays is shown in FIG. The interconnect structure 100 of FIG. 1 includes two conductive features 104 embedded within a dielectric layer 102. A metal cap layer 106 is formed on the conductive member 104. Dielectric cap layer 108 is on metal cap layer 106 and dielectric layer 102. During the metal cover forming process, the metal residue 110 is simultaneously formed. Some of the metal residue 110 falls between the two conductive members 104, thus causing a short circuit between the two conductive members 104.

The present invention provides an interconnect structure that significantly reduces or eliminates short circuits between adjacent conductive members due to metal remaining in the metal cap forming process. The interconnect structure has a metal cap layer directly on a conductive layer embedded in a dielectric layer, and a first dielectric cap layer directly on the dielectric layer. The electrically conductive member has a first top end surface that is substantially coplanar with a second top end surface of the dielectric layer. The metal cover layer does not extend substantially over the second top end surface, and the first dielectric cover layer does not extend substantially above the first top end surface. The term "substantially does not extend to" as used in the present invention is used to mean that there is no or only a small amount of metal covering material on the top surface of the dielectric layer. Similarly, there is no or only a few first dielectric covering materials on the top surface of the conductive member within the interconnect structure. The first dielectric cap layer is also thicker than the metal cap layer. As such, even if any residual metal capping material remains on the first dielectric cap layer during the metal capping deposition process, the first dielectric cap layer breaks the connection between adjacent conductive features. The term "residual" is used to mean any metal covering material fragments that can be formed during the metal cover forming step. This avoids short circuits between adjacent conductive members. As a result, the interconnect structure of the present invention provides improved EM and TDDB reliability as compared to the conventional interconnect structure described above.

Referring to FIG. 2, this figure provides an initial interconnect structure 200. The initial interconnect structure 200 includes a dielectric layer 202 and at least one conductive feature 204 embedded within the dielectric layer 202. The initial interconnect structure 200 can be over a semiconductor substrate (not shown) that includes one or more semiconductor devices. The initial interconnect structure 200 can additionally include a diffusion barrier layer (not shown) that separates the conductive features 204 from the dielectric layer 202, as desired.

The initial structure 200 can be made by conventional techniques known to those skilled in the art, for example; the initial interconnect structure 200 can be formed by first supplying a dielectric layer 202 to the surface of a substrate (not shown). The substrate can be a semiconductor material, an insulating material, a conductive material, or a combination of two or more of the foregoing. When the substrate comprises a semiconductor material, materials such as Si, SiGe, SiGeC, SiC, Ge alloy, GaAs, InAs, InP or other III/V or II/VI semiconductor materials can be used. In addition to the listed semiconductor materials, the present invention contemplates the case where the substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI) or insulator. Silicon germanium-on-insulator (SGOI). When the substrate is a semiconductor material, one or more semiconductor devices such as, for example, a complementary metal oxide semiconductor (CMOS) device can be fabricated thereon.

When the substrate is an insulating material, the insulating material may be an organic insulator, an inorganic insulator, or a combination of an organic insulator and an inorganic insulator. The substrate can be a single layer or multiple layers.

When the substrate is a conductive material, the substrate may include, for example, polycrystalline germanium, elemental metal, elemental metal alloy, metal halide, metal nitride, or a combination of two or more of the foregoing. The substrate can be a single layer or multiple layers.

Dielectric layer 202 can be any interlayer dielectric, including inorganic dielectric or organic dielectric. Dielectric layer 202 can be porous or non-porous. Examples of suitable dielectrics that can be used as dielectric layer 202 include, but are not limited to, SiO ₂ , sesquioxanes, C-doped oxides including Si, C, O, and H atoms (ie, organic tannic acid) Salt), thermosetting polyarylene ether or a multilayer structure of these. The term "polyaromatic" as used in this application denotes an aryl moiety or a substituted aryl moiety which is bonded, fused to a ring or like an inert chain group such as oxygen, sulfur, sulfonamide, anthracene, carbonyl or the like. Chained together.

Dielectric layer 202 preferably has a dielectric constant of about 4.0 or less, and dielectric layer 202 preferably has a dielectric constant of about 2.8 or less. These dielectrics generally have lower parasitic interference than dielectric materials having a dielectric constant higher than 4.0. The dielectric constant mentioned in this specification is a vacuum measurement.

The thickness of the dielectric layer 202 varies depending on the dielectric material used, as well as the exact number of dielectric films within the initial interconnect structure 200. Typically and for normal interconnect structures, the dielectric layer 202 has a thickness from about 200 nm to about 450 nm.

The conductive member 204 can be formed by photolithography, for example, by applying a photoresist layer on the surface of the dielectric layer 202, the photoresist layer being exposed under the desired illumination pattern. The exposed photoresist layer is developed using a conventional photoresist developer. The patterned photoresist layer is used as an etch mask to transfer the pattern to dielectric layer 202. The etched regions of dielectric layer 202 are then filled into a conductive material to form conductive features 204.

Conductive component 204 includes, but is not limited to, a polysilicon, a conductive metal, an alloy of two or more conductive metals, a conductive metal halide, or a combination of two or more of the foregoing. Conductive member 204 is preferably a conductive metal such as Cu, Al, W or alloys thereof. The conductive member 204 is more preferably Cu or a Cu alloy (for example, AlCu). The conductive material is filled into the etched region of the dielectric layer 202 using a conventional deposition process, including but not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition). , PECVD), sputtering, chemical solution deposition or electroplating to form conductive features 204. After deposition, a conventional planarization process such as, for example, chemical mechanical polishing (CMP) can be used to provide a conductive member 204 having a top end surface 208 that is substantially coplanar with the top end surface 206 of the dielectric layer 202. Structure.

Conductive member 204 is preferably separated from dielectric layer 202 by a diffusion barrier layer (not shown). The diffusion barrier layer can include, but is not limited to, Ta, TaN, Ti, TiN, Ru, RuTaN, RuTa, W, WN or any other material that can act as a barrier to prevent diffusion of the conductive material into the dielectric layer. The diffusion barrier layer may be formed by a deposition process such as, for example, atomic layer deposition (ALD), CVD, PECVD, physical vapor deposition (PVD), sputtering, chemical solution deposition, or electroplating. The diffusion barrier layer may also comprise a two-layer structure comprising a lower layer of metal nitride, such as, for example, TaN, and an upper metal layer such as, for example, Ta.

The thickness of the diffusion barrier varies depending on the deposition process and the materials employed. Typically, the diffusion barrier has a thickness from about 4 nm to about 40 nm, more typically from about 7 nm to about 20 nm.

After the at least one conductive feature 204 is formed within the dielectric layer 202, a first dielectric cap layer 210 is formed over the initial interconnect structure 200 (FIG. 3). The first dielectric cap layer 210 is formed by a conventional deposition process such as, for example, CVD, PECVD, chemical solution deposition, or evaporation. The first dielectric cap layer 210 can be any suitable dielectric capping material including, but not limited to, SiC, Si ₄ NH ₃ , SiO ₂ , carbon doped oxide, nitrogen and hydrogen doped tantalum carbide (SiC (N , H)) or a multilayer structure of these. The thickness of the first dielectric cap layer 210 varies depending on the deposition process and the materials used. Typically, the thickness of the first dielectric cap layer 210 is from about 5 nm to about 80 nm, more typically from about 10 nm to about. 50 nm.

In FIG. 4, a portion of the first dielectric cap layer 210 is removed to expose the top end surface 208 of the conductive feature 204. A portion of the first dielectric cap layer 210 may be removed by photolithography, for example, a photoresist layer is applied over the surface of the first dielectric cap layer 210, the photoresist layer being exposed under the desired illumination pattern. The exposed photoresist layer is developed using a conventional photoresist developer. The patterned photoresist layer is used as an etch mask to remove a portion of the first dielectric cap layer 210. As shown in FIG. 4, after the portion is removed, the remaining first dielectric cap layer 210A does not substantially extend to the top end surface 208 of the conductive member 204, i.e., the top end surface 208 of the conductive member 204 within the interconnect structure. There is no or minimal first dielectric covering material 210.

Next, a metal cap layer 212 (FIG. 5) is selectively formed on the top end surface 208 of the conductive member 204. The metal cap layer 212 may be formed by CVD, PECVD, ALD, plasma enhanced atomic layer deposition (PEALD), electroplating process, or electroless plating process. Metal cover layer 212 can be any metal suitable for the present invention. The metal cap layer 212 is preferably Co, Ru, Ir, Rh, Pt, Ta, W, Mn, Mo, Ni, TaN, Ti, Al or an alloy containing two or more of the above metals. Typically the metal cap layer 212 has a thickness from about 1 nm to about 20 nm, more typically from about 2 nm to about 10 nm. As shown in FIG. 5, the metal cap layer 212 does not substantially extend to the top end surface 206 of the dielectric layer 202, i.e., there is no or minimal metal coverage on the top end surface 206 of the dielectric layer 202 within the interconnect structure. Material 212.

The metal cap layer 212 is thinner than the first dielectric cap layer 210. The thickness of the metal cap layer 212 is preferably about 50% or less of the thickness of the first dielectric cap layer 210, and the thickness of the metal cap layer 212 is more preferably about 20% or less of the thickness of the first dielectric cap layer 210. The metal cap layer 212 has a bottom surface 216 that is generally coplanar with the bottom surface 214 of the remaining first dielectric cap layer 210A.

During formation of the metal cap layer 212, a residue 218 of metal capping material may be formed on the remaining first dielectric cap layer 210A. As shown in FIG. 6, because the first dielectric cap layer 210A is thicker than the metal cap layer 212, the first dielectric cap layer 210A serves as a dielectric barrier between two adjacent metal caps 212a and 212b. As such, the first dielectric cap layer 210 interrupts the continuity between two adjacent conductive members 204a and 204b. This avoids a short circuit between two adjacent conductive members 204a and 204b. As a result, the interconnect structure of the present invention provides improved EM and TDDB reliability as compared to the conventional interconnect structure described above.

The cleaning step is performed as needed to remove residual metal cover material 218 to further avoid short circuits between adjacent conductive members. The cleaning step can be a wet cleaning step, a plasma cleaning step, or a touch grinding step. The wet cleaning step can use diluted HF or other acid that removes metal oxides. The plasma cleaning step may employ a plasma containing a noble gas or H ₂ . The touch grinding step can be a short-term chemical mechanical polishing (CMP) step.

In FIG. 7, a second dielectric cap layer 220 is formed on the remaining first dielectric cap layer 210A and metal cap layer 212. The second dielectric cap layer 220 is the same or different material as the first dielectric cap layer 210 , and the second dielectric cap layer 220 is preferably the same material as the first dielectric cap layer 210 . Examples of suitable materials that can be used as the second dielectric cap layer 220 include, but are not limited to, SiC, Si ₄ NH ₃ , SiO ₂ , carbon doped oxide, nitrogen and hydrogen doped tantalum carbide (SiC (N, H) )) or a multilayer structure of these. The second dielectric cap layer 220 is formed by a conventional deposition process such as, for example, CVD, PECVD, chemical solution deposition, or evaporation. The thickness of the second dielectric cap layer 220 varies depending on the deposition process and the materials used. Typically, the thickness of the second dielectric cap layer 220 is from about 5 nm to about 80 nm, more typically from about 10 nm to about. 50 nm. The second cap layer 220 is preferably in direct contact with the remaining first dielectric cap layer 210A and the metal cap layer 212.

If desired, the structure shown in FIG. 7 can be removed by a touch-up grinding step to remove a portion of the second dielectric cap layer 220 (element symbol 220A represents the ground second dielectric cap layer 220), and The flat wiring structure shown in FIG. 8 is provided. CMP and/or grinding methods can be used in this step of the invention.

The present invention has been particularly shown and described with reference to the preferred embodiments thereof. Therefore, the present invention is not limited by the scope of the invention and the details of the invention and the scope of the appended claims.

100. . . Inline structure

102. . . Dielectric layer

104. . . Conductive component

106. . . Metal cover

108. . . Dielectric overlay

110. . . Metal residue

200. . . Initial interconnect structure

202. . . Dielectric layer

204. . . Conductive component

206. . . Top surface

208. . . Top surface

210. . . First dielectric cover

210A. . . Remaining first dielectric cover

212. . . Metal cover

214. . . Bottom surface

216. . . Bottom surface

218. . . the remains

212a. . . Metal cover

212b. . . Metal cover

204a. . . Conductive component

204b. . . Conductive component

220. . . Second dielectric cover

220A. . . Second dielectric cover

The drawings are included to further understand the invention and are incorporated in and constitute a part of this specification. The drawings illustrate specific embodiments of the invention, and may be used to explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a prior art interconnect structure in which a metal cladding layer is provided on the top end of a conductive member.

2 through 8 are cross-sectional views illustrating exemplary method steps for fabricating an interconnect structure in accordance with an embodiment of the present invention.

It will be appreciated that for simplicity and clarity of illustration, the elements shown within the drawings are not necessarily to scale. For example, the dimensions of some of the elements may be more exaggerated than others for clarity.

202. . . Dielectric layer

204. . . Conductive component

210A. . . Remaining first dielectric cover

212. . . Metal cover

220A. . . Second dielectric cover

Claims (15)

An interconnect structure comprising: a dielectric layer having a conductive member embedded therein, the conductive member having a first top end surface substantially coplanar with a second top end surface of the dielectric layer; a metal cap layer Directly on the first top surface, wherein the metal cover layer does not extend substantially above the second top surface; a first dielectric cover layer directly on the second top surface, wherein the first a dielectric cap layer does not extend substantially above the first top end surface, and a top surface of the first dielectric cap layer is higher than a top end surface of the metal cap layer; and a second dielectric cap layer directly Located on the metal cover layer and the first dielectric cover layer; wherein the metal cover layer is composed of: i) a metal; or ii) a combination of metals; and wherein the metal cover layer has a substantially uniform composition distributed. The interconnect structure of claim 1, wherein the first dielectric cap layer has a thickness of from about 5 nm to about 80 nm, wherein the metal cap layer has a thickness of from about 1 nm to about 20 nm, or wherein the second dielectric layer The thickness of the electrical cover layer is from about 5 nm to about 80 nm. The interconnect structure of claim 1, wherein the second dielectric cover layer is in contact with the metal cover layer and the first dielectric cover layer, or wherein the metal cover layer has a bottom surface, substantially A bottom surface of the first dielectric cap layer is coplanar. The wiring structure of claim 1, wherein the metal coating layer is Co, Ru, Ir, Rh, Pt, Ta, W, Mn, Mo, Ni, TaN, Ti, Al or contains two or more of An alloy of the above metals, or wherein the first dielectric coating layer is SiN, SiC, Si ₄ NH ₃ , SiO ₂ , carbon doped oxide, nitrogen and hydrogen doped lanthanum carbide (SiC(N,H)) or Including two or more combinations of the above materials, or wherein the second dielectric coating layer is SiN, SiC, Si ₄ NH ₃ , SiO ₂ , carbon doped oxide, nitrogen and hydrogen doped tantalum carbide (SiC (N , H)) or comprising a combination of two or more of these materials. The interconnect structure of claim 1, wherein the dielectric layer has a dielectric constant of about 4.0 or less, or wherein the conductive member is Cu, Al, W, Ag, Ti, Ta, or the like An alloy of metal or other element. A method of forming an interconnect structure comprising: providing a dielectric layer having a conductive member embedded therein, the conductive member having a first top end surface substantially coplanar with a second top end surface of the dielectric layer Forming a first dielectric cap layer on the dielectric layer; removing a portion of the first dielectric cap layer to expose the first top end surface of the conductive member; selectively on the first top end surface of the conductive member Forming a metal cap layer, wherein a top end surface of the first dielectric cap layer is higher than a top end surface of the metal cap layer and does not extend substantially above the second top end surface; and directly on the first dielectric cap Forming a second dielectric cap layer on the layer and the metal cap layer, wherein the metal cap layer is composed of: i) a metal; or ii) a combination of metals; and wherein the metal cap layer has a substantially uniform Composition distribution. The method of claim 6, wherein the first dielectric cover layer has a thickness of from about 5 nm to about 80 nm, wherein the metal cover layer has a thickness of from about 1 From nm to about 20 nm, or wherein the thickness of the second dielectric cap layer is from about 5 nm to about 80 nm. The method of claim 6, wherein the second dielectric cover layer is in contact with the metal cover layer and the first dielectric cover layer, or wherein the metal cover layer has a bottom surface, substantially the first A bottom surface of the dielectric cap layer is coplanar. The method of claim 6, wherein the first dielectric cap layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition or evaporation, and wherein the first A dielectric cap layer is SiN, SiC, Si ₄ NH ₃ , SiO ₂ , carbon doped oxide, nitrogen and hydrogen doped lanthanum carbide (SiC(N,H)) or a combination comprising two or more of these materials . The method of claim 6, wherein the portion of the first dielectric cap layer is removed by photolithographic etching and RIE or wet etching. The method of claim 6, wherein the metal coating layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD). , an electroplating process or an electroless plating process, and wherein the metal cap layer is Co, Ru, Ir, Rh, Pt, Ta, W, Mn, Mo, Ni, TaN, Ti, Al or comprises two or more of these An alloy of the above metals. The method of claim 6, wherein the second dielectric cap layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition or evaporation, and wherein the first The two dielectric cap layers are SiN, SiC, Si ₄ NH ₃ , SiO ₂ , carbon doped oxide, nitrogen and hydrogen doped lanthanum carbide (SiC(N,H)) or a combination comprising two or more of these materials . The method of claim 6, wherein the dielectric layer has a dielectric constant of about 4.0 or less, or wherein the conductive member is Cu, Al, W, Ag, Ti, Ta, or comprises the aforementioned metal or other The alloy of the elements. The method of claim 6, further comprising, after forming the second dielectric cover layer and after forming the metal cover layer, using a wet cleaning step, a plasma cleaning step or a touch grinding step Remove residual metal covering material. The method of claim 6, further comprising removing a portion of the second dielectric cap layer by a touch grinding step after the forming the second dielectric cap layer.