TWI512753B - Sense amplifier and method for determining values of voltages on bit line pair - Google Patents

Description

Voltage interpretation method of sense amplifier and bit line pair

The present invention relates to the technical field of memory, and more particularly to a voltage sensing method for a memory sense amplifier and a bit line pair.

In the existing memory technology, some use an analog sense amplifier to perform signal amplification of a bit line pair. The analog sense amplifier has the advantage of fast operation speed. However, since the sense amplifier is implemented by a differential amplifier, the threshold voltage (Vth) of the transistor often occurs due to process problems (ie, The so-called mismatch problem) has the disadvantage that this sense amplifier has a voltage offset.

In addition, some memory technologies use digital sense amplifiers for signal amplification. However, the sense amplifiers of the factor bits need to operate in full swing mode, so they have the disadvantage of slow operation speed. .

The present invention provides a sense amplifier that operates at a fast speed and has a small voltage offset problem.

The invention further provides a voltage interpretation method for a bit line pair, which is suitable for use with the aforementioned sense amplifier.

The present invention provides a sense amplifier that includes a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line, and is configured to receive a first signal of a clock signal and a bit line to delay a clock signal according to a voltage level of the first voltage, thereby generating The first delay signal. The second delay chain is electrically connected to a complementary bit line, and is configured to receive the second voltage on the clock signal and the complementary bit line to delay the clock signal according to the voltage of the second voltage. According to the second delay signal.

The invention further provides a voltage interpretation method for a bit line pair, comprising the steps of: delaying a clock signal according to a voltage level of a first voltage on a bit line, thereby generating a first delay signal, and according to a complementary The voltage of the second voltage on the bit line is delayed by the clock signal to generate a second delay signal; and the first voltage and the first voltage are determined according to the phase relationship between the first delay signal and the second delay signal. The voltage magnitude of both voltages.

The present invention employs two delay chains to convert the magnitude of the voltage on the bit line and the complementary bit line to a phase delay, respectively. Therefore, the user only needs to determine the voltage level on the bit line and the complementary bit line according to the phase relationship between the first delay signal and the second delay signal. Since the voltage is larger, the delay is smaller. Therefore, when the phase of the first delay signal leads the phase of the second delay signal, it can be determined that the voltage on the bit line is greater than the voltage on the complementary bit line; When the phase of the delayed signal leads the phase of the first delayed signal, it can be determined that the voltage on the complementary bit line is greater than the voltage on the bit line.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 illustrates a sense amplifier in accordance with an embodiment of the present invention. The sense amplifier 110 is suitable for use in a memory such as a random access memory (RAM). Referring to FIG. 1 , the sense amplifier 110 is configured to electrically connect one bit line pair formed by the bit line 102 and the complementary bit line 104 . In this example, sense amplifier 110 includes delay chains 120 and 130, and each delay chain has an even number of inverters (as indicated by flags 122-132, 142-152).

The delay chain 120 is electrically connected to the bit line 102, and is configured to receive the clock signal CLK and the voltage V1 on the bit line 102 to delay the clock signal CLK according to the voltage of the voltage V1, thereby generating a delay signal. DS1. The delay chain 140 is electrically connected to the complementary bit line 104, and is configured to receive the clock signal CLK and the voltage V2 on the complementary bit line 104 to delay the clock signal CLK according to the voltage of the voltage V2. A delay signal DS2 is generated. In addition, in this example, each inverter receives the read enable signal EN for read control.

FIG. 2 illustrates one of the circuit architectures of the inverter in the delay chain 120. Referring to FIG. 2, the inverter 200 includes two P-type transistors (indicated by 202 and 204, respectively) and two N-type transistors (indicated by 206 and 208, respectively). One of the source/drain electrodes of the P-type transistor 202 is electrically connected to the power supply voltage VDD, and the gate of the P-type transistor 202 is used to receive the read enable signal EN. One source/drain of the P-type transistor 204 is electrically connected to another source/drain of the P-type transistor 202, and the gate of the P-type transistor 204 is used as an input terminal of the inverter 200 to receive input. The signal IN, and the other source/drain of the P-type transistor 204 is used as the output of the inverter 200 to provide the output signal OUT.

In addition, one source/drain of the N-type transistor 206 is electrically connected to another source/drain of the P-type transistor 204, and the gate of the N-type transistor 206 is electrically connected to the gate of the P-type transistor 204. . One source/drain of the N-type transistor 208 is electrically connected to another source/drain of the N-type transistor 206, and the gate of the N-type transistor 208 is used to receive the voltage V1 (ie, the voltage on the bit line 102). The other source/drain of the N-type transistor 208 is used to electrically connect the reference potential VSS. It can be seen from the circuit architecture shown in FIG. 2 that the larger the value of the voltage V1, the faster the charging and discharging speed of the potential of the output terminal of the inverter 200.

FIG. 3 illustrates one of the circuit architectures of the inverter in the delay chain 140. Referring to FIG. 3, the inverter 300 also includes two P-type transistors (indicated by 302 and 304, respectively) and two N-type transistors (labeled 306 and 308, respectively). As can be seen from FIG. 3, the circuit architecture of the inverter 300 is the same as that of the inverter 200, except that the gate of the N-type transistor 308 in the inverter 300 is used to receive the voltage V2 (ie, the complementary bit line). Voltage on 104). As can be seen from the circuit architecture shown in FIG. 3, when the value of the voltage V2 is larger, the charging and discharging speeds of the potential of the output terminal of the inverter 300 are faster.

Referring again to FIG. 1, since the charging and discharging speeds of the output terminals of each of the inverters in the delay chain 120 are determined according to the magnitude of the voltage V1, the charging and discharging of the output terminals of each of the inverter chains 140 are charged. The speed is determined according to the magnitude of the voltage V2. Therefore, if the magnitudes of the voltages V1 and V2 are different, the delay degree of the delay signal DS1 outputted by the delay chain 120 and the delay signal DS2 outputted by the delay chain 140 will be different. Therefore, the back-end circuit can determine whether the voltages V1 and V2 are small and small according to the delay degree of the two delay signals, which is illustrated by FIG.

FIG. 4 illustrates one of the timing relationships of the pulse signal CLK, the delay signal DS1, and the delay signal DS2. As shown, the delay signal DS1 is delayed by Td1, while the delayed signal DS2 is delayed by Td2. That is to say, the phase of the delay signal DS1 is advanced by the phase of the delay signal DS2. Since the degree of delay of each delay signal is inversely proportional to the magnitude of the voltage V1 or V2, it can be determined that the voltage V1 is greater than the voltage V2. On the other hand, if the phase of the delay signal DS2 is advanced by the phase of the delay signal DS1, it can be determined that the voltage V2 is greater than the voltage V1.

Since each of the above delay chains is composed of a plurality of inverters, even if the threshold voltage (Vth) of a certain transistor is different due to a process problem, the voltage offset problem will follow each delay chain. The number of inverters used is reduced by an increase in the number of inverters. Therefore, the voltage offset problem of the sense amplifier of the present invention is small compared to the conventional analog sense amplifier. In addition, since the inverter in each of the above delay chains adopts a low swing circuit structure, the sensing amplifier of the present invention operates faster than a conventional digital sense amplifier. .

The circuit architecture of the two low swing inverters will be further exemplified below. Referring to FIG. 5, another circuit architecture of the inverter in the delay chain 120 is illustrated. Referring to FIG. 5, the inverter 500 includes a P-type transistor (indicated by 502) and two N-type transistors (indicated by 504 and 506, respectively). One of the source/drain electrodes of the P-type transistor 502 is electrically connected to the power supply voltage VDD, and the gate of the P-type transistor 502 is used as an input terminal of the inverter 500 to receive the input signal IN, and the P-type power Another source/drain of crystal 502 is used as the output of inverter 500 to provide an output signal OUT. One source/drain of the N-type transistor 504 is electrically connected to another source/drain of the P-type transistor 502, and the gate of the N-type transistor 504 is electrically connected to the gate of the P-type transistor 502. One source/drain of the N-type transistor 506 is electrically connected to another source/drain of the N-type transistor 504, and the gate of the N-type transistor 506 is used to receive the voltage V1 (ie, the voltage on the bit line 102). The other source/drain of the N-type transistor 506 is used to electrically connect the reference potential VSS.

FIG. 6 illustrates another circuit architecture of the inverter in the delay chain 140. Referring to FIG. 6, the inverter 600 also includes a P-type transistor (indicated by 602) and two N-type transistors (indicated by 604 and 606, respectively). As can be seen from FIG. 6, the circuit structure of the inverter 600 is the same as that of the inverter 500, except that the gate of the N-type transistor 606 in the inverter 600 is used to receive the voltage V2 (ie, the complementary bit line). Voltage on 104).

FIG. 7 illustrates still another circuit architecture of the inverter in the delay chain 120. Referring to Figure 7, the inverter 700 includes two P-type transistors (indicated by 702 and 704) and an N-type transistor (labeled 706). One of the sources/drains of the P-type transistor 702 is used to electrically connect the power supply voltage VDD, and the gate of the P-type transistor 702 is used to receive the voltage V1 (ie, the voltage on the bit line 102). One source/drain of the P-type transistor 704 is electrically connected to another source/drain of the P-type transistor 702. The gate of the P-type transistor 704 serves as an input terminal of the inverter 700 to receive the input signal IN. The other source/drain of the P-type transistor 704 is used as an output of the inverter 700 to provide an output signal OUT. One source/drain of the N-type transistor 706 is electrically connected to another source/drain of the P-type transistor 704, and the gate of the N-type transistor 706 is electrically connected to the gate of the P-type transistor 704, and N The other source/drain of the type transistor 706 is used to electrically connect the reference potential VSS.

FIG. 8 illustrates yet another circuit architecture of the inverter in delay chain 140. Referring to Figure 8, the inverter 800 also includes two P-type transistors (labeled 802 and 804) and an N-type transistor (labeled 806). As can be seen from FIG. 8, the circuit architecture of the inverter 800 is the same as that of the inverter 700, except that the gate of the P-type transistor 802 in the inverter 800 is used to receive the voltage V2 (ie, the complementary bit line). Voltage on 104).

In addition, in order to avoid the same phase of the delay signal DS1 and the delay signal DS2, the back-end circuit cannot determine whether the voltage on the bit line 102 and the voltage on the complementary bit line 104 are large or small, and the designer can sense the voltage. A phase change detector is added to the amplifier to aid identification, as shown in Figure 9.

9 is a sense amplifier in accordance with another embodiment of the present invention. Referring to FIG. 9, the sense amplifier 900 includes a delay chain 910, a delay chain 920, and a phase change detector 930. The delay chain 910 is configured to delay the clock signal CLK according to the voltage level of the voltage V1 on a bit line (not shown), and accordingly generate the delay signal DS1. The delay chain 920 is configured to delay the clock signal CLK according to the voltage of the voltage V2 on a complementary bit line (not shown), and accordingly generate the delay signal DS2. As for the phase change detector 930, it has an initial operational phase and a sensing operational phase, wherein the sensing operational phase is after the initial operational phase. In the initial operation phase, the phase change detector 930 detects the order of the phases of the delay signals DS1 and DS2 and stores them as the first detection result. Therefore, the voltages of the voltages V1 and V2 can be made the same in this initial operation phase, so that the first detection result stored by the phase change detector 930 can reflect the difference in charging and discharging speed between the delay chains 910 and 920. .

After storing the first detection result, the phase change detector 930 can then be brought into the sensing operation phase, and the memory starts normal operation, so that the voltages V1 and V2 can respectively reflect the bit line (not shown). The voltage changes on the complementary bit line (not shown). In the sensing operation phase, the phase change detector 930 detects the sequence of the phases of the delay signals DS1 and DS2 and stores them as the second detection result. When the second detection result shows that the phases of the delay signals DS1 and DS2 are the same, the phase change detector 930 uses the output signals SAO and SAOB to output a result opposite to the first detection result; and when the second detection result is displayed When the phases of the delay signals DS1 and DS2 are different, the phase change detector 930 will use the output signals SAO and SAOB to output the second detection result. Further examples will be explained below.

It is assumed that the first detection result shows that the delay signal DS2 leads the delay signal DS1, indicating that the charging and discharging speed of the delay chain 920 is faster than the charging and discharging speed of the delay chain 910 when the voltages V1 and V2 are the same. Therefore, when the second detection result shows that the delay signals DS1 and DS2 are in phase, it means that the actual detection result should be opposite to the first detection result, so the phase change detector 930 uses the output signals SAO and SAOB to output and The result of the opposite detection result, that is, the output signal SAO and SAOB are used to output the delayed signal DS1 as the result of the leading delay signal DS2. When the second detection result shows that the phases of the delay signals DS1 and DS2 are different, it means that the actual detection result should be the same as the second detection result, so the phase change detector 930 will use the output signals SAO and SAOB. To output the second test result.

FIG. 10 illustrates one implementation of phase change detector 930. Referring to FIG. 10, the phase change detector 930 includes four D-type flip-flops (indicated by 932, 934, 936, and 938, respectively), a comparison circuit (indicated by 940), and two multiplexers ( Marked with 942 and 944 respectively). Each D-type flip-flop has a data input (marked by D), a data output (marked by Q), and a clock input (marked by a triangle). The data input terminal D of the D-type flip-flop 932 is used to receive the delay signal DS1, and the clock input terminal of the D-type flip-flop 932 is used to receive the delay signal DS2. The data input terminal D of the D-type flip-flop 934 is used to receive the delay signal DS2, and the clock input terminal of the D-type flip-flop 934 is used to receive the delay signal DS1. The data input terminal D of the D-type flip-flop 936 is used to receive the signal Qn outputted by the data output terminal Q of the D-type flip-flop 932, and the clock input terminal of the D-type flip-flop 936 is used to receive the initial setting signal INI. . This initial setting signal INI is used to determine whether the phase change detector 930 is in an initial operational phase or a sensing operational phase. The data input terminal D of the D-type flip-flop 938 is used to receive the signal Qbn outputted by the data output terminal Q of the D-type flip-flop 934, and the clock input terminal of the D-type flip-flop 938 is used to receive the initial setting signal INI. .

In addition, the multiplexer 942 is configured to receive the signals Qn and Qbi and output one of the signals Qn and Qbi according to the selection signal SEL. The multiplexer 944 is configured to receive the signals Qbn and Qi and output one of the signals Qbn and Qi according to the selection signal SEL. The comparison circuit 940 is configured to receive the signals Qn, Qbn, Qi, and Qbi, and compare whether the phases of the signals Qn and Qbn are the same, thereby outputting the selection signal SEL. When the comparison result is YES, the comparison circuit 940 conveniently controls the multiplexers 942 and 944 to output the signals Qbi and Qi respectively by the selection signal SEL to respectively output the signals SAO and SAOB of the phase change detector 930, and as the first detection. The result is the opposite of the output. When the comparison result is no, the comparison circuit 940 conveniently controls the multiplexers 942 and 944 to output the signals Qn and Qbn respectively by the selection signal SEL to respectively serve as the output signals SAO and SAOB of the phase change detector 930, and as the second detection. The result is output.

With the teachings of the above embodiments, there is a basic step in the art for a voltage interpretation method that can be generalized to a bit line pair, as shown in FIG. Referring to FIG. 11, the voltage reading method includes: delaying a clock signal according to a voltage level of a first voltage on a bit line, thereby generating a first delay signal, and according to a second voltage on a complementary bit line The voltage level is used to delay the clock signal to generate a second delay signal (as shown in step S1102); and to determine the first voltage and the first phase according to the phase relationship between the first delay signal and the second delay signal. The voltage magnitude of both voltages (as shown in step S1104).

The voltage interpretation method may further include the following steps: when determining that the phase of the first delay signal leads the phase of the second delay signal, determining that the first voltage system is greater than the second voltage, and determining the phase of the second delay signal When the phase of the first delay signal is advanced, it is determined that the second voltage system is greater than the first voltage.

In summary, the present invention employs two delay chains to convert the magnitudes of the voltages on the bit lines and the complementary bit lines into phase delays, respectively. Therefore, the user only needs to determine the voltage level on the bit line and the complementary bit line according to the phase relationship between the first delay signal and the second delay signal. Since the voltage is larger, the delay is smaller. Therefore, when the phase of the first delay signal leads the phase of the second delay signal, it can be determined that the voltage on the bit line is greater than the voltage on the complementary bit line; When the phase of the delayed signal leads the phase of the first delayed signal, it can be determined that the voltage on the complementary bit line is greater than the voltage on the bit line.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102. . . Bit line

104. . . Complementary bit line

110, 900. . . Sense amplifier

120, 140, 910, 920. . . Delay chain

122~132, 142~152, 200, 300, 500, 600, 700, 800. . . inverter

202, 204, 302, 304, 502, 602, 702, 704, 802, 804. . . P-type transistor

206, 208, 306, 308, 504, 506, 604, 606, 706, 806. . . N type transistor

930. . . Phase change detector

932, 934, 936, 938. . . D-type flip-flop

940. . . Comparison circuit

942, 944. . . Multiplexer

CLK. . . Clock signal

DS1, DS2. . . Delay signal

EN. . . Read enable signal

IN. . . Inverter input signal

INI. . . Initial setting signal

OUT. . . Inverter output signal

SAO, SAOB. . . Phase change detector output signal

Td1. . . Delay time of delay signal DS1

Td2. . . Delay time of delay signal DS2

V1. . . Voltage on bit line 102

V2. . . Voltage on complementary bit line 104

VDD. . . voltage

SEL. . . Select signal

VSS. . . Reference potential

Qn, Qbn, Qi, Qbi. . . Signal output by D-type flip-flop

D. . . Data input terminal of D-type flip-flop

Q. . . Data output of D-type flip-flop

R. . . Reset end of D-type flip-flop

S1102, S1104. . . step

1 illustrates a sense amplifier in accordance with an embodiment of the present invention.

FIG. 2 illustrates one of the circuit architectures of the inverter in the delay chain 120.

FIG. 3 illustrates one of the circuit architectures of the inverter in the delay chain 140.

FIG. 4 illustrates one of the timing relationships of the pulse signal CLK, the delay signal DS1, and the delay signal DS2.

FIG. 5 illustrates another circuit architecture of the inverter in the delay chain 120.

FIG. 6 illustrates another circuit architecture of the inverter in the delay chain 140.

FIG. 7 illustrates still another circuit architecture of the inverter in the delay chain 120.

FIG. 8 illustrates yet another circuit architecture of the inverter in delay chain 140.

9 is a sense amplifier in accordance with another embodiment of the present invention.

FIG. 10 illustrates one implementation of phase change detector 930.

Figure 11 is a diagram showing the basic steps of a voltage interpretation method for bit line pairs in accordance with an embodiment of the present invention.

102. . . Bit line

104. . . Complementary bit line

110. . . Sense amplifier

120, 140. . . Delay chain

122~132, 142~152. . . inverter

CLK. . . Clock signal

DS1, DS2. . . Delay signal

EN. . . Read enable signal

V1. . . Voltage on bit line 102

V2. . . Voltage on complementary bit line 104

Claims (12)

A sense amplifier includes: a first delay chain electrically connected to a bit line, and configured to receive a clock signal and a first voltage on the bit line to depend on a voltage of the first voltage Delaying the clock signal to generate a first delay signal; and a second delay chain for electrically connecting a complementary bit line and for receiving the clock signal and the second of the complementary bit line The voltage is delayed by the clock signal according to the voltage of the second voltage, thereby generating a second delay signal. A sense amplifier as claimed in claim 1 wherein each delay chain has an even number of inverters. The sense amplifier of claim 2, wherein each of the first delay chains comprises: a first P-type transistor, wherein a source/drain is electrically connected to a power source. a voltage, and a gate thereof for receiving a read enable signal; a second P-type transistor, wherein a source/drain is electrically connected to another source/drain of the first P-type transistor, and the gate thereof The pole is used as the input end of the inverter, and the other source/drain is used as the output end of the inverter; a first N-type transistor, one source/drain is electrically connected to the second P-type transistor Another source/drain, wherein the gate is electrically connected to the gate of the second P-type transistor; and a second N-type transistor, wherein a source/drain is electrically connected to the first N-type transistor The other source/drain has a gate for receiving the first voltage and another source/drain for electrically connecting to a reference potential. The sense amplifier of claim 3, wherein each of the second delay chains comprises: a first P-type transistor, wherein a source/drain is electrically connected to the power source. a voltage, and a gate thereof for receiving the read enable signal; a second P-type transistor, wherein a source/drain is electrically connected to another source/drain of the first P-type transistor, and the gate thereof The pole is used as the input end of the inverter, and the other source/drain is used as the output end of the inverter; a first N-type transistor, one source/drain is electrically connected to the second P-type transistor Another source/drain, wherein the gate is electrically connected to the gate of the second P-type transistor; and a second N-type transistor, wherein a source/drain is electrically connected to the first N-type transistor The other source/drain is configured to receive the second voltage and another source/drain for electrically connecting the reference potential. The sense amplifier of claim 2, wherein each of the first delay chains comprises: a P-type transistor, wherein a source/drain is electrically connected to a power supply voltage, The gate is used as the input end of the inverter, and the other source/drain is used as the output end of the inverter; a first N-type transistor, one source/drain is electrically connected to the P-type transistor Another source/drain, wherein the gate is electrically connected to the gate of the P-type transistor; and a second N-type transistor, wherein a source/drain is electrically connected to the first N-type transistor A source/drain has a gate for receiving the first voltage and another source/drain for electrically connecting to a reference potential. The sense amplifier of claim 5, wherein each of the second delay chains comprises: a P-type transistor, wherein a source/drain is electrically connected to the power supply voltage, The gate is used as the input end of the inverter, and the other source/drain is used as the output end of the inverter; a first N-type transistor, one source/drain is electrically connected to the P-type transistor Another source/drain, wherein the gate is electrically connected to the gate of the P-type transistor; and a second N-type transistor, wherein a source/drain is electrically connected to the first N-type transistor A source/drain has a gate for receiving the second voltage and another source/drain for electrically connecting the reference potential. The sense amplifier of claim 2, wherein each of the first delay chains comprises: a first P-type transistor, wherein a source/drain is electrically connected to a power source. a voltage, and a gate thereof receives the first voltage; a second P-type transistor, a source/drain is electrically connected to another source/drain of the first P-type transistor, and the gate thereof is inverted The input of the device, and the other source/drain as the output of the inverter; and an N-type transistor, one source/drain is electrically connected to another source of the second P-type transistor The gate is electrically connected to the gate of the second P-type transistor, and the other source/drain is electrically connected to a reference potential. The sense amplifier of claim 7, wherein each of the second delay chains comprises: a first P-type transistor, wherein a source/drain is electrically connected to the power supply voltage, and a gate thereof receives the second voltage; and a second P-type transistor is electrically connected to a source/drain Another source/drain of the first P-type transistor has a gate as an input of the inverter and another source/drain as an output of the inverter; and an N-type transistor, One source/drain is electrically connected to another source/drain of the second P-type transistor, and the gate is electrically connected to the gate of the second P-type transistor, and the other source/drain is used The reference potential is electrically connected. The sense amplifier of claim 2, further comprising a phase change detector having an initial operation phase and a sensing operation phase, the sensing operation phase being after the initial operation phase And in the initial operation phase, the phase change detector detects the sequence of the phase of the first delay signal and the second delay signal, and stores the first detection result according to the first detection result, and in the sensing operation phase The phase change detector detects the sequence of the phase of the first delay signal and the second delay signal, and stores the result as a second detection result, and when the second detection result displays the first delay signal When the phase of the second delay signal is the same, the phase change detector outputs a result opposite to the first detection result, and when the second detection result shows the phase of the first delay signal and the second delay signal In the case of not being the same, the phase change detector outputs the second detection result. The sense amplifier of claim 9, wherein the phase change detector comprises: a first D-type flip-flop having a first data input, a first data output, and a first time a pulse input end, the first data input end is configured to receive the a first delay signal, wherein the first clock input is configured to receive the second delay signal; and a second D-type flip-flop has a second data input end, a second data output end, and a second time a second data input terminal for receiving the second delay signal, wherein the second clock input terminal is configured to receive the first delay signal; and a third D-type flip-flop device having a third data source An input end, a third data output end and a third clock input end, wherein the third data input end is configured to receive the signal output by the first data output end, and the third clock input end is configured to receive a signal An initial setting signal, the initial setting signal is used to determine that the phase change detector is in the initial operation phase or the sensing operation phase; a fourth D-type flip-flop has a fourth data input terminal and a fourth data output And a fourth clock input end, the fourth data input end is configured to receive the signal output by the second data output end, and the fourth clock input end is configured to receive the initial setting signal; a device for receiving the first data output end The output signal and the signal output by the fourth data output end, and output one of the signal output by the first data output end and the signal output by the fourth data output end according to a selection signal; a second multiplexer for receiving the signal output by the second data output end and the signal output by the third data output end, and outputting the signal output by the second data output end according to the selection signal and the third One of the signals outputted by the data output terminal; and a comparison circuit for receiving the signal output by the first data output terminal, the signal output by the second data output terminal, and the third data output terminal The output signal and the signal output by the fourth data output are used to compare the first capital Whether the phase outputted by the output end of the signal and the signal outputted by the second data output end are the same, according to which the selection signal is output, and when the comparison result is yes, the comparison circuit controls the first use of the selection signal a multiplexer and the second multiplexer respectively output a signal output by the fourth data output terminal and a signal output by the third data output terminal to output as a result opposite to the first detection result, and When the comparison result is no, the comparison circuit controls the first multiplexer and the second multiplexer to output the signal output by the first data output end and the second data output end respectively by using the selection signal. The signal is output as the second detection result. A voltage interpretation method for a bit line pair includes: delaying a clock signal according to a voltage level of a first voltage on a bit line, thereby generating a first delay signal, and according to one of the complementary bit lines The voltage of the two voltages delays the clock signal to generate a second delay signal; and determines the first voltage and the second voltage according to a phase relationship between the first delay signal and the second delay signal The voltage of both. The voltage interpretation method of claim 11, wherein when determining that the phase of the first delay signal is ahead of the phase of the second delay signal, determining that the first voltage system is greater than the second voltage When it is determined that the phase of the second delay signal is ahead of the phase of the first delay signal, it is determined that the second voltage system is greater than the first voltage.