TWI510927B - A server system - Google Patents
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- TWI510927B TWI510927B TW102141703A TW102141703A TWI510927B TW I510927 B TWI510927 B TW I510927B TW 102141703 A TW102141703 A TW 102141703A TW 102141703 A TW102141703 A TW 102141703A TW I510927 B TWI510927 B TW I510927B
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Description
本發明是有關於伺服器系統,且特別是有關於一種可在I2C匯流排中進行從電子器件選擇之伺服器系統。This invention relates to servo systems, and more particularly to a server system that can be selected from an electronic device in an I2C bus.
一般伺服器系統中除了使用平行匯流排(Parallel Bus)之外,還有串列匯流排。而其中一種串列匯流排(I2C匯流排)已非常地普遍被設計於伺服器系統中。In addition to the parallel bus (Parallel Bus), there are serial bus bars in the general server system. One of the serial busbars (I2C busbars) has been very commonly designed in server systems.
I2C為Inter-Integrated Circuit的縮寫,顧名思義,就是積體電路(Integrated Circuit)之間溝通的匯流排。傳統的平行匯流排因採用平行的架構(8位元、16位元等等),所以積體電路之間的接線較多,且需要解碼電路,而顯得複雜。而I2C匯流排只需要兩條線就能傳送資料,因此具有更佳的可靠度與安全性。此外,I2C匯流排還可容許一從積體電路上有多個主積體電路。因此,如何正確將從積體電路與主積體電路連接即成為追求之目標。I2C is the abbreviation of Inter-Integrated Circuit. As the name suggests, it is the bus that communicates between the integrated circuits. Conventional parallel busbars use parallel architectures (8-bit, 16-bit, etc.), so there is more wiring between the integrated circuits and it is necessary to decode the circuits, which is complicated. The I2C bus line only needs two lines to transmit data, so it has better reliability and security. In addition, the I2C bus bar can also allow a plurality of main body circuits on a slave circuit. Therefore, how to correctly connect the integrated circuit from the main integrated circuit becomes the goal.
鑑於上述,本發明提供一種可在I2C匯流排中選擇 特定從電子器件實現不同功能之伺服器系統。In view of the above, the present invention provides a choice in an I2C bus A server system that implements different functions from an electronic device.
本發明之一態樣係在提供一種伺服器系統,至少包含一基板管理控制器和多個個運算模組。每一運算模組更包括一系統級晶片、多個從電子器件和一切換器。切換器,分別通過I2C匯流排耦接該基板管理控制器與該系統級晶片,以及該複數個從電子器件。其中,對每一運算模組,切換器發出一地址選擇信號至此些個從電子器件,以選擇從電子器件其中之一連接切換器,切換器根據一控制信號切換基板管理控制器與系統級晶片耦接從電子器件其中之一。One aspect of the present invention provides a server system including at least a substrate management controller and a plurality of computing modules. Each computing module further includes a system level chip, a plurality of slave devices, and a switch. The switch is coupled to the baseboard management controller and the system level chip through the I2C busbar, and the plurality of slave devices. Wherein, for each computing module, the switch sends an address selection signal to the slave devices to select one of the slave switches, and the switch switches the substrate management controller and the system level chip according to a control signal. Coupling one of the slave electronics.
在一實施例中,從電子器件為一記憶體,該基板管理控制器與該系統級晶片通過該切換器分別接收該記憶體之配置資訊。In one embodiment, the slave electronic device is a memory, and the baseboard management controller and the system-level chip respectively receive configuration information of the memory through the switch.
在一實施例中,從電子器件為一網絡晶片,該基板管理控制器監測該網路晶片之溫度,並可由該切換器切換該系統及晶片讀取該網路晶片之溫度。In one embodiment, the slave electronic device is a network chip, the substrate management controller monitors the temperature of the network chip, and the switch can switch the system and the temperature at which the wafer reads the network chip.
在一實施例中,從電子器件為一電壓調節器,該電壓調節器為該系統級晶片供電且由該系統級晶片讀取其電壓,並可由該切換器切換該基板管理控制器監測該電壓調節器之溫度。In one embodiment, the slave electronic device is a voltage regulator that supplies power to the system level chip and reads its voltage from the system level chip, and the switch can switch the substrate management controller to monitor the voltage. The temperature of the regulator.
在一實施例中,基板管理控制器透過一多工器和該複數個運算模組耦接。In one embodiment, the substrate management controller is coupled to the plurality of computing modules through a multiplexer.
在一實施例中,切換器為一多工器。In an embodiment, the switch is a multiplexer.
在一實施例中,基板管理控制器或該系統級晶片發 出該位址選擇訊號給該切換器。In an embodiment, the substrate management controller or the system level chip The address selection signal is sent to the switch.
綜上所述,本發明提供一切換器可在多個從電子器件中選擇其一來和主元件耦接,因此可實現不同之功能。In summary, the present invention provides a switch that can select one of a plurality of slave devices to be coupled to the master device, thereby implementing different functions.
100‧‧‧伺服器系統100‧‧‧Server system
101‧‧‧基板管理控制器101‧‧‧Base Management Controller
102‧‧‧系統級晶片102‧‧‧System level wafer
103‧‧‧記憶體103‧‧‧ memory
104‧‧‧電壓調節器104‧‧‧Voltage regulator
105‧‧‧網路晶片105‧‧‧Network Chip
106‧‧‧切換器106‧‧‧Switcher
107‧‧‧多工器107‧‧‧Multiplexer
110和112‧‧‧運算模組110 and 112‧‧‧ computing modules
301和302‧‧‧步驟301 and 302‧‧ steps
第1圖所示為伺服器系統概略圖。Figure 1 shows a schematic diagram of the server system.
第2圖所示為根據本發明一實施例的伺服器系統概略圖。2 is a schematic diagram of a server system in accordance with an embodiment of the present invention.
第3圖所示為在一I2C匯流排中選擇一從電子器件之切換方法。Figure 3 shows a method of switching a slave electronic device in an I2C bus.
以下為本發明較佳具體實施例以所附圖示加以詳細說明,下列之說明及圖示使用相同之參考數字以表示相同或類似元件,並且在重複描述相同或類似元件時則予省略。The following description of the preferred embodiments of the invention is in the
第1圖所示為伺服器系統概略圖。伺服器系統100包括一基板管理控制器(Baseboard Management Controller,BMC)101以及複數個運算模組110,每一運算模組110包括一系統級晶片(System-on-chip,SOC)102以及多個從電子器件,包括一記憶體103、一電壓調節器104以及一網路晶片105。其中記憶體103、電壓調節器104以及網路晶片105是透過I2C匯流排耦接系統級晶片102。而記憶體103儲存 控制開機與基本輸出入的BIOS韌體。電壓調節器104用以提供系統級晶片102之核心電壓。網路晶片105用以提供系統級晶片102連接網路之用。Figure 1 shows a schematic diagram of the server system. The server system 100 includes a baseboard management controller (BMC) 101 and a plurality of computing modules 110. Each computing module 110 includes a system-on-chip (SOC) 102 and a plurality of The slave device includes a memory 103, a voltage regulator 104, and a network chip 105. The memory 103, the voltage regulator 104, and the network chip 105 are coupled to the system level wafer 102 through the I2C bus. Memory 103 is stored Controls the boot and basic output of the BIOS firmware. Voltage regulator 104 is used to provide the core voltage of system level wafer 102. The network chip 105 is used to provide a system level chip 102 for connecting to the network.
當進行開機操作時,系統級晶片102需使用記憶體103中儲存之基本輸出入的韌體以進行開機,此時記憶體103為I2C匯流排之從電子器件,而系統級晶片102則為I2C匯流排之主元件。而在待開機時,基板管理控制器101亦須存取記憶體103之型式以管理後續開機程序,此時記憶體103為I2C匯流排之從電子器件,而基板管理控制器101則為I2C匯流排之主元件。此外,當電壓調節器104提供系統級晶片102核心電壓時,系統級晶片102可透過I2C匯流排獲取電壓調節器104之參數值,此時電壓調節器104作為I2C匯流排之從電子器件,而系統級晶片102則為I2C匯流排之主元件。而基板管理控制器101則需監測電壓調節器104之溫度進行後續管理,此時電壓調節器104為I2C匯流排之從電子器件,而基板管理控制器101則為I2C匯流排之主元件。另一方面,當網路晶片105正常工作時,系統級晶片102透過I2C匯流排讀取溫度以及其他參數,此時網路晶片105為I2C匯流排之從電子器件,而系統級晶片102則為I2C匯流排之主元件。同時,基板管理控制器101監測溫度進行後續管理,此時網路晶片105為I2C匯流排之從電子器件,而基板管理控制器101則為I2C匯流排之主元件。換言之,在I2C匯流排之架構下,記憶體103、電壓調節器104以及網路晶片105均可作為基板管理 控制器101或系統級晶片102之從電子器件來進行不同之操作。When the booting operation is performed, the system level chip 102 needs to use the basic input and output firmware stored in the memory 103 to be turned on. At this time, the memory 103 is the slave device of the I2C bus, and the system level chip 102 is the I2C. The main component of the bus. When the device is to be powered on, the substrate management controller 101 also needs to access the type of the memory 103 to manage the subsequent booting process. At this time, the memory 103 is the slave device of the I2C bus, and the substrate management controller 101 is the I2C sink. The main component of the row. In addition, when the voltage regulator 104 provides the system-level chip 102 core voltage, the system-level chip 102 can obtain the parameter value of the voltage regulator 104 through the I2C bus bar, at which time the voltage regulator 104 acts as the slave device of the I2C bus. System level wafer 102 is the primary component of the I2C bus. The substrate management controller 101 needs to monitor the temperature of the voltage regulator 104 for subsequent management. At this time, the voltage regulator 104 is the slave device of the I2C bus, and the substrate management controller 101 is the main component of the I2C bus. On the other hand, when the network chip 105 is operating normally, the system level chip 102 reads the temperature and other parameters through the I2C bus bar. At this time, the network chip 105 is the slave device of the I2C bus, and the system level chip 102 is The main component of the I2C bus. At the same time, the substrate management controller 101 monitors the temperature for subsequent management. At this time, the network chip 105 is the slave device of the I2C bus, and the substrate management controller 101 is the main component of the I2C bus. In other words, under the architecture of the I2C bus, the memory 103, the voltage regulator 104, and the network chip 105 can be used as the substrate management. The controller 101 or the system level wafer 102 performs different operations from the electronics.
因此,為實現不同之功能,如第2圖所示為根據本發明一實施例的伺服器系統概略圖。本發明伺服器系統100包括一基板管理控制器101以及複數個運算模組112,每一運算模組112包括:一系統級晶片102、一切換器106以及多個從電子器件。從電子器件,包括一記憶體103、一電壓調節器104以及一網路晶片105。其中,切換器106,分別通過I2C匯流排耦接基板管理控制器101與系統級晶片102,以及記憶體103、電壓調節器104和網路晶片105。 換言之,記憶體103、電壓調節器104以及網路晶片105均透過該切換器106來耦接基板管理控制器101以及系統級晶片102。透過切換器106可選擇基板管理控制器101以及系統級晶片102其中之一耦接記憶體103、電壓調節器104或網路晶片105藉以實現不同功能。在一實施例中,切換器106會發出一地址選擇信號至記憶體103、電壓調節器104以及網路晶片105,以選擇記憶體103、電壓調節器104以及網路晶片105其中之一連接切換器106。切換器106並根據一控制信號切換基板管理控制器101與系統級晶片102耦接記憶體103、電壓調節器104以及網路晶片105其中之一。例如,若透過切換器106選擇電壓調節器104,此時電壓調節器104為系統級晶片102供電且由系統級晶片102讀取其電壓,並可由切換器106切換基板管理控制器101監測電壓調節器104之溫度。亦或是,透過切換器106 選擇記憶體103,此時基板管理控制器101與系統級晶片102通過切換器106分別接收記憶體103之配置資訊。亦或是,透過切換器106選擇網絡晶片105,此時基板管理控制器101監測網路晶片105之溫度,並可由切換器106切換系統級晶片102讀取網路晶片105之溫度。在一實施例中,切換器106,例如為一多工器,可根據基板管理控制器101或系統級晶片102發出之地址信號讓基板管理控制器101以及系統級晶片102其中之一耦接記憶體103、電壓調節器104或網路晶片105。此外在基板管理控制器101和此些運算模組112間可設置一多工器107,藉以提供基板管理控制器101選擇此些運算模組112其中之一耦接以進行後續之操作。Therefore, in order to realize different functions, FIG. 2 is a schematic diagram of a server system according to an embodiment of the present invention. The server system 100 includes a substrate management controller 101 and a plurality of computing modules 112. Each computing module 112 includes a system level chip 102, a switch 106, and a plurality of slave devices. The slave device includes a memory 103, a voltage regulator 104, and a network chip 105. The switch 106 is coupled to the baseboard management controller 101 and the system level chip 102, and the memory 103, the voltage regulator 104, and the network chip 105 through the I2C bus bar. In other words, the memory 103, the voltage regulator 104, and the network chip 105 are coupled to the substrate management controller 101 and the system level chip 102 through the switch 106. One of the substrate management controller 101 and the system level chip 102 can be selected by the switch 106 to couple the memory 103, the voltage regulator 104 or the network chip 105 to implement different functions. In one embodiment, the switch 106 sends an address selection signal to the memory 103, the voltage regulator 104, and the network chip 105 to select one of the memory 103, the voltage regulator 104, and the network chip 105. 106. The switch 106 switches the substrate management controller 101 and the system level chip 102 to one of the memory 103, the voltage regulator 104, and the network chip 105 according to a control signal. For example, if the voltage regulator 104 is selected by the switch 106, the voltage regulator 104 supplies power to the system level wafer 102 and its voltage is read by the system level wafer 102, and can be switched by the switch 106 to monitor the voltage regulation by the substrate management controller 101. The temperature of the device 104. Or, through the switch 106 The memory 103 is selected. At this time, the substrate management controller 101 and the system level chip 102 respectively receive the configuration information of the memory 103 through the switch 106. Alternatively, the network chip 105 is selected by the switch 106, at which time the substrate management controller 101 monitors the temperature of the network wafer 105, and the switch 106 switches the system level wafer 102 to read the temperature of the network wafer 105. In one embodiment, the switch 106, for example, a multiplexer, can couple one of the substrate management controller 101 and the system level chip 102 according to an address signal sent from the substrate management controller 101 or the system level chip 102. Body 103, voltage regulator 104 or network wafer 105. In addition, a multiplexer 107 can be disposed between the substrate management controller 101 and the computing modules 112 to provide the substrate management controller 101 to select one of the computing modules 112 for subsequent operations.
第3圖所示為在一I2C匯流排中選擇一從電子器件之切換方法,請同時參閱第2圖與第3圖。其中,在一I2C匯流排中具有記憶體103、電壓調節器104以及網路晶片105等多個從電子器件,以及基板管理控制器101以及系統級晶片102等至少二主元件。首先於步驟301,在一I2C匯流排上耦接一切換器。例如,設置一切換器106,使得記憶體103、電壓調節器104以及網路晶片105均透過該切換器106來耦接基板管理控制器101以及系統級晶片102。接著於步驟302,控制該切換器從該至少二主元件選擇其一來和該些從電子器件耦接。例如,控制切換器106選擇基板管理控制器101以及系統級晶片102其中之一來耦接記憶體103、電壓調節器104或網路晶片105,實現一特定功能。Figure 3 shows how to select a slave electronic device in an I2C bus. Please refer to Figure 2 and Figure 3. The I2C bus bar has at least two main components such as a plurality of slave electronic devices such as a memory 103, a voltage regulator 104, and a network chip 105, and a substrate management controller 101 and a system-level wafer 102. First, in step 301, a switch is coupled to an I2C bus. For example, a switch 106 is provided such that the memory 103, the voltage regulator 104, and the network chip 105 are coupled to the substrate management controller 101 and the system level chip 102 through the switch 106. Next, in step 302, the switch is controlled to select one of the at least two main components to be coupled to the slave electronic devices. For example, the control switch 106 selects one of the substrate management controller 101 and the system level chip 102 to couple the memory 103, the voltage regulator 104, or the network chip 105 to achieve a particular function.
綜上所述,本發明提供一切換器可在至少兩個主元件中選擇其一來和從電子器件耦接,因此可實現不同之功能。且可根據需求切換不同之從電子器件,在使用上更為方便。In summary, the present invention provides a switch that can select one of at least two main components and be coupled from an electronic device, thereby implementing different functions. Moreover, different slave electronic devices can be switched according to requirements, which is more convenient to use.
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
100‧‧‧伺服器系統100‧‧‧Server system
101‧‧‧基板管理控制器101‧‧‧Base Management Controller
102‧‧‧系統級晶片102‧‧‧System level wafer
103‧‧‧記憶體103‧‧‧ memory
104‧‧‧電壓調節器104‧‧‧Voltage regulator
105‧‧‧網路晶片105‧‧‧Network Chip
106‧‧‧切換器106‧‧‧Switcher
107‧‧‧多工器107‧‧‧Multiplexer
112‧‧‧運算模組112‧‧‧ Computing Module
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Citations (4)
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TW200725294A (en) * | 2005-12-28 | 2007-07-01 | Inventec Corp | Data transmission system applied in an electronic apparatus with multiple servo units |
TW201216079A (en) * | 2010-10-06 | 2012-04-16 | Inventec Corp | Server system and method for using shared baseboard management controller |
US20130067134A1 (en) * | 2011-09-13 | 2013-03-14 | International Business Machines Corporation | Pseudo multi-master i2c operation in a blade server chassis |
US20130201316A1 (en) * | 2012-01-09 | 2013-08-08 | May Patents Ltd. | System and method for server based control |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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TW200725294A (en) * | 2005-12-28 | 2007-07-01 | Inventec Corp | Data transmission system applied in an electronic apparatus with multiple servo units |
TW201216079A (en) * | 2010-10-06 | 2012-04-16 | Inventec Corp | Server system and method for using shared baseboard management controller |
US20130067134A1 (en) * | 2011-09-13 | 2013-03-14 | International Business Machines Corporation | Pseudo multi-master i2c operation in a blade server chassis |
US20130201316A1 (en) * | 2012-01-09 | 2013-08-08 | May Patents Ltd. | System and method for server based control |
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