TWI508250B - Memory cell structures - Google Patents

Description

Memory cell structure

The present invention relates generally to semiconductor memory devices and methods, and more particularly to memory cell structures and methods of forming the same.

The memory device is typically configured as an internal semiconductor integrated circuit in a computer or other electronic device. There are many different types of memory, including, in particular, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), fast Flash memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM; also Called magnetic random access memory), conductive bridged random access memory (CBRAM).

The memory device is used as a non-volatile memory for a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memory can be used especially in a personal computer, a portable memory card, a solid state drive (SSD), a PDA, a digital camera, a cellular phone, a portable music player. (such as MP3 players) and a movie player and other electronic devices. Code and system data, such as a basic input/output system (BIOS), are typically stored in a non-volatile memory device.

For example, many memory devices (such as RRAM, PCRAM, MRAM, STTRAM, and CBRAM) can be organized into, for example, a two-terminal cross-point architecture. A memory cell array. The memory cell array in the two-terminal cross-point architecture can include electrodes having a flat surface between the memory cell materials. For a filament-like memory device (such as RRAM and/or CBRAM), the location of the active region of the memory cell between the flat surfaces of the electrodes is variable because the flat surface of the electrode provides material across the memory cell. A substantially uniform electric field.

The present invention encompasses memory cell structures and methods of forming the same. The memory unit includes: a first electrode having a sidewall at an angle of less than 90 degrees with respect to a bottom surface of the first electrode; and a second electrode including an electrode contact portion of the second electrode, the electrode The contact portion has a sidewall at an angle of less than 90 degrees with respect to the bottom surface of the first electrode, wherein the second electrode is above the first electrode; and a storage element interposed between the first electrode and the second electrode The electrode contacts between the portions.

In one or more embodiments, a memory cell (having: a first electrode having sidewalls at an angle of less than 90 degrees with respect to a bottom surface of the first electrode; and an electrode contact portion of a second electrode The electrode contact portion has a sidewall having an angle of less than 90 degrees with respect to the bottom surface of the first electrode, and the fibril nucleation position thereof is positioned at one of the first electrode and the electrode of the second electrode Contact one of the points between the points.

BRIEF DESCRIPTION OF THE DRAWINGS In the following detailed description of the invention, reference to the drawings These embodiments are described in sufficient detail to enable the general practitioner to The embodiments of the present invention are to be construed as being illustrative, and other embodiments may be utilized, and may be

As used herein, "a plurality of" items may mean one or more of such items. For example, many memory devices may mean one or more memory devices. In addition, as used herein, the designations "N" and "M", particularly with respect to the component symbols, indicate that the various embodiments of the invention may include a specified number of specific features.

Herein, the drawings follow a numbering convention in which the first digit or the first digits correspond to the schema numbering and the remaining digits identify one of the elements or components in the drawing. Similar numbers may be used to identify similar elements or components between different figures. For example, 208 may refer to element "08" in FIG. 2 and one of the similar elements in FIG. 3 may be labeled 308. It will be appreciated that elements shown in the various embodiments herein can be added, exchanged, and/or eliminated to provide numerous additional embodiments of the invention. In addition, it should be understood that the proportions and relative dimensions of the elements of the present invention are intended to illustrate embodiments of the invention and are not to be considered as limiting.

1 is a block diagram showing a portion of a memory cell array 100. In the example illustrated in FIG. 1, array 100 is an array of intersections comprising: a first number of conductive lines 130-0, 130-1, . . ., 130-N (eg, access lines), Etc. may be referred to herein as a word line; and a second number of conductive lines 120-0, 120-1, ..., 120-M (eg, data lines), which may be referred to herein as bit elements. line. As depicted, word lines 130-0, 130-1, ..., 130-N are substantially parallel to each other and substantially orthogonal to each other substantially Parallel bit lines 120-0, 120-1, ..., 120-M; however, embodiments are not limited thereto.

The memory cell array 100 can be a memory cell, such as the memory cell described in connection with Figures 2, 3, 4A, 4B, and 4C. In this example, a memory cell is located at the intersection of word lines 130-0, 130-1, ..., 130-N and bit lines 120-0, 120-1, ..., 120-M. Each of the memory cells can be configured as a two-terminal architecture having, for example, a particular word line 130-0, 130-1, ..., 130-N and a bit line 120-0, 120-1, ..., 120-M are used as electrodes of the memory unit.

For example, the memory cells can be resistive variable memory cells (eg, RRAM cells, CBRAM cells, PCRAM cells, and/or STT-RAM cells) and other types of memory cells. A storage component 125 can include a storage component material and/or a selection device (e.g., an access device). The portion of the storage element material of the storage element 125 can include a programmable portion of the memory unit, for example, the portion can be programmed for a number of different data states. The access device can be, in particular, a diode or a non-ohmic device (NOD). For example, in a resistive variable memory cell, a storage component can include a portion of a memory cell having a resistor that can respond to a particular data state in response to, for example, an externally programmed voltage and/or current pulse. The specific level is programmed. A storage element can comprise one or more materials that collectively comprise a portion of a variable resistance storage element material of a storage element. For example, the materials may comprise a metal ion source layer, an oxygen absorbing layer (eg, an oxygen source layer), and an active switching layer (such as a solid electrolyte, a chalcogenide, a transition metal oxide material, or have two or Two or more metals (such as transition metals, alkaline earth gold At least one of a valence oxide and one of a rare earth metal). Embodiments are not limited to being associated with one or several specific resistance variable materials associated with storage elements 125 of a memory unit. For example, the resistance variable material can be a chalcogenide formed from various doped or undoped materials. Other examples of resistive variable materials that can be used to form the storage element include, inter alia, binary metal oxide materials, giant magnetoresistive materials, and/or various polymer-based resistance variable materials.

In operation, cross-over memory can be applied by applying selected word lines 130-0, 130-1, ..., 130-N and bit lines 120-0, 120-1, ..., 120-M. The memory cell array 100 is programmed by one of the body cells (eg, a write voltage). The width and/or magnitude of the voltage pulses across the memory cells can be adjusted (e.g., varied) to program a particular data state of the memory cells, for example, by adjusting the resistance level of one of the storage elements.

One bit line 120 corresponding to the respective memory cell can be sensed in response to a particular voltage applied to one of the selected word lines 130-0, 130-1, ..., 130-N coupled to the respective cell. A sensing (e.g., reading) operation is used to determine the data state of a memory cell, for example, at currents of 0, 120-1, ..., 120-M. The sensing operation can also include biasing the unselected word lines and bit lines at a particular voltage to sense the data state of a selected cell.

2 illustrates a portion of a memory cell array in accordance with one or more embodiments of the present invention. The memory cell array of FIG. 2 can be an array such as one of the arrays 100 depicted in FIG. As shown in FIG. 2, an electrode material 204 is formed on a substrate material 201. The substrate material 201 can be a semiconductor material such as germanium and various other substrate materials. Electrode material 204 can be a conductive material such as copper and/or tungsten and various other conductive materials. Electrode material The material 204 can be a bottom electrode, such as a conductive line (eg, one of the access lines shown in FIG. 1 (such as word lines 130-0 to 130-N) or a data line (such as bit line 120-0 to 120-M)). Electrode material 204 can be etched to form a plurality of valleys therein. For example, an isotropic etch process (such as plasma etching) and/or a wet etch process can be used to form the valleys in electrode material 204. The valleys in electrode material 204 have, for example, non-perpendicular sidewalls that are at an angle of less than 90 degrees with respect to the flat bottom surface of electrode material 204. In one or more embodiments, the side walls can have an angle between at least 10 and 80 degrees. In one or more embodiments, the side walls can have an angle between about 30 degrees and about 60 degrees. In one or more embodiments, the sidewalls may be convex and/or concave and substantially non-perpendicular. Embodiments are not limited to a particular non-perpendicular angle of one of the sidewalls of electrode 204. The etching used to form the electrode material 204 of the valleys in the electrode material 204 also isolates the electrodes 204 from each other.

In one or more embodiments, a valley in the electrode material 204 can be filled with a dielectric material 202. Dielectric material 202 can be a dielectric oxide or nitride such as tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO _x ) and various other dielectric materials. In the example shown in FIG. 2, dielectric material 202 and electrode material 204 are planarized to form a flat surface of dielectric material 202 and electrode material 204. The planarization of the surface of the electrode material 204 can result in the cross-sectional mask of the electrode 204 having a trapezoidal cross-sectional shape and separating the electrodes 204 from the dielectric material 202 formed in the respective valleys between the electrodes 204. Although not shown in FIG. 2, electrode 204 forms, for example, a conductive line along one of the directions into the page.

In one or more embodiments, a storage element material 206 can be formed over the planarization surface of the dielectric material 202 and the electrode material 204. Electrode material 204 includes a contact portion 207. The contact portion 207 of the electrode material can interface and contact the storage element material 206. For example, the storage element material 206 can be formed using a deposition process such as atomic layer deposition (ALD) and/or chemical vapor deposition (CVD). The storage element material 206 can comprise, for example, one or more resistance variable materials, such as a transition metal oxide material or one of two or more metals (eg, transition metals, alkaline earth metals, and/or rare earth metals). Titanium ore. Embodiments are not limited to a particular resistance variable material.

A dielectric material 212 can be formed over the storage element material 206. Dielectric material 212 can be a dielectric oxide or nitride such as, for example, tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO _x ). Material 212 can be etched to form a valley therein. For example, an isotropic etch process (such as plasma etching) and/or a wet etch process can be used to form the valleys in material 212. The etch process can be a selective etch process that etches down to one of the storage element materials 206. The sidewalls of the valleys in the dielectric material 212 are non-perpendicular (eg, at an angle of less than 90 degrees relative to the flat bottom surface of the substrate and/or the bottom surface of the electrode material 204) and may be straight, convex, and/or concave .

As depicted in FIG. 2, one of the electrode contact portions 210 of the electrode 208 can be formed in a valley formed in the dielectric material 212. Thus, the electrode contact portion 210 of the electrode 208 has sidewalls defined by sidewalls of the valleys formed in the dielectric material 212. The electrode contact portion 210 of the electrode 208 can be formed via a deposition process such as physical vapor deposition (PVD), CVD, and/or ALD. Embodiments are not limited to a particular contact material. In one or more embodiments, the contact material 210 can be composed of the same material as the electrode material 208. In one or more embodiments, the contact material 210 may be different from the material of the electrode material 208. Material composition. For example, contact material 210 can be a metal ion source material such as silver sulfide and/or copper telluride, while electrode material 208 can be tungsten and/or copper. In one or more embodiments in which the contact material 210 and the electrode material 208 are different materials, at least one intervening layer (eg, TaN) (not shown) may be included between the contact material 210 and the electrode material 208 to provide adhesion and / or a diffusion barrier.

An electrode material 208 may be formed in the remaining portion of the valley formed in the dielectric material 212 (eg, the remaining portion not filled by the electrode contact portion 210 of the electrode 208) to contact the electrode contact portion 210. Electrode material 208 can be a conductive material such as, for example, copper and/or tungsten. The electrode material 208 can be a top electrode, such as a conductive line (such as one of the access lines (such as word lines 130-0 to 130-N) or a data line (such as bit line 120-0 as shown in FIG. 1). To 120-M)). The electrode material 208 and the dielectric material 212 formed in the valley may be planarized (eg, etched back) to isolate the electrode material 208 formed in each valley of the dielectric material 212. The valleys formed in the dielectric material 212 have an orientation that is not parallel to the valleys formed in, for example, the electrode material 204 such that the electrodes 204 and 208 are not parallel. In one or more embodiments, electrodes 204 and 208 are orthogonal.

The memory cell according to the embodiment illustrated in FIG. 2 can provide less variability associated with a fibril nucleation location than the aforementioned memory cells (eg, CBRAM and/or RRAM cells). For example, the fibril nucleation sites can be positioned between a blunt peak of a respective electrode 204 and a point of the respective electrode contact portion 210. That is, the fibril nucleation site is between the point of the electrode contact portion 210 of the electrode 208 and the blunt peak of the electrode material 204, which is less variably less than having any fibril nucleation between, for example, two flat surfaces. One of the memory units in position. In addition, The point of the electrode contact portion 210 of the electrode 208 and the blunt peak of the electrode material 204 may concentrate the electric field in the storage element material 206 such that one of the voltages associated with one of the memory cells of FIG. 2 forms a voltage less than an electrode having a flat surface. One of the memory cells forms a voltage.

3 illustrates a portion of a memory cell array in accordance with one or more embodiments of the present invention. The memory cell array of FIG. 3 can be an array such as one of the arrays 100 depicted in FIG. As shown in FIG. 3, an electrode material 304 may be formed on a substrate 301. The substrate material 301 can be a substrate material such as tantalum and various other substrate materials. Electrode material 304 can be a conductive material such as copper/or tungsten and various other conductive materials. The electrode material 304 can be a bottom electrode, such as a conductive line (such as one of the access lines shown in FIG. 1 (such as word lines 130-0 to 130-N) or a data line (such as bit line 120-0 to 120-M)). Electrode material 304 can be etched to form a plurality of valleys therein. For example, the valleys in the electrode material 304 can be formed using a general isotropic etch process (such as plasma etching) and/or a wet etch process. The valleys in electrode material 304 have, for example, non-vertical sidewalls that are at an angle of less than 90 degrees with respect to the flat bottom surface of electrode material 304. In one or more embodiments, the side walls can have an angle between at least 10 and 80 degrees. In one or more embodiments, the side walls can have an angle between about 30 degrees and about 60 degrees. Embodiments are not limited to a particular non-perpendicular angle of one of the sidewalls of electrode 304. The etching of the electrode material 304 for forming the valleys in the electrode material 304 also isolates the electrodes 304 from each other.

In one or more embodiments, a valley in the electrode material 304 can be filled with a dielectric material 302. Dielectric material 302 can be a dielectric oxide or nitride such as tantalum nitride (Si ₃ N ₄ ) or tantalum oxide (SiO _x ) and various other dielectric materials. In the example shown in FIG. 3, dielectric material 302 can be etched to expose spikes in electrode material 304. For example, the dielectric material 302 can be etched using an anisotropic etch process such as plasma etching and/or physical sputtering. The etch process can be a selective etch process that etches only one of the dielectric materials 302. Etching of electrode material 304 can result in a cross-section of electrode 304 having a triangular cross-sectional shape. The etching of the electrode material 304 can include forming an electrode material 304 having a triangular cross-section, wherein the substantially triangular portions of the electrode material are separated by a dielectric material 302 formed in respective valleys between the electrode materials. Although not shown in FIG. 3, electrode 304 forms, for example, a conductive line along the direction into the page.

In one or more embodiments, a storage element material 306 can be formed over the electrode material 304 and the dielectric material 302. For example, storage element material 306 can be formed using a deposition process such as atomic layer deposition (ALD) and/or chemical vapor deposition (CVD). The electrode material 304 includes a contact portion 307. The contact portion 307 of the electrode material can be bound to the storage element material 306. The storage element material 306 is formed on the peak of the electrode material 304, and the conformal procedure used to form the storage element material 306 can cause the storage element material 306 to include spikes formed over the peaks of the electrode material 304. The storage element material 306 can comprise, for example, one or more resistance variable materials, such as a solid electrolyte composed of a transition metal oxide material or a chalcogenide material. Embodiments are not limited to a particular resistance variable material.

A dielectric material 312 can be formed over the storage element material 306. Dielectric material 312 can be a dielectric oxide or nitride such as, for example, tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (SiO _x ). Dielectric material 312 can be etched to form valleys therein. For example, an isotropic etch process (such as plasma etching) and/or a wet etch process can be used to form the valleys in the dielectric material 312. The etch process can be a selective etch process that etches down to one of the storage element materials 306. The sidewalls of the valleys in the dielectric material 312 are non-perpendicular, such as at an angle of less than 90 degrees relative to the flat bottom surface of the dielectric material 312 and/or the bottom surface of the electrode material 304.

As depicted in FIG. 3, one of the electrode contact portions 310 of the electrode 308 can be formed in a valley formed in the dielectric material 312. Thus, the electrode contact portion 310 of the electrode 308 can be formed on the peak of the storage element material 306. The peak of the storage element material 306 can serve as a saddle in which the electrode contact portion 310 of the electrode 308 is formed on a spike. The electrode contact portion 310 of the electrode 308 can have sidewalls defined by sidewalls of the valleys formed in the dielectric material 312. The electrode contact material can be formed using PVD, CVD, and/or ALD. In various embodiments, the electrode contact portion 310 of the electrode 308 can be CuTe formed via PVD. However, embodiments are not limited to a particular contact material.

An electrode material 308 may be formed in the remaining portion of the valley formed in the dielectric material 312 (eg, the remaining portion not filled by the electrode contact portion 310 of the electrode 308) to contact the electrode contact portion 310. Electrode material 308 can be a conductive material such as, for example, copper and/or tungsten. Electrode material 308 can be a top electrode, such as a conductive line (such as one of the access lines (such as word lines 130-0 to 130-N) or a data line (such as bit line 120-0 as shown in FIG. 1). To 120-M)). The electrode material 308 and the dielectric material 312 formed in the valley may be planarized (eg, polished and/or etched back) to be isolated from the dielectric material 312. Electrode material 308 in each valley. The valleys formed in the dielectric material 312 have an orientation orthogonal to one of the valleys formed in, for example, the electrode material 304 such that the electrodes 304 and 308 are orthogonal.

The memory unit according to the embodiment illustrated in FIG. 3 can provide less variability associated with a fibril nucleation location than the aforementioned memory unit (eg, CBRAM and/or RRAM unit). For example, the fibril nucleation location can be positioned between the electrode contact portion 310 of the electrode 308 formed on the peak of the storage element material 306 and the spike of the electrode material 304. That is, the fibril nucleation site is between the electrode contact portion 310 of the electrode 308 coupled to the peak of the storage element material 306 and the peak of the electrode material 304, the variability of which is less than, for example, between two flat surfaces One of the fibril nucleation sites is a memory unit. In addition, the electrode contact portion 310 of the electrode 308 coupled to the peak of the storage element material 306 and the peak of the electrode material 304 can concentrate the electric field in the storage element material 306 such that one of the memory cells of FIG. 3 forms a voltage less than and has One of the memory cells associated with one of the electrodes having a flat surface forms a voltage.

4A-4C illustrate a portion of a memory cell in accordance with one or more embodiments of the present invention. 4A is a block diagram of one portion of a memory cell in accordance with one or more embodiments of the present invention. FIG. 4A illustrates an electrode 404 of a memory unit. Electrode 404 can be one of the bottom electrodes of the memory unit. In various embodiments, electrode 404 includes a saddle region 405. The saddle region 405 includes a region that is recessed from, for example, the surface of the electrode 404 such that it has a saddle shape. The saddle region 405 can be formed by etching the electrode 404. Can be used to form saddle regions using, for example, electrodes and/or wet chemical etching procedures Etching of electrode 404 of 405. The saddle region 405 can include one surface area that is larger than the etched front surface area of the portion of the electrode 404 to be etched.

4B is a block diagram of one portion of a memory cell in accordance with one or more embodiments of the present invention. 4B illustrates electrode 404 of FIG. 4A in which storage element material 406 is formed in saddle region 405. The storage element material 406 has a uniform thickness and is in conformal contact with the electrode 404 above the surface region of the saddle region 405 defined during the etching process described above in connection with FIG. 4A. The surface area of the portion of the saddle region 405 that is in contact with the storage element material 406 is greater than the surface area of one of the surfaces of the bottom of the electrode 404 below the saddle region (which is the area of a corresponding flat intersection device). The interface area of the portion of the saddle region 405 that is in contact with the storage element material 406 is greater than the footprint of the projection region of the storage element. The footprint of the projection area of the storage element can be defined by multiplying the width 411 of the electrode 404 by the width 413 of the electrode 408.

4C is a block diagram of one portion of a memory cell in accordance with one or more embodiments of the present invention. An electrode 408 is illustrated in Figure 4C. Electrode 408 can be a top electrode and can be formed over material 406 formed in saddle region 405 of electrode 404 shown in Figure 4B. Thus, the electrode 408 is conformally formed over the saddle region 405 and the conformal storage element material 406 via the cut and/or damascene. Thus, electrode 408 includes a reverse saddle region 409. When electrode 408 is placed over electrode 404, the surface region of 409 can be in contact with the outer surface region of storage element material 406. Electrode 408 can be configured such that one of the bottom surfaces of electrode 408 is under the top surface of one of electrodes 404 when electrode 408 is placed over electrode 404. The surface area of the storage element material 406 is greater than the surface area of one of the bottom surfaces of the electrode 404 below the saddle area (which is associated with a flat device) The area corresponds to). Electrode 408 can be placed over electrode 404 and storage element material 406 such that electrode 408 is oriented non-parallel to electrode 404.

The memory cell formed according to the embodiment illustrated in FIGS. 4A-4C may have a larger memory electrode between the electrode and the storage element material than the memory cell having a flat surface area of the contact surface between the electrode and the storage element material. One surface area of the contact surface (e.g., between electrodes 406 and 408 and storage element material 406). Providing a surface area of the contact surface between the electrode and the storage element material in the memory unit by the saddle intersection than the flat intersection memory unit can give a given technology node and an RRAM device having an area distribution switching mechanism Provides greater signal-to-noise ratio (eg, sensing margin) and other benefits.

in conclusion

The present invention encompasses memory cell structures and methods of forming the same. The memory unit includes: a first electrode having a sidewall at an angle of less than 90 degrees with respect to a bottom surface of the first electrode; and a second electrode including an electrode contact portion of the second electrode, the electrode The contact portion has a sidewall at an angle of less than 90 degrees with respect to the bottom surface of the first electrode, wherein the second electrode is above the first electrode; and a storage element interposed between the first electrode and the second electrode The electrode contacts between the portions.

Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that the <RTIgt; The invention is intended to cover adaptations or variations of the various embodiments of the invention. It should be understood that the above description has been made in an illustrative and non-limiting manner. Combinations of the above embodiments with other embodiments not specifically described herein will be apparent to those of ordinary skill in the art. Many of the invention The scope of the embodiments encompasses other applications in which the above structures and methods are used. Accordingly, the scope of the various embodiments of the invention should be

In the foregoing [Embodiment], in order to simplify the present invention, some features may be grouped together in a single embodiment. The method of the present invention should not be construed as reflecting the intention that the disclosed embodiments of the present invention must use more features than those clearly recited in the claims. Rather, as the following claims reflect, the invention is characterized by less than all features of a single disclosed embodiment. Therefore, the following request items are hereby incorporated into [Embodiment], wherein each request item supports itself as a separate embodiment.

100‧‧‧Memory Cell Array

120-0‧‧‧Conductive wire/data line/bit wire

120-1‧‧‧Conductive wire/data line/bit wire

120-M‧‧‧Conductive wire/data line/bit wire

125‧‧‧Storage components

130-0‧‧‧Conductive wire/access wire/word wire

130-1‧‧‧Conductive wire/access wire/word wire

130-N‧‧‧Conductive wire/access wire/word wire

201‧‧‧Substrate material

202‧‧‧ dielectric materials

204‧‧‧Electrode material / electrode

206‧‧‧Storage component materials

207‧‧‧Contact section

208‧‧‧Electrode material / electrode

210‧‧‧Electrode contact parts/contact materials

212‧‧‧ dielectric materials

301‧‧‧Substrate

302‧‧‧Dielectric materials

304‧‧‧Electrode material / electrode

306‧‧‧Storage component materials

307‧‧‧Contact section

308‧‧‧Electrode material / electrode

310‧‧‧Electrode contact parts/contact materials

312‧‧‧ dielectric materials

404‧‧‧electrode

405‧‧‧ saddle area

406‧‧‧Storage component materials/materials

408‧‧‧electrode

409‧‧‧Reverse saddle area

411‧‧‧Width

413‧‧‧Width

1 is a block diagram showing a portion of a memory cell array.

2 illustrates a portion of a memory cell array in accordance with one or more embodiments of the present invention.

3 illustrates a portion of a memory cell array in accordance with one or more embodiments of the present invention.

4A-4C illustrate a portion of a memory cell in accordance with one or more embodiments of the present invention.

201‧‧‧Substrate material

202‧‧‧ dielectric materials

204‧‧‧Electrode material / electrode

206‧‧‧Storage component materials

207‧‧‧Contact section

208‧‧‧Electrode material / electrode

210‧‧‧Electrode contact parts/contact materials

212‧‧‧ dielectric materials

Claims (34)

A memory unit comprising: a first electrode having a sidewall at an angle of less than 90 degrees with respect to a bottom surface of the first electrode; and a second electrode including an electrode contact portion of the second electrode, the The electrode contact portion has a sidewall at an angle of less than 90 degrees with respect to the bottom surface of the first electrode, wherein the second electrode is above the first electrode, and the second electrode is formed on a first dielectric material. The first dielectric material has sidewalls that are at an angle of less than 90 degrees with respect to the bottom surface of the first electrode, and wherein one of the angled sidewalls of the second electrode and the one of the first electrodes are adjacent to each other; And a storage element interposed between the first electrode and the electrode contact portion of the second electrode, wherein the first dielectric material is formed on a top surface of the storage element. The memory cell of claim 1, wherein one of the electrode contact portions of the second electrode has a sidewall that is at an angle of less than 90 degrees with respect to the bottom surface of the first electrode. The memory unit of claim 1, wherein the first electrode has a trapezoidal cross-sectional area and a sidewall selected from the group consisting of straight, concave or convex. The memory unit of claim 3, wherein a top surface of one of the trapezoidal cross-sectional areas of the first electrode is an electrode contact portion of the first electrode and is in contact with the storage element. The memory unit of claim 1, wherein the first electrode has a triangle The cross-sectional area and the sidewall selected from the group consisting of a straight side wall, a concave side wall, or a convex side wall. The memory unit of claim 1, wherein the storage element comprises a resistance variable material and a selection device. The memory unit of claim 1, wherein the sidewalls of the electrode contact portion converge toward the storage element. The memory unit of claim 7, wherein an active area of the memory unit is between a vertex of one of the first electrodes and a vertex of the electrode contacting portion of the second electrode. A memory cell comprising: a resistance variable material formed on one of the first electrodes having one of the non-vertical sidewalls; a first dielectric material formed on top of the variable resistance material And having a valley formed therein, the valley having a non-vertical wall; and a contact portion of a second electrode formed in the valley such that the contact portion has a non-vertical sidewall defined by the valley. The memory cell of claim 9, wherein a remaining portion of one of the second electrodes is formed over the contact portion of one of the second electrodes in the valley such that the remaining portion of the second electrode has a valley defined by the valley Angled side walls. The memory unit of claim 9, wherein the first electrode is a bottom electrode and one of the angled sidewalls is formed in a valley, the valley is connected to the bottom electrode and an adjacent bottom electrode between. The memory unit of claim 9, wherein the first electrode is a bottom electrode Polar conductor line. The memory unit of claim 12, wherein the second electrode is a top electrode conductor line that is not parallel to the bottom electrode conductor line. A memory cell comprising: a resistance variable material formed on one of the first electrodes having one of the angled sidewalls such that one of the resistance variable material peaks and the angled sidewall of the resistance variable material Formed; a first dielectric material formed on the resistance variable material and having a valley formed therein; and a contact portion of a second electrode formed in the valley such that the contact portion contacts The peak of the variable resistance material and the angled sidewalls of the variable resistance material are such that the contact portion of the second electrode has angled sidewalls defined by the valley. The memory cell of claim 14, wherein the remaining portion of one of the second electrodes is formed on the contact portion within the valley such that the remaining portion of the second electrode has angled sidewalls defined by the valley. The memory cell of claim 14, wherein the contact portion of the second electrode is formed on the peak of the variable resistance material and overlaps the sidewalls of the variable resistance material. The memory cell of claim 14, wherein the surface area of the contact surface between the contact portion of the second electrode and the variable resistance material is defined by the sidewalls of the resistance variable material. The memory unit of claim 14, wherein the angled sidewalls of the contact portion of the second electrode are opposite to a bottom surface of the first dielectric material It is from about 10 degrees to about 80 degrees. A memory unit comprising: a first electrode having a saddle region; a resistance variable material formed in the saddle region and having a portion in contact with the first electrode; and a second electrode It has a portion that is in contact with the variable resistance material. The memory unit of claim 19, wherein an interface area of the portion of the variable resistance material in contact with the saddle region of the first electrode is greater than an area below the saddle region, and the interface area is It is equal to the width of one of the first electrodes multiplied by the width of one of the second electrodes. The memory cell of claim 19, wherein a surface area of the portion of the resistive variable material in contact with the second electrode is greater than a surface area of a surface of the first electrode below the saddle region. The memory unit of claim 19, wherein a bottom surface of one of the second electrodes is positioned under a top surface of the first electrode. The memory unit of claim 19, wherein the first electrode and the second electrode are oriented non-parallel to each other. The memory unit of claim 19, wherein the first electrode and the second electrode are surrounded by a dielectric material. The memory unit of claim 19, wherein the memory unit is a resistive random access memory (RRAM) unit. A memory cell array comprising: a first number of electrodes each having a first amount of electricity relative to the first quantity a bottom surface of the pole having a side wall having an angle of less than 90 degrees; a second number of electrodes each including an electrode contact portion having sidewalls at an angle of less than 90 degrees with respect to the bottom surfaces of the first number of electrodes The second number of electrodes are over the first number of electrodes and are formed on a plurality of dielectric material portions, each of the plurality of dielectric material portions having the bottom surface relative to the first number of electrodes a sidewall having an angle of less than 90 degrees, and wherein one of the angled sidewalls of each of the second number of electrodes is adjacent to each other at an angled sidewall of each of the first number of electrodes; and An element between the first number of electrodes and the electrode contact portions of the second number of electrodes, wherein the plurality of dielectric material portions are formed on a top surface of the plurality of storage elements. The memory cell array of claim 26, wherein the plurality of portions of the first dielectric material separate each of the first number of electrodes from each other. The memory cell array of claim 26, wherein a plurality of portions of the second dielectric material separate each of the second number of electrodes from each other. The memory cell array of claim 26, wherein the memory cell array is configured as a cross-point memory cell array. A memory cell array comprising: a plurality of saddle regions formed in a plurality of portions of a first contact material, wherein each of the plurality of portions of the first contact material is separated by a first dielectric material; a variable resistance storage element formed in each of the plurality of saddle regions; and A plurality of portions of a second contact material are formed over the variable resistance storage element in each of the plurality of saddle regions. The memory cell array of claim 30, wherein the plurality of portions of the second contact material are separated by a second dielectric material. The memory cell array of claim 30, wherein the plurality of portions of the first contact material and the portions of the second contact material are oriented non-parallel to each other. The memory cell array of claim 30, wherein the memory cell array is configured as a cross-point memory cell array. The memory cell array of claim 30, wherein the resistive variable storage element comprises a resistance variable storage element and a selection device.