TWI494765B - Vga interface switch apparatus - Google Patents

Description

VGA interface switching device

The invention relates to a VGA (video graphics array) interface switching device.

In testing the computer motherboard, in addition to the test computer and monitor, an additional computer and monitor are needed to facilitate viewing of the circuit diagram and other data. This requires two monitors, which not only takes up space but also wastes costs.

In view of the above, it is necessary to provide a VGA interface switching device for switching two sets of VGA signals to one monitor.

A VGA interface switching device includes first to third VGA interfaces, a single-pole double-throw switch, a switch control chip, and first to sixth electronic switches, wherein the switch controls the first and second enable pins of the chip to be connected to The first throwing point of the single-pole double-throw switch is further connected to the first ends of the fourth to sixth electronic switches, and is connected to the power pin of the first VGA interface through a first resistor, the switch controls the wafer The third and fourth enable pins are connected to the second throwing point of the single-pole double-throw switch, and are further connected to the first ends of the first to third electronic switches, and connected to the first VGA through a second resistor a power supply pin of the interface, the blade portion of the single-pole double-throw switch is grounded through a third resistor, and the first input pin and the first output pin of the switch control chip are respectively connected to the row of the second and first VGA interfaces a synchronous signal pin, wherein the second input pin and the second output pin of the switch control chip are respectively connected to the field sync signal pins of the second and first VGA interfaces, and the switch controls the third input pin of the chip and The third output pin is connected to the first And a line sync signal pin of the first VGA interface, wherein the fourth input pin and the fourth output pin of the switch control chip are respectively connected to the field sync signal pins of the third and first VGA interfaces, and the second VGA The three-way analog video signal pins of the interface are respectively connected to the second ends of the first to third electronic switches, and the three analog video signal pins of the third VGA interface are respectively connected to the fourth to sixth electronic switches. The second ends of the first to third electronic switches are respectively connected to the third ends of the fourth to sixth electronic switches, and are respectively connected to the three analog video signal pins of the first VGA interface. When the first ends of the first to sixth electronic switches are turned on at a high level, and the switches control the first to fourth enable pins of the chip to be low level, the first to fourth input pins respectively turn on the First to fourth output pins.

Compared with the prior art, the VGA interface switching device selectively switches the first VGA interface to the second VGA interface or the first VGA interface and the third VGA through the switching of the single-pole double-throw switch. It is very convenient to connect the interface, no need to use two monitors, which greatly reduces the cost.

Referring to FIG. 1 to FIG. 3, a preferred embodiment of the VGA interface switching device 100 of the present invention includes a first VGA interface 20, a second VGA interface 30, a third VGA interface 40, a switch 50, and a switch control. Wafer 60, six electronic switches Q1-Q6, three resistors R1-R3.

In this embodiment, the first to third VGA interfaces 20-40 and the switch 50 are disposed on an outer surface of the housing 70, and other components are disposed inside the housing 70. In other embodiments, the components are It can also be placed on a printed circuit board. In this embodiment, the electronic switches Q1-Q6 are all NMOS field effect transistors, and the first to third ends of the electronic switches Q1-Q6 respectively correspond to the gate, the drain and the source of the NMOS field effect transistor. Other electronic switches Q1-Q6 may also use other types of electronic switches in other embodiments. In this embodiment, the switch 50 is a push button type single pole double throw switch, including a knife portion c and two throwing points a, b. When the switch 50 is pressed, the knife portion c is switched from one of the throwing points. Go to another throw.

The first to third VGA interfaces 20-40 each include fifteen pins 1-15, wherein pins 1-3 are R, G, B three-way analog video signal pins, and pin 13 is a line sync signal ( HSYNC) pin, pin 14 is field sync signal (VSYNC) pin, pin 9 is power pin, pins 5-8, 10 are ground pins, pins 4, 11, 12, 15 are ID0 Pin, ID1 pin, SDA pin, and SCL pin. The ground pins 5-8 and 10 are grounded, and the pins 4, 11, 12, and 15 are all vacant.

In this embodiment, the switch control wafer 60 is a four-way bus buffer gate wafer (such as the model number SN74LVC125ADBR) having a three-state output. Other embodiments may also use other types of switch control wafers. The switch control chip 60 includes a power pin VCC, a ground pin GND, first to fourth enable pins OE1-OE4, first to fourth input pins 1A-4A, and first to fourth output leads. Feet 1Y-4Y. When the first enable pin OE1 is at a low level, the first input pin 1A is connected to the first output pin 1Y, and when the second enable pin OE2 is at a low level, the second input pin is The pin 2A is connected to the second output pin 2Y, and when the third enable pin OE3 is at a low level, the third input pin 3A is connected to the third output pin 3Y, when the fourth When the enable pin OE4 is at a low level, the fourth input pin 4A is turned on with the fourth output pin 4Y.

The power supply pin VCC of the switch control wafer 60 is connected to the power supply pin 9 of the second VGA interface 30, and the ground pin GND is grounded. The first and second enable pins OE1 and OE2 are connected to the throwing point a of the switch 50, and are also connected to the first end of the electronic switch Q4-Q6, and are connected to the first VGA interface through the resistor R3. 20 power pin 9. The third and fourth enable pins OE3 and OE4 are connected to the throwing point b of the switch 50, and are also connected to the first end of the electronic switch Q1-Q3, and are connected to the first VGA interface through the resistor R2. 20 power pin 9. The blade portion c of the changeover switch 50 is grounded through the resistor R1. The first input pin 1A and the first output pin 1Y are respectively connected to the second VGA interface 30 and the horizontal sync signal pin 13 of the first VGA interface 20, the second input pin 2A and the second output The pin 2Y is respectively connected to the second VGA interface 30 and the field sync signal pin 14 of the first VGA interface 20, and the third input pin 3A and the third output pin 3Y are respectively connected to the third VGA interface 40. And the line sync signal pin 13 of the first VGA interface 20, the fourth input pin 4A and the fourth output pin 4Y are respectively connected to the field synchronization signal pin of the third VGA interface 40 and the first VGA interface 20 14. The R, G, and B analog analog signal pins 1-3 of the second VGA interface 30 are respectively connected to the second ends of the electronic switches Q1-Q3, and the R, G, and B paths of the third VGA interface 40 are respectively The analog video signal pins 1-3 are respectively connected to the second ends of the electronic switches Q4-Q6. The third ends of the electronic switches Q1-Q3 are respectively connected to the third ends of the electronic switches Q4-Q6, and are also respectively connected to the R, G, B three-way analog video signal pins 1-3 of the first VGA interface 20. .

When the VGA interface switching device 100 is applied, the first VGA interface 20 is plugged into a corresponding VGA interface of a monitor (not shown), and the second VGA interface 30 and the third VGA interface 40 are respectively connected to the VGA interface. The corresponding VGA interface of the computer motherboard (not shown), at which time the two computer motherboards are turned on, and the power supply pin VCC of the switch control chip 60 receives the voltage signal received by the power pin 9 of the second VGA interface 30. Working, if the blade portion c of the switch 50 is turned on at the time of the throwing point a, the first and second enable pins OE1 and OE2 of the switch control wafer 60 are in a low state, and the third The fourth enable pins OE3 and OE4 are in a high state, the first ends of the electronic switches Q1-Q3 are at a high level, and the first ends of the electronic switches Q4-Q6 are at a low level. The electronic switches Q1-Q3 are turned on, and the electronic switches Q4-Q6 are turned off, so that the pins 1, 2, 3, 13, and 14 of the first VGA interface 20 and the pins 1 and 2 of the second VGA interface 30 are respectively The 3, 13, and 14 phases are connected, that is, the computer motherboard connected to the second VGA interface 30 communicates with the monitor, and the monitor displays the content thereof.At this time, the switch 50 is pressed, and the blade c is connected to the throwing point b. The switch controls the first and second enable pins OE1 and OE2 of the wafer 60 to be in a high state, and the third and The fourth enable pins OE3 and OE4 are in a low state, the first ends of the electronic switches Q1-Q3 are at a low level, and the first ends of the electronic switches Q4-Q6 are at a high level, The electronic switches Q1-Q3 are turned off, and the electronic switches Q4-Q6 are turned on, so that the pins 1, 2, 3, 13, and 14 of the first VGA interface 20 and the pins 1 and 2 of the third VGA interface 40 are respectively The 3, 13, and 14 phases are connected, that is, the computer motherboard connected to the third VGA interface 40 communicates with the monitor, and the monitor displays the content correspondingly. After the switch 50 is pressed again, the content of the other computer motherboard is switched again. Therefore, it is convenient to switch the display content between the two computer boards through the VGA interface switching device 100, and the two monitors are not needed, which greatly reduces the cost.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

100. . . VGA interface switching device

70. . . case

20. . . First VGA interface

30. . . Second VGA interface

40. . . Third VGA interface

50. . . Toggle switch

60. . . Switch control chip

Q1-Q4. . . electronic switch

R1-R3. . . resistance

1 is a schematic diagram of a preferred embodiment of a VGA interface switching device of the present invention.

2 to 3 are circuit diagrams of a preferred embodiment of the VGA interface switching device of the present invention.

100. . . VGA interface switching device

70. . . case

20. . . First VGA interface

30. . . Second VGA interface

40. . . Third VGA interface

50. . . Toggle switch

Claims (3)

A VGA interface switching device includes first to third VGA interfaces, a single-pole double-throw switch, a switch control chip, and first to sixth electronic switches, wherein the switch controls the first and second enable pins of the chip to be connected to The first throwing point of the single-pole double-throw switch is further connected to the first ends of the fourth to sixth electronic switches, and is connected to the power pin of the first VGA interface through a first resistor, the switch controls the wafer The third and fourth enable pins are connected to the second throwing point of the single-pole double-throw switch, and are further connected to the first ends of the first to third electronic switches, and connected to the first VGA through a second resistor a power supply pin of the interface, the blade portion of the single-pole double-throw switch is grounded through a third resistor, and the first input pin and the first output pin of the switch control chip are respectively connected to the row of the second and first VGA interfaces a synchronous signal pin, wherein the second input pin and the second output pin of the switch control chip are respectively connected to the field sync signal pins of the second and first VGA interfaces, and the switch controls the third input pin of the chip and The third output pin is connected to the first And a line sync signal pin of the first VGA interface, wherein the fourth input pin and the fourth output pin of the switch control chip are respectively connected to the field sync signal pins of the third and first VGA interfaces, and the second VGA The three-way analog video signal pins of the interface are respectively connected to the second ends of the first to third electronic switches, and the three analog video signal pins of the third VGA interface are respectively connected to the fourth to sixth electronic switches. The second ends of the first to third electronic switches are respectively connected to the third ends of the fourth to sixth electronic switches, and are respectively connected to the three analog video signal pins of the first VGA interface. When the first ends of the first to sixth electronic switches are turned on at a high level, and the switches control the first to fourth enable pins of the chip to be low level, the first to fourth input pins respectively turn on the First to fourth output pins. The VGA interface switching device of claim 1, wherein the switch control wafer is a four-way bus buffer gate wafer having a three-state output. The VGA interface switching device of claim 1, wherein the first to sixth electronic switches are NMOS field effect transistors, and the first to third ends of the first to sixth electronic switches respectively correspond to NMOS The gate, drain and source of the field effect transistor.