TWI492410B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- TWI492410B TWI492410B TW102111127A TW102111127A TWI492410B TW I492410 B TWI492410 B TW I492410B TW 102111127 A TW102111127 A TW 102111127A TW 102111127 A TW102111127 A TW 102111127A TW I492410 B TWI492410 B TW I492410B
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- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 116
- 239000002184 metal Substances 0.000 claims description 116
- 239000000758 substrate Substances 0.000 claims description 54
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 23
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 21
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 11
- 239000011787 zinc oxide Substances 0.000 claims description 11
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical group O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 7
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 7
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 6
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 6
- 239000004408 titanium dioxide Substances 0.000 claims description 6
- 230000003667 anti-reflective effect Effects 0.000 claims description 5
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 163
- 239000010408 film Substances 0.000 description 12
- 230000007246 mechanism Effects 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- -1 Al2O3) Chemical compound 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000003912 environmental pollution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Photovoltaic Devices (AREA)
Description
本發明是有關於一種半導體裝置及其製造方法,特別是有關於一種具有三層結構以形成類透明導電膜之電流傳導機制之半導體裝置及其製造方法。 The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a three-layer structure to form a current-conducting mechanism of a transparent conductive film and a method of fabricating the same.
近年來,由於環境污染的問題越來越嚴重,很多國家開始開發新的綠色能源來減少環境污染的問題。太陽能電池可將太陽的光能轉為電能,且這種轉換不會產生任何污染性的物質,因此太陽能電池逐漸受到重視。其中,為了增加太陽能電池之受光面積,因此可將太陽能電池之正極與負極均設置於太陽能電池之背光面,此即為指叉狀背面電極(Interdigitated Back Contact,IBC)太陽能電池。 In recent years, as the problem of environmental pollution has become more and more serious, many countries have begun to develop new green energy sources to reduce environmental pollution. Solar cells can convert the sun's light energy into electrical energy, and this conversion does not produce any polluting substances, so solar cells are gradually gaining attention. In order to increase the light receiving area of the solar cell, the positive electrode and the negative electrode of the solar cell can be disposed on the backlight surface of the solar cell, which is an interdigitated back contact (IBC) solar cell.
請參閱第1圖,係為一習知指叉狀背面電極太陽能電池之半導體裝置之剖面示意圖,此半導體裝置100具有半導體基板110,且半導體基板110於鄰近背光面110a之一側具有p型摻雜區111與n型摻雜區112,並連接金屬層150以分別作為半導體裝置100之正極與負極。 1 is a schematic cross-sectional view of a conventional semiconductor device for a fork-shaped back electrode solar cell. The semiconductor device 100 has a semiconductor substrate 110, and the semiconductor substrate 110 has a p-type doping on a side adjacent to the backlight surface 110a. The impurity region 111 and the n-type doping region 112 are connected to the metal layer 150 to serve as a positive electrode and a negative electrode of the semiconductor device 100, respectively.
而習知之半導體裝置100之製造方法係先於半導體基板110之背光 面110a上形成保護層120,再形成保護層120的開口121以暴露出部分之p型摻雜區111與n型摻雜區112。接著,再沉積金屬層150以覆蓋保護層120與暴露出之p型摻雜區111與n型摻雜區112,藉以使金屬層150接觸p型摻雜區111與n型摻雜區112。最後再於金屬層150中形成開口151,以分開接觸p型摻雜區111之金屬層與接觸n型摻雜區112之金屬層。 The manufacturing method of the conventional semiconductor device 100 precedes the backlight of the semiconductor substrate 110. A protective layer 120 is formed on the face 110a, and an opening 121 of the protective layer 120 is formed to expose a portion of the p-type doped region 111 and the n-type doped region 112. Next, a metal layer 150 is deposited to cover the protective layer 120 and the exposed p-type doped region 111 and the n-type doped region 112, thereby contacting the metal layer 150 with the p-type doped region 111 and the n-type doped region 112. Finally, an opening 151 is formed in the metal layer 150 to separately contact the metal layer of the p-type doping region 111 and the metal layer contacting the n-type doping region 112.
然而,於此製造方法中,開洞製程為必要之步驟。因此,開口尺寸之控制、應移除之部分保護層與金屬層是否殘留以及開口圖案之完整性等因素,將影響半導體裝置100之成長品質之優劣。此外,開洞製程亦容易造成保護層120對半導體基板110之鈍化效果變差。 However, in this manufacturing method, the hole opening process is a necessary step. Therefore, the control of the opening size, whether the portion of the protective layer to be removed and the metal layer remain, and the integrity of the opening pattern, etc., will affect the quality of the semiconductor device 100. In addition, the opening process also tends to cause the passivation effect of the protective layer 120 on the semiconductor substrate 110 to be deteriorated.
有鑑於上述習知技藝之問題,本發明之其中一目的就是在提供一種減少開洞製程之半導體裝置及其製造方法,藉以避免習知技藝之問題。 In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a semiconductor device for reducing the hole opening process and a method of fabricating the same, which avoids the problems of the prior art.
緣是,為達上述目的,本發明提供一種半導體裝置之製造方法,包含下列步驟:提供半導體基板,此半導體基板具有第一主表面,且半導體基板於鄰近第一主表面之一側具有複數個摻雜區;形成第一氧化層於半導體基板之第一主表面上;形成第一金屬圖案層於第一氧化層上,且第一金屬圖案層投影至第一主表面之圖案形狀係包含於半導體基板中之摻雜區之區域中;形成第二氧化層覆蓋第一氧化層及第一金屬圖案層;以及利用電鍍製程直接於第二氧化層上形成圖案形狀對應於第一金屬圖案層之第二金屬圖案層。 In order to achieve the above object, the present invention provides a method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate having a first major surface, and the semiconductor substrate having a plurality of sides adjacent to the first major surface a doped region; a first oxide layer is formed on the first main surface of the semiconductor substrate; a first metal pattern layer is formed on the first oxide layer, and a pattern shape of the first metal pattern layer projected onto the first main surface is included in a region of the doped region in the semiconductor substrate; forming a second oxide layer covering the first oxide layer and the first metal pattern layer; and forming a pattern shape directly on the second oxide layer by using an electroplating process corresponding to the first metal pattern layer a second metal pattern layer.
其中,本發明之半導體裝置之製造方法可於形成第一氧化層前,先去除第一主表面上之原生氧化物。 Wherein, the method of fabricating the semiconductor device of the present invention may remove the native oxide on the first major surface before forming the first oxide layer.
其中,本發明之半導體裝置可為指叉狀背面電極太陽能電池或其他光伏半導電體裝置,且本發明之半導體裝置中之半導體基板更具有相對於第一主表面之第二主表面,其中本發明之半導體裝置之製造方法更包含形成抗反射層於半導體基板之第二主表面上。 Wherein, the semiconductor device of the present invention may be a finger-shaped back electrode solar cell or other photovoltaic semiconductor device, and the semiconductor device in the semiconductor device of the present invention further has a second main surface relative to the first main surface, wherein The method of fabricating a semiconductor device of the invention further includes forming an anti-reflective layer on the second major surface of the semiconductor substrate.
其中,第一氧化層之厚度小於5奈米,第一金屬圖案層之厚度介於15奈米至20奈米之間,第二氧化層之厚度介於10奈米至20奈米之間。 Wherein, the thickness of the first oxide layer is less than 5 nm, the thickness of the first metal pattern layer is between 15 nm and 20 nm, and the thickness of the second oxide layer is between 10 nm and 20 nm.
其中,第一金屬圖案層之材料可為鋁、金、銀、銅、鈦或其他具有良好導電性之金屬或合金。此外,第一氧化層之材料可為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁、二氧化錫或其他適合之氧化物,第二氧化層之材料可為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁、二氧化錫或其他適合之氧化物。並且,第二氧化層之材料可相同於第一氧化層之材料。 The material of the first metal pattern layer may be aluminum, gold, silver, copper, titanium or other metals or alloys having good electrical conductivity. In addition, the material of the first oxide layer may be ceria, yttria, titania, zinc oxide, aluminum oxide, tin dioxide or other suitable oxide, and the material of the second oxide layer may be ceria, yttrium oxide, Titanium dioxide, zinc oxide, aluminum oxide, tin dioxide or other suitable oxides. Also, the material of the second oxide layer may be the same as the material of the first oxide layer.
因此,本發明之半導體裝置之製造方法可藉由三層結構共同形成類透明導電膜之電流傳導機制,藉以減少開洞製程,進而減少因開洞製程所導致之製程誤差。此外,本發明之半導體裝置之製造方法亦可藉由於半導體基板之第一主表面上依序堆疊形成第一氧化層、第一金屬圖案層及第二氧化層,以共同形成類透明導電膜之電流傳導機制,藉以可直接形成投影至第一主表面之圖案形狀包含於摻雜區之區域內之第二金屬圖案層,且此第二金屬圖案層不需經由開口與摻雜區直接連接,即可完成本發明之半導體裝置 。 Therefore, the manufacturing method of the semiconductor device of the present invention can form a current conduction mechanism of a transparent conductive film by a three-layer structure, thereby reducing the opening process, thereby reducing the process error caused by the opening process. In addition, the method for fabricating the semiconductor device of the present invention may be formed by sequentially forming a first oxide layer, a first metal pattern layer and a second oxide layer on the first main surface of the semiconductor substrate to form a transparent conductive film. a current conduction mechanism, whereby a second metal pattern layer that is formed in a pattern shape projected onto the first main surface and included in a region of the doped region is directly formed, and the second metal pattern layer is directly connected to the doped region via the opening, The semiconductor device of the present invention can be completed .
此外,本發明更提供一種半導體裝置,此半導體裝置例如為指叉狀背面電極太陽能電池或其他光伏半導電體裝置。其中,本發明之半導體裝置包含:半導體基板,具有相對之第一主表面及第二主表面,且此半導體基板於鄰近第一主表面之一側具有複數個摻雜區;第一氧化層,形成於半導體基板之第一主表面上;第一金屬圖案層,形成於第一氧化層上,且此第一金屬圖案層投影至第一主表面之圖案形狀係包含於半導體基板中之摻雜區之區域內;第二氧化層,覆蓋第一氧化層及第一金屬圖案層;第二金屬圖案層,形成於第二氧化層上,且第二金屬圖案層之圖案形狀係對應於第一金屬圖案層之圖案形狀;以及抗反射層,形成於半導體基板之第二主表面上。 Furthermore, the present invention further provides a semiconductor device such as a forked back electrode solar cell or other photovoltaic semiconductor device. The semiconductor device of the present invention comprises: a semiconductor substrate having a first main surface and a second main surface, wherein the semiconductor substrate has a plurality of doped regions on a side adjacent to the first main surface; the first oxide layer, Formed on the first main surface of the semiconductor substrate; the first metal pattern layer is formed on the first oxide layer, and the pattern shape of the first metal pattern layer projected onto the first main surface is doped in the semiconductor substrate a region of the region; a second oxide layer covering the first oxide layer and the first metal pattern layer; a second metal pattern layer formed on the second oxide layer, wherein the pattern shape of the second metal pattern layer corresponds to the first a pattern shape of the metal pattern layer; and an anti-reflection layer formed on the second main surface of the semiconductor substrate.
其中,第一氧化層之厚度小於5奈米,第一金屬圖案層之厚度介於15奈米至20奈米之間,第二氧化層之厚度介於10奈米至20奈米之間。 Wherein, the thickness of the first oxide layer is less than 5 nm, the thickness of the first metal pattern layer is between 15 nm and 20 nm, and the thickness of the second oxide layer is between 10 nm and 20 nm.
其中,第一金屬圖案層之材料可為鋁、金、銀、銅、鈦或其他具有良好導電性之金屬或合金。此外,第一氧化層之材料可為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁、二氧化錫或其他適合之氧化物,第二氧化層之材料可為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁、二氧化錫或其他適合之氧化物。並且,第二氧化層之材料可相同於第一氧化層之材料。 The material of the first metal pattern layer may be aluminum, gold, silver, copper, titanium or other metals or alloys having good electrical conductivity. In addition, the material of the first oxide layer may be ceria, yttria, titania, zinc oxide, aluminum oxide, tin dioxide or other suitable oxide, and the material of the second oxide layer may be ceria, yttrium oxide, Titanium dioxide, zinc oxide, aluminum oxide, tin dioxide or other suitable oxides. Also, the material of the second oxide layer may be the same as the material of the first oxide layer.
因此,本發明之半導體裝置之一特點在於,藉由第一氧化層、第一金屬圖案層及第二氧化層共同形成類透明導電膜之電流傳導機 制,藉以可直接形成投影至第一表面之圖案形狀包含於摻雜區之區域內之第二金屬圖案層,且此第二金屬圖案層不需經由開口直接連接摻雜區,即可成為本發明之半導體裝置之電極。 Therefore, one of the semiconductor devices of the present invention is characterized in that a current conducting machine such as a transparent conductive film is formed by a first oxide layer, a first metal pattern layer and a second oxide layer. The second metal pattern layer can be directly formed in the region of the doped region, and the second metal pattern layer can be directly connected to the doped region via the opening. An electrode of a semiconductor device of the invention.
綜上所述,依本發明之半導體裝置及其製造方法,可具有一或多個下述優點: In summary, the semiconductor device and the method of fabricating the same according to the present invention may have one or more of the following advantages:
(1)藉由於半導體基板之第一主表面上依序堆疊形成第一氧化層、第一金屬圖案層及第二氧化層,以共同形成類透明導電膜之電流傳導機制,藉以可直接形成投影至第一主表面之圖案形狀包含於摻雜區之區域內之第二金屬圖案層,且此第二金屬圖案層不需經由開口與摻雜區直接連接,即可完成本發明之半導體裝置。 (1) forming a first oxide layer, a first metal pattern layer, and a second oxide layer by sequentially stacking on the first main surface of the semiconductor substrate to jointly form a current conduction mechanism of the transparent conductive film, thereby directly forming a projection The semiconductor device of the present invention can be completed by the pattern shape of the first main surface including the second metal pattern layer in the region of the doped region, and the second metal pattern layer is directly connected to the doped region via the opening.
(2)藉由第一氧化層、第一金屬圖案層及第二氧化層共同形成類透明導電膜之電流傳導機制,藉以避免於製造半導體裝置時使用開洞製程,進而避免因開洞製程所導致之製程誤差。 (2) forming a current conduction mechanism of the transparent conductive film by the first oxide layer, the first metal pattern layer and the second oxide layer, thereby avoiding the use of the hole opening process in the manufacture of the semiconductor device, thereby avoiding the hole opening process The resulting process error.
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
110‧‧‧半導體基板 110‧‧‧Semiconductor substrate
110a‧‧‧背光面 110a‧‧‧Backlight
111‧‧‧p型摻雜區 111‧‧‧p-doped region
112‧‧‧n型摻雜區 112‧‧‧n-doped area
120‧‧‧保護層 120‧‧‧Protective layer
121‧‧‧開口 121‧‧‧ openings
150‧‧‧金屬層 150‧‧‧metal layer
151‧‧‧開口 151‧‧‧ openings
200‧‧‧半導體裝置 200‧‧‧Semiconductor device
210‧‧‧半導體基板 210‧‧‧Semiconductor substrate
210a‧‧‧第一主表面 210a‧‧‧ first major surface
210b‧‧‧第二主表面 210b‧‧‧second main surface
211‧‧‧n型摻雜區 211‧‧‧n-doped region
211A‧‧‧區域 211A‧‧‧Area
212‧‧‧p型摻雜區 212‧‧‧p-doped region
212A‧‧‧區域 212A‧‧‧Area
213‧‧‧間隔區 213‧‧‧ interval zone
220‧‧‧第一氧化層 220‧‧‧First oxide layer
230‧‧‧第一金屬圖案層 230‧‧‧First metal pattern layer
231‧‧‧第一n型對應金屬圖案 231‧‧‧First n-type corresponding metal pattern
232‧‧‧第一p型對應金屬圖案 232‧‧‧The first p-type corresponding metal pattern
240‧‧‧第二氧化層 240‧‧‧Second oxide layer
250‧‧‧第二金屬圖案層 250‧‧‧Second metal pattern layer
251‧‧‧第二n型對應金屬圖案 251‧‧‧Second n-type corresponding metal pattern
251a‧‧‧圖案形狀 251a‧‧‧pattern shape
252‧‧‧第二p型對應金屬圖案 252‧‧‧Second p-type corresponding metal pattern
252a‧‧‧圖案形狀 252a‧‧‧pattern shape
261‧‧‧保護層 261‧‧‧protection layer
262‧‧‧抗反射層 262‧‧‧Anti-reflective layer
910-950‧‧‧步驟 910-950‧‧‧Steps
第1圖係為習知指叉狀背面電極太陽能電池之半導體裝置之剖面示意圖。 1 is a schematic cross-sectional view of a semiconductor device of a conventional finger-shaped back electrode solar cell.
第2-4圖係為本發明之半導體裝置之製程局部剖面示意圖。 Figure 2-4 is a partial cross-sectional view showing the process of the semiconductor device of the present invention.
第5圖係為本發明之半導體裝置之局部剖面示意圖。 Fig. 5 is a partial cross-sectional view showing the semiconductor device of the present invention.
第6圖係為本發明之半導體裝置之局部仰視圖。 Figure 6 is a partial bottom plan view of the semiconductor device of the present invention.
第7圖係為本發明之半導體裝置之製造方法之流程圖。 Fig. 7 is a flow chart showing a method of manufacturing a semiconductor device of the present invention.
請參閱第2圖至第7圖,第2-4圖係為本發明之半導體裝置之製程 剖面示意圖,第5圖係為本發明之半導體裝置之剖面示意圖,第6圖係為本發明之半導體裝置之局部仰視圖,第7圖係為本發明之半導體裝置之製造方法之流程圖。 Please refer to FIG. 2 to FIG. 7 , and FIG. 2-4 is a process of the semiconductor device of the present invention. 5 is a schematic cross-sectional view of a semiconductor device of the present invention, FIG. 6 is a partial bottom view of the semiconductor device of the present invention, and FIG. 7 is a flow chart of a method for fabricating the semiconductor device of the present invention.
如第2圖至第7圖所示,本發明之半導體裝置200之製造方法係先提供半導體基板210(步驟910),其中半導體基板210具有第一主表面210a,且於鄰近第一主表面210a之一側具有複數個摻雜區(如n型摻雜區211及p型摻雜區212)。本實施例中的半導體裝置200為一指叉狀背面電極太陽能電池,半導體基板210之第一主表面210a為此太陽能電池之背光面,且半導體基板210於鄰近第一主表面210a之一側具有複數個摻雜區(如n型摻雜區211及p型摻雜區212)。其中,同一極性之摻雜區可以彼此相連或是分成多個互不相連的小區域。而需特別說明的是,半導體基板210本身亦可能含有摻雜物,但本說明書上下文中所提到之摻雜區係指該區域之摻雜濃度大於基板210之背景摻雜濃度,或是該區域之摻雜物之極性異於半導體基板210之背景摻雜物之極性。除此之外,此些摻雜區(如n型摻雜區211及p型摻雜區212)之間可具有間隔區213,且此間隔區213之摻雜濃度等同於半導體基板210之背景摻雜濃度,或者此間隔區213之極性相同於半導體基板210背景摻雜物之極性。 As shown in FIGS. 2 to 7, the method of fabricating the semiconductor device 200 of the present invention first provides a semiconductor substrate 210 (step 910), wherein the semiconductor substrate 210 has a first major surface 210a adjacent to the first major surface 210a. One side has a plurality of doped regions (such as an n-type doped region 211 and a p-type doped region 212). The semiconductor device 200 in this embodiment is a finger-shaped back electrode solar cell. The first main surface 210a of the semiconductor substrate 210 is a backlight surface of the solar cell, and the semiconductor substrate 210 has a side adjacent to the first main surface 210a. A plurality of doped regions (such as an n-type doped region 211 and a p-type doped region 212). The doped regions of the same polarity may be connected to each other or divided into a plurality of small regions that are not connected to each other. It should be particularly noted that the semiconductor substrate 210 itself may also contain a dopant, but the doping region mentioned in the context of the specification means that the doping concentration of the region is greater than the background doping concentration of the substrate 210, or The polarity of the dopant of the region is different from the polarity of the background dopant of the semiconductor substrate 210. In addition, the doped regions (such as the n-type doping region 211 and the p-type doping region 212) may have a spacer region 213, and the doping concentration of the spacer region 213 is equivalent to the background of the semiconductor substrate 210. The doping concentration, or the polarity of the spacer 213 is the same as the polarity of the background dopant of the semiconductor substrate 210.
此外,本發明之半導體裝置200之半導體基板210可例如更具有相對於第一主表面210a之第二主表面210b,且本發明之半導體裝置200之製造方法於提供半導體基板210後,可形成抗反射層262於第二主表面210b上。舉例而言,半導體基板210之第二主表面210b可例如為指叉狀背面電極太陽能電池之受光面,因此可於半 導體基板210之第二主表面210b上依序堆疊形成保護層261與抗反射層262,藉以增加本發明之半導體裝置200對於光線之吸收量。此外,於步驟910中所提供之半導體基板210更可已具有保護層261與抗反射層262。 In addition, the semiconductor substrate 210 of the semiconductor device 200 of the present invention may have, for example, a second main surface 210b opposite to the first main surface 210a, and the method of fabricating the semiconductor device 200 of the present invention may form an anti-deformation after the semiconductor substrate 210 is provided. The reflective layer 262 is on the second major surface 210b. For example, the second main surface 210b of the semiconductor substrate 210 can be, for example, a light receiving surface of a fork-shaped back electrode solar cell, and thus can be half The protective layer 261 and the anti-reflective layer 262 are sequentially stacked on the second main surface 210b of the conductor substrate 210, thereby increasing the absorption amount of light by the semiconductor device 200 of the present invention. In addition, the semiconductor substrate 210 provided in step 910 may have a protective layer 261 and an anti-reflection layer 262.
而於提供半導體基板210(步驟910)後,本發明之半導體裝置200之製造方法形成第一氧化層220於半導體基板210之第一主表面210a上(步驟920),藉以保護半導體基板210與半導體基板210中之n型摻雜區211及p型摻雜區212。其中半導體基板210之材料例如為單晶矽或多晶矽,第一氧化層220之材料可例如為二氧化矽(SiO2)、氧化矽(silicon oxide)、二氧化鈦(TiO2)、氧化鋅(ZnO)、氧化鋁(如三氧化二鋁Al2O3)、二氧化錫(SnO2)或其他適合之氧化物。且第一氧化層220對半導體基板210具有一定鈍化效果,但第一氧化層220之厚度較佳係小於5奈米,以不影響半導體裝置200之整體導電度。舉例而言,本發明之半導體裝置200之製造方法可例如於移除半導體基板210之第一主表面210a上的原生氧化物後,以熱氧化之方式形成二氧化矽或氧化矽於半導體基板210之第一主表面210a上,亦或者,以物理氣相沉積法(physical vapor phase deposition,PVD)或化學氣相沉積法(chemical vapor deposition,CVD)形成氧化物於半導體基板210之第一主表面210a上,藉以形成第一氧化層220於半導體基板210之第一主表面210a上。 After the semiconductor substrate 210 is provided (step 910), the manufacturing method of the semiconductor device 200 of the present invention forms the first oxide layer 220 on the first main surface 210a of the semiconductor substrate 210 (step 920), thereby protecting the semiconductor substrate 210 and the semiconductor. The n-type doping region 211 and the p-type doping region 212 in the substrate 210. The material of the semiconductor substrate 210 is, for example, a single crystal germanium or a polycrystalline germanium. The material of the first oxide layer 220 may be, for example, hafnium oxide (SiO2), silicon oxide, titanium oxide (TiO2), zinc oxide (ZnO), oxidation. Aluminum (such as Al2O3), tin dioxide (SnO2) or other suitable oxide. The first oxide layer 220 has a certain passivation effect on the semiconductor substrate 210, but the thickness of the first oxide layer 220 is preferably less than 5 nm so as not to affect the overall conductivity of the semiconductor device 200. For example, the manufacturing method of the semiconductor device 200 of the present invention may form the germanium dioxide or hafnium oxide on the semiconductor substrate 210 by thermal oxidation, for example, after removing the native oxide on the first main surface 210a of the semiconductor substrate 210. Forming an oxide on the first major surface of the semiconductor substrate 210 on the first main surface 210a or by physical vapor phase deposition (PVD) or chemical vapor deposition (CVD) The first oxide layer 220 is formed on the first main surface 210a of the semiconductor substrate 210 by 210a.
接著,於步驟920後,本發明之半導體裝置200之製造方法形成第一金屬圖案層230於第一氧化層220上(步驟930),且第一金屬圖案層230投影至第一主表面210a之圖案形狀係包含於n型摻雜區 211及p型摻雜區212所共同組成之區域內。其中,第一金屬圖案層230之圖案形狀可相對應於n型摻雜區211及p型摻雜區212所共同組成之區域。此外,第一金屬圖案層230之材料可例如為鋁(Al)、金(Au)、銀(Ag)、銅(Cu)、鈦(Ti)或其他具有良好導電性之金屬或合金。並且,第一金屬圖案層230之厚度較佳係介於15奈米(nanometer,nm)至20奈米之間,藉以形成導電度較為完整也較佳且不致影響後續製程之連續薄膜。 Next, after the step 920, the manufacturing method of the semiconductor device 200 of the present invention forms the first metal pattern layer 230 on the first oxide layer 220 (step 930), and the first metal pattern layer 230 is projected onto the first main surface 210a. The pattern shape is included in the n-type doping region The region between the 211 and the p-doped region 212 is common. The pattern shape of the first metal pattern layer 230 may correspond to a region where the n-type doping region 211 and the p-type doping region 212 are common. Further, the material of the first metal pattern layer 230 may be, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), titanium (Ti), or other metals or alloys having good electrical conductivity. Moreover, the thickness of the first metal pattern layer 230 is preferably between 15 nanometers (nm) and 20 nanometers, thereby forming a continuous film which is relatively complete in conductivity and which does not affect subsequent processes.
舉例而言,於步驟920後,本發明之半導體裝置200之製造方法可例如利用金屬遮罩搭配物理氣相沉積法,藉以進行區域化之薄膜金屬沉積。其中,金屬遮罩之開洞位置投影至第一主表面210a上之尺寸大小係包含於n型摻雜區211及p型摻雜區212所共同形成之區域內。因此,本發明之半導體裝置200之製造方法於步驟930中可形成第一n型對應金屬圖案231與第一p型對應金屬圖案232,且第一n型對應金屬圖案231與第一p型對應金屬圖案232投影至第一主表面210a上之圖案形狀係各別包含於n型摻雜區211及p型摻雜區212之區域內,而此些第一n型對應金屬圖案231與第一p型對應金屬圖案232共同組成第一金屬圖案層230。 For example, after step 920, the method of fabricating the semiconductor device 200 of the present invention can utilize, for example, a metal mask in conjunction with physical vapor deposition to effect regionalized thin film metal deposition. The size of the opening position of the metal mask projected onto the first main surface 210a is included in a region formed by the n-type doping region 211 and the p-type doping region 212. Therefore, in the manufacturing method of the semiconductor device 200 of the present invention, the first n-type corresponding metal pattern 231 and the first p-type corresponding metal pattern 232 may be formed in step 930, and the first n-type corresponding metal pattern 231 corresponds to the first p-type. The pattern shapes projected onto the first main surface 210a by the metal pattern 232 are respectively included in the regions of the n-type doping region 211 and the p-type doping region 212, and the first n-type corresponding metal patterns 231 and the first The p-type corresponding metal patterns 232 collectively constitute the first metal pattern layer 230.
而於步驟930後,本發明之半導體裝置200之製造方法形成第二氧化層240覆蓋第一金屬圖案層230與暴露出之第一氧化層220(步驟940)。其中,第二氧化層240之厚度較佳係介於10奈米至20奈米之間,且第二氧化層240之材料可為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁(如三氧化二鋁)、二氧化錫或其他適合之氧化物。並且,第二氧化層240之材料可相同或不同於第一氧化層220之材料。舉例而言,於步驟940中,可利用物理氣相沉積法或 化學氣相沉積法等製程技術,以形成覆蓋第一金屬圖案層230與第一氧化層220之第二氧化層240。其中,第一氧化層220、第一金屬圖案層230與第二氧化層240之三層結構可共同形成類透明導電膜之電流傳導機制,且此三層結構之表面電阻率低達10-4-10-5歐姆公分(Ω‧cm)。 After the step 930, the manufacturing method of the semiconductor device 200 of the present invention forms the second oxide layer 240 to cover the first metal pattern layer 230 and the exposed first oxide layer 220 (step 940). The thickness of the second oxide layer 240 is preferably between 10 nm and 20 nm, and the material of the second oxide layer 240 may be ceria, yttria, titania, zinc oxide, or aluminum oxide. Al2O3), tin dioxide or other suitable oxide. Also, the material of the second oxide layer 240 may be the same or different from the material of the first oxide layer 220. For example, in step 940, physical vapor deposition or A process technique such as chemical vapor deposition to form a second oxide layer 240 covering the first metal pattern layer 230 and the first oxide layer 220. The three-layer structure of the first oxide layer 220, the first metal pattern layer 230 and the second oxide layer 240 can jointly form a current conduction mechanism of the transparent conductive film, and the surface resistivity of the three-layer structure is as low as 10-4. -10-5 ohm centimeters (Ω ‧ cm).
接著,於步驟940後,本發明之半導體裝置200之製造方法利用電鍍製程,直接形成圖案形狀對應於第一金屬圖案層230之第二金屬圖案層250(步驟950),藉以避免進行開洞製程及其所導致之製程誤差。舉例而言,於步驟950中,可將前述之三層結構接上電位並置於電鍍槽內,藉由此三層結構不同區域之導電性,藉以於特定位置上電鍍有第二n型對應金屬圖案251及第二p型對應金屬圖案252而共同組成第二金屬圖案層250。換言之,由於相對應於第一金屬圖案層230之圖案形狀之區域相對於其他區域,具有較佳之導電性,因此第二金屬圖案層250可直接電鍍於相對應於第一金屬圖案層230之圖案形狀之區域上之第二氧化層240上,藉以形成圖案形狀對應於第一金屬圖案層230之圖案形狀之第二金屬圖案層250。其中,由於第一金屬圖案層230投影至第一主表面210a之圖案形狀係包含於n型摻雜區211及p型摻雜區212所共同形成之區域內,因此第二金屬圖案層250投影至第一主表面210a之圖案形狀亦包含於n型摻雜區211及p型摻雜區212所共同形成之區域內。 Then, after the step 940, the manufacturing method of the semiconductor device 200 of the present invention directly forms the second metal pattern layer 250 corresponding to the first metal pattern layer 230 by using an electroplating process (step 950), thereby avoiding the opening process. And the resulting process error. For example, in step 950, the foregoing three-layer structure can be connected to a potential and placed in a plating bath, whereby the second n-type corresponding metal is plated at a specific position by the conductivity of different regions of the three-layer structure. The pattern 251 and the second p-type corresponding metal pattern 252 together constitute the second metal pattern layer 250. In other words, since the region corresponding to the pattern shape of the first metal pattern layer 230 has better conductivity with respect to other regions, the second metal pattern layer 250 can be directly plated on the pattern corresponding to the first metal pattern layer 230. On the second oxide layer 240 on the shape of the shape, a second metal pattern layer 250 having a pattern shape corresponding to the pattern shape of the first metal pattern layer 230 is formed. The pattern shape of the first metal pattern layer 230 projected onto the first main surface 210a is included in a region where the n-type doping region 211 and the p-type doping region 212 are formed together, so the second metal pattern layer 250 is projected. The pattern shape to the first main surface 210a is also included in a region where the n-type doping region 211 and the p-type doping region 212 are formed together.
舉例而言,第二n型對應金屬圖案251投影至第一主表面210a之圖案形狀251a係包含於n型摻雜區211之區域211A內,第二p型對應金屬圖案252投影至第一主表面210a之圖案形狀252a係包含於摻 雜區212之區域212A內,藉以使得第一n型對應金屬圖案231及第二n型對應金屬圖案251共同組成n型摻雜區211之連外電極,以及使得第一p型對應金屬圖案232及第二p型對應金屬圖案252共同組成p型摻雜區212之連外電極。且為了分別導出具有不同極性之n型摻雜區211與p型摻雜區212中之電流,第二n型對應金屬圖案251與第二p型對應金屬圖案252係相互分離。 For example, the pattern shape 251a projected onto the first main surface 210a by the second n-type corresponding metal pattern 251 is included in the region 211A of the n-type doping region 211, and the second p-type corresponding metal pattern 252 is projected onto the first main The pattern shape 252a of the surface 210a is included in the blend In the region 212A of the impurity region 212, the first n-type corresponding metal pattern 231 and the second n-type corresponding metal pattern 251 together constitute an external electrode of the n-type doping region 211, and the first p-type corresponding metal pattern 232 is formed. And the second p-type corresponding metal pattern 252 together constitute an external electrode of the p-type doping region 212. And in order to separately derive currents in the n-type doped regions 211 and the p-type doped regions 212 having different polarities, the second n-type corresponding metal patterns 251 and the second p-type corresponding metal patterns 252 are separated from each other.
總言之,本發明之半導體裝置200之製造方法可藉由三層結構共同形成類透明導電膜之電流傳導機制,藉以避免開洞製程,進而避免因開洞製程所導致之製程誤差。再者,本發明之半導體裝置200之製造方法可藉由三層結構共同形成類透明導電膜之電流傳導機制,藉以可直接形成投影至第一主表面210a上之圖案形狀包含於摻雜區之區域內之第二金屬圖案層250,且此第二金屬圖案層250不需經由開口與摻雜區直接連接,即可完成本發明之半導體裝置200。 In summary, the manufacturing method of the semiconductor device 200 of the present invention can form a current conduction mechanism of a transparent conductive film by a three-layer structure to avoid a hole opening process, thereby avoiding a process error caused by a hole opening process. Furthermore, the manufacturing method of the semiconductor device 200 of the present invention can form a current conduction mechanism of a transparent conductive film by a three-layer structure, whereby a pattern shape directly projected onto the first main surface 210a is included in the doped region. The semiconductor device 200 of the present invention can be completed by the second metal pattern layer 250 in the region, and the second metal pattern layer 250 is directly connected to the doped region via the opening.
因此,本發明之半導體裝置200可例如為指叉狀背面電極太陽能電池等光伏半導電體裝置。其中,本發明之半導體裝置200可包含半導體基板210、第一氧化層220、第一金屬圖案層230、第二氧化層240、第二金屬圖案層250以及抗反射層262。其中,半導體基板210具有相對應之第一主表面210a與第二主表面210b。舉例而言,第一主表面210a和第二主表面210b可為指叉狀背面電極太陽能電池之背光面和受光面。並且,半導體基板210於鄰近第一主表面210a之一側可例如具有複數個摻雜區(如n型摻雜區211及p型摻雜區212)。 Therefore, the semiconductor device 200 of the present invention may be, for example, a photovoltaic semiconductor device such as a fork-shaped back electrode solar cell. The semiconductor device 200 of the present invention may include a semiconductor substrate 210, a first oxide layer 220, a first metal pattern layer 230, a second oxide layer 240, a second metal pattern layer 250, and an anti-reflection layer 262. The semiconductor substrate 210 has a corresponding first main surface 210a and second main surface 210b. For example, the first major surface 210a and the second major surface 210b may be a backlight surface and a light receiving surface of the interdigitated back electrode solar cell. Moreover, the semiconductor substrate 210 may have a plurality of doped regions (such as an n-type doped region 211 and a p-type doped region 212) on a side adjacent to the first main surface 210a.
續言之,第一氧化層220係形成於半導體基板210之第一主表面 210a上,第一金屬圖案層230係形成於第一氧化層220上,且第一金屬圖案層230投影至第一主表面210a上之圖案形狀包含於摻雜區所共同形成之區域內。此外,第二氧化層240係覆蓋第一氧化層220及第一金屬圖案層230,而第二金屬圖案層250係形成於第二氧化層240上,且第二金屬圖案層250之圖案形狀係相對應於第一金屬圖案層230之圖案形狀。換言之,第二金屬圖案層250投影至第一主表面210a上之圖案形狀包含於摻雜區所共同形成之區域內。另外,半導體基板210之第二主表面210b上可依序堆疊有保護層261及抗反射層262之複層結構。 In other words, the first oxide layer 220 is formed on the first main surface of the semiconductor substrate 210. The first metal pattern layer 230 is formed on the first oxide layer 220, and the pattern shape projected onto the first main surface 210a by the first metal pattern layer 230 is included in a region where the doped regions are formed together. In addition, the second oxide layer 240 covers the first oxide layer 220 and the first metal pattern layer 230, and the second metal pattern layer 250 is formed on the second oxide layer 240, and the pattern shape of the second metal pattern layer 250 is Corresponding to the pattern shape of the first metal pattern layer 230. In other words, the pattern shape projected onto the first main surface 210a by the second metal pattern layer 250 is included in a region where the doped regions are formed together. In addition, a multi-layer structure of the protective layer 261 and the anti-reflection layer 262 may be sequentially stacked on the second main surface 210b of the semiconductor substrate 210.
其中,第一氧化層220之材料可例如為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁(如三氧化二鋁)、二氧化錫或其他適合之氧化物,第一金屬圖案層230之材料可例如為鋁、金、銀、銅、鈦或其他導電性佳之金屬,且第二氧化層240之材料可例如為二氧化矽、氧化矽、二氧化鈦、氧化鋅、氧化鋁(如三氧化二鋁)、二氧化錫或其他適合之氧化物。並且,第二氧化層240之材料可相同或不同於第一氧化層220之材料。 The material of the first oxide layer 220 may be, for example, hafnium oxide, hafnium oxide, titanium dioxide, zinc oxide, aluminum oxide (such as aluminum oxide), tin dioxide or other suitable oxide, and the first metal pattern layer 230 The material may be, for example, aluminum, gold, silver, copper, titanium or other metal with good conductivity, and the material of the second oxide layer 240 may be, for example, cerium oxide, cerium oxide, titanium dioxide, zinc oxide, aluminum oxide (such as trioxide). Alluminium), tin dioxide or other suitable oxide. Also, the material of the second oxide layer 240 may be the same or different from the material of the first oxide layer 220.
此外,因為於本發明之半導體裝置200中,第一氧化層220、第一金屬圖案層230及第二氧化層240係用以共同形成類透明導電膜之三層結構,因此第一氧化層220之厚度較佳係小於5奈米,第一金屬圖案層230之厚度較佳係介於15奈米至20奈米之間,且第二氧化層240之厚度較佳係介於10奈米至20奈米之間。 In addition, in the semiconductor device 200 of the present invention, the first oxide layer 220, the first metal pattern layer 230, and the second oxide layer 240 are used to collectively form a three-layer structure of a transparent conductive film, and thus the first oxide layer 220 Preferably, the thickness of the first metal pattern layer 230 is between 15 nm and 20 nm, and the thickness of the second oxide layer 240 is preferably between 10 nm and 20 nm. Between 20 nm.
因此,本發明之半導體裝置200之一特點在於,藉由第一氧化層220、第一金屬圖案層230及第二氧化層240共同形成類透明導電膜之電流傳導機制,藉以可直接形成投影至第一主表面210a之圖 案形狀包含於摻雜區之區域內之第二金屬圖案層250,且此第二金屬圖案層250不需經由開口直接連接摻雜區,即可成為本發明之半導體裝置200之電極。 Therefore, one of the features of the semiconductor device 200 of the present invention is that the first oxide layer 220, the first metal pattern layer 230 and the second oxide layer 240 together form a current conduction mechanism of the transparent conductive film, thereby directly forming a projection to Diagram of the first major surface 210a The shape of the second metal pattern layer 250 is included in the region of the doped region, and the second metal pattern layer 250 is directly connected to the doped region via the opening to form an electrode of the semiconductor device 200 of the present invention.
以上所述僅為舉例性,而非為限制性者。任何未脫離本發明之精神與範疇,而對其進行之等效修改或變更,均應包含於後附之申請專利範圍中。 The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.
200‧‧‧半導體裝置 200‧‧‧Semiconductor device
210‧‧‧半導體基板 210‧‧‧Semiconductor substrate
210a‧‧‧第一主表面 210a‧‧‧ first major surface
210b‧‧‧第二主表面 210b‧‧‧second main surface
211‧‧‧n型摻雜區 211‧‧‧n-doped region
212‧‧‧p型摻雜區 212‧‧‧p-doped region
213‧‧‧間隔區 213‧‧‧ interval zone
220‧‧‧第一氧化層 220‧‧‧First oxide layer
230‧‧‧第一金屬圖案層 230‧‧‧First metal pattern layer
231‧‧‧第一n型對應金屬圖案 231‧‧‧First n-type corresponding metal pattern
232‧‧‧第一p型對應金屬圖案 232‧‧‧The first p-type corresponding metal pattern
240‧‧‧第二氧化層 240‧‧‧Second oxide layer
250‧‧‧第二金屬圖案層 250‧‧‧Second metal pattern layer
251‧‧‧第二n型對應金屬圖案 251‧‧‧Second n-type corresponding metal pattern
252‧‧‧第二p型對應金屬圖案 252‧‧‧Second p-type corresponding metal pattern
261‧‧‧保護層 261‧‧‧protection layer
262‧‧‧抗反射層 262‧‧‧Anti-reflective layer
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