TWI482162B - Method and apparatus for reducing erase time of memory by using partial pre-programming - Google Patents

Description

Method and apparatus for reducing memory erasure time by partial pre-programming

This invention relates to techniques for non-volatile memory arrays, and more particularly to methods and apparatus for reducing memory erase time.

U.S. Patent Nos. 6,094,373 and 6,842,378 discuss the process of performing erasure in a group of memory cells, one of which is followed by a pre-programming step. In this group of memory cells, some memory cells are in a stylized state and some other memory cells are in an erased state. Before erasing all the memory cells in the memory cells of this group, the memory cells in the memory cells that have been erased will be pre-programmed to stylized state. Such pre-stylization will bring all the memory cells in the group memory cell to a shared stylized state, and prevent the memory cells that have been erased from being erased again. The erase after the pre-programming step then brings the self-programming state of all memory cells in the group memory cell to a shared erase state. Therefore, the pre-programming prevents the memory cells in the group of memory cells from being unexpected after being erased by bringing the threshold voltages of all the memory cells in the group of memory cells to a stylized state before erasing. Wide threshold voltage distribution.

The disadvantage of this pre-programming is that it is a very time consuming operation compared to erasing. The erase program is relatively fast compared to pre-stylization, and all memory cells in this group of memory cells are erased. However, not all memory cells in this group of memory cells are pre-programmed; the memory cells in the erased state are treated differently from the memory cells in the stylized state. The memory cells in the memory group that have been erased state are first pre-programmed to a stylized state, and the memory cells in the memory group that are already in the stylized state are not pre-programmed first. These different processing of memory cells in different states will result in pre-stylization that is more necessary than erasing. time consuming. Although pre-stylization can cause the memory cells in this group of memory cells to produce a narrower threshold voltage distribution, it also causes the erasing process to take longer.

The techniques described herein provide an integrated circuit having a non-volatile memory array and control circuitry. The non-volatile memory array has a plurality of memory cells each of a plurality of threshold voltage ranges, the plurality of threshold voltage ranges including at least one erase threshold voltage range and a stylized threshold voltage range. The control circuit is responsive to an erase command to erase a group of memory cells in the non-volatile memory array, and the erase has a plurality of stages including a pre-programming stage and an erase stage. The pre-programming stage is to program the threshold voltage of the group of memory cells in a first group of memory cells within the erased threshold voltage range, and does not program the threshold voltage system in the group of memory cells in the erase criticality A second set of memory cells within the voltage range. In the erase phase after the pre-stylization phase, the control circuit erases the entire group of memory cells.

In some embodiments described herein, the erase command selects a group of memory cells from the plurality of memory cells segmented by the non-volatile memory array for erasing.

In some embodiments described herein, the erase command specifies that the group of memory cells is partitioned into a plurality of pre-programmed regions. The stylization of the first set of memory cells in the pre-stylized phase is only in one of the pre-programmed regions of the plurality of pre-programmed regions. Memory cells in other pre-programmed regions are not pre-programmed, regardless of whether the threshold voltage of these cells is within the erase threshold voltage range. The integrated circuit further includes a memory for storing pre-programmed location data, and the control circuit reads the pre-programmed location data to determine the pre-programmed region. The control circuit can change the pre-programmed area to the next pre-programmed area each time the erase command is responded to erase the group of memory cells. here In some embodiments described herein, wherein the pre-programmed region is the first time the control circuit responds to the erase command to erase the group of memory cells from the plurality of pre-programmed regions when the integrated circuit is turned on Selecting, and wherein the control circuit changes the pre-programmed region to the next pre-stylized region each time the second and subsequent times after the integrated circuit is turned on, in response to the erase command to erase the group of memory cells .

In some embodiments described herein, the erasing stage erases at least the first set of memory cells (programmed in the pre-stylturization phase) and the second set of memory cells (not in the pre-stylized phase) Stylized). The first set of memory cells (programmed in the pre-stylturization phase) and the second set of memory cells (not programmed in the pre-stylturization phase) have a threshold voltage value before the pre-stylization phase. Except for the threshold voltage range. The memory cell selected by the erase command may be further included in the third set of memory cells within the threshold voltage range before the pre-stylization phase. The third set of memory cells are not stylized during the pre-stylization phase and are erased along with the first set of memory cells and the second set of memory cells during the erase phase.

The techniques disclosed herein also include a method. The method comprises at least the following steps: responsive to a erase command to erase a group of memory cells of a non-volatile memory array, the data in the memory cells being one of a plurality of threshold voltage ranges, the plurality of threshold voltage ranges being at least Included is a erased threshold voltage range representative of the erased state and a stylized threshold voltage range representative of the stylized state: (i) performing a pre-stylization phase that stylizes the threshold voltage in the group of memory cells at the erase critical a first set of memory cells within a voltage range, and does not program a second set of memory cells in the group having a threshold voltage within the erase threshold voltage; and (ii) performing after the pre-stylization phase In the erasing phase, the erasing phase erases the entire group of memory cells.

Many different embodiments are described herein.

The technique disclosed herein also includes another method in which the control circuit stylizes the first set of memory cells only in the plurality of preprograms during the pre-programming phase The threshold voltage in a pre-programmed region of the region is the memory cell within the erase voltage range, regardless of whether the threshold voltage of the memory cell in other pre-programmed regions is within the erase threshold voltage range.

The techniques described herein also provide an integrated circuit having a non-volatile memory array and control circuitry. The non-volatile memory array has a plurality of memory cells, and each of the memory cells has a threshold voltage that is one of an erased state or a stylized state. The control circuit erases a group of memory cells of the non-volatile memory array during an erase cycle. The erase period includes at least: (i) a pre-programming stage that only programs a portion of the memory cells of the memory cell in the erased state; and (ii) an erase after the pre-stylization phase In the stage, the erasing stage erases the entire group of memory cells.

The techniques described herein also provide a method of erasing memory cells during an erase cycle, the memory cells being arranged in a memory array having a plurality of word lines. The method of the erase cycle includes at least: performing a pre-stylization phase in the erase cycle, which only programs a portion of a set of memory cells in an erased state; and performing an erase on the erase week In the stage, it erases all memory cells in the memory cells of the group.

In some embodiments described herein, the set of memory cells are allocated as a plurality of word line lines, and the portion of the set of memory cells is allocated as part of a plurality of word line lines.

In some embodiments described herein, the method is responsive to an erase command to erase a set of memory cells in the memory array, and the data in the memory cell is comprised of an erase threshold representative of an erased state. The voltage range and the programmed threshold voltage range representing a stylized state.

In some embodiments described herein, the stylization of the portion of the set of memory cells in the pre-stylized phase is only performed in a pre-programmed region of the group partitioned into a plurality of pre-stylized regions . Some implementations described here In the example, the method further includes reading the pre-programmed location data stored in a memory to determine the pre-programmed area. In some embodiments described herein, the pre-programmed region is selected from the plurality of pre-stylized regions. In some embodiments described herein, the method further includes receiving the erase command for the first time when the integrated circuit having the memory array is turned on to select the pre-programmed region from the plurality of pre-stylized regions. . In some embodiments described herein, the method further includes changing the pre-programmed region to the next pre-programmed region each time the erase command is received. In some embodiments described herein, the method further includes receiving the erase command for the first time when the integrated circuit having the memory array is turned on to select the pre-programmed region from the plurality of pre-stylized regions. And changing the pre-programmed area to the next pre-stylized area each time the erase command is received the second time after the integrated circuit having the non-volatile memory array is turned on and thereafter.

In some embodiments described herein, the pre-stylization phase does not program a second set of memory cells in the group of memory cells having a threshold voltage within the programmed threshold voltage range, and the erase phase The portion of the memory cells of the group of memory cells, other portions of the memory cells of the group of memory cells, and the second group of memory cells are erased.

Many different embodiments are described herein.

Figure 1 is an example flow diagram of an erase program showing a series of threshold voltage distributions of memory cells that are not used in a erase step without a pre-programmed erase step.

There are two threshold voltage distributions in the threshold voltage distribution of a set of memory cells shown in the series of patterns. The dashed line indicates that the erasing procedure in this group of memory cells begins with a memory cell in which the memory cell threshold voltage is distributed in the erased state, which has a lower threshold voltage distribution. The solid line indicates that the erasing procedure in the group of memory cells starts from the memory cell in which the memory cell threshold voltage is distributed in the stylized state, and has a higher Critical voltage distribution.

In the region of 10, two separate threshold voltage distributions are shown. This combination of memory cells represented by two separate threshold voltage distributions can represent the memory cell threshold voltage distribution in a erased group of memory cells. The dashed line indicates that the memory cell threshold voltage distribution in this erase process begins with a lower threshold voltage distribution. The solid line indicates that the memory cell threshold voltage distribution in this erase process starts from a higher threshold voltage distribution.

In the area of 12, this group of memory cells is subjected to a repeated erasing step without pre-stylization. This repeated erase step is to show that a multiple erase program without pre-programming can cause an unexpectedly wider threshold voltage distribution, which is discussed further below. Any particular single erase procedure can be performed in a single erase step (or multiple erase steps if the erase verification fails).

In the region of 14, two overlapping critical voltage distributions are shown. Again, this combination of memory cells represented by two overlapping threshold voltage distributions can represent the memory cell threshold voltage distribution in a erase group. The dashed line indicates that the erase procedure in this group of memory cells begins with a lower threshold voltage distribution, but it now has an unexpectedly wider threshold voltage distribution and even extends into a negative threshold voltage. The dashed threshold voltage distribution is repeatedly erased, although it has begun to be erased from a lower threshold voltage distribution. Because the pre-programming step is continually skipped in this multiple erase process, the threshold voltage distribution extends into the negative threshold voltage direction. The solid line indicates that the erase procedure in this group of memory cells begins with a higher threshold voltage distribution.

In the area of 16, it indicates that this group of memory cells is soft-programmed. The effect of this soft stylization on over-erase and low-threshold memory cells is to make the threshold voltage distribution of this group of memory cells closer.

In the area of 18, two overlapping critical voltage distributions are shown. Soft stylization only successfully corrects portions of the unexpectedly wider threshold voltage distribution. The solid line indicates that the erase procedure in this group of memory cells begins with a higher threshold voltage distribution. Soft path Modification is sufficient to correct the critical voltage distribution of this solid line. The dashed line indicates that the erase procedure in this group of memory cells begins with a lower threshold voltage distribution, but it now has an unexpectedly wider threshold voltage distribution and even extends into a negative threshold voltage. Soft stylization is not sufficient to correct the critical voltage distribution of the dashed line.

The eraser program shown in 10th to 18th is relatively fast because it skips pre-stylization. However, the threshold voltage distribution it generates is broad and even extends into a negative threshold voltage, which is problematic for the anti-gate array.

Figure 2 is an example flow diagram of an erase program showing a series of threshold voltage distributions of memory cells using a complete pre-programmed erase step in an erase program.

In the region of 20, two separate threshold voltage distributions are shown. This combination of memory cells represented by two separate threshold voltage distributions can represent the memory cell threshold voltage distribution in a erase group. The dashed line indicates that the erase procedure in this group of memory cells begins with a lower threshold voltage distribution. The solid line indicates that the erase procedure in this group of memory cells begins with a higher threshold voltage distribution.

In the area of 22, this group of memory cells is represented for complete pre-stylization. In the complete pre-stylization, all memory cells of the lower critical voltage distribution in this dashed line are programmed. In the region of 24, the two overlapping threshold voltage distributions are shown to represent the memory cells combined to represent the memory cell threshold voltage distribution in a erase group. The dashed line indicates that the erase program in this group of memory cells is programmed from a lower threshold voltage distribution. The solid line indicates that the erase procedure in this group of memory cells begins with a stylized state of a higher threshold voltage distribution, which does not change. As a result, both the dotted cell and the solid cell memory cell voltage distribution are higher threshold voltage distributions.

In the area of 26, this memory cell group is shown as an erase step. As a result of this erasing step, the threshold voltage distribution becomes wider. In the region of 28, the two overlapping threshold voltage distributions are shown to represent the memory cells combined to represent the memory cell threshold voltage distribution in a erase group. As in step 24 The pre-stylized conclusion is that both the dotted line and the solid memory cell critical voltage distribution are higher threshold voltage distributions. After erasing, both the dotted cell and the solid line memory cell voltage distribution at step 28 are both lower threshold voltage distributions.

In the area of 30, this group of memory cells is soft-programmed. This soft programming effect on over-erase and low-threshold voltage memory cells is to make the threshold voltage distribution of this group of memory cells closer. In the region of 32, two overlapping threshold voltage distributions are shown, the memory cells represented by which can be combined to represent the critical voltage distribution of all memory cells in a erased group. As with the conclusion of erasing at 28, both the dotted cell and the solid line memory cell voltage distribution are unexpectedly broadened, with a lower threshold voltage distribution. After soft programming, both the dotted cell and the solid line memory cell voltage distribution have a narrower, lower threshold voltage distribution.

The erase procedure as shown in Figures 20-32 has an acceptable threshold voltage distribution in the erased group memory cell. However, this erase procedure becomes very time consuming because step 22 programs each memory cell at a lower threshold voltage distribution to a complete pre-stylization of a higher threshold voltage distribution.

Figure 3 is a block diagram of a memory cell showing that a memory array is divided into a plurality of multiple erase groups, and a group of memory cells are divided into a plurality of pre-programmed regions.

This memory array 48 is divided into multiple erased memory cells 1, 2, ..., i..., M. A memory cell group can be, for example, a contiguous memory cell group of segments, blocks, or paragraphs that can be erased together in response to an erase command. The erased group of the memory cell can respond to an erase command that erases the entire memory array for the entire memory array.

This erased memory cell can be further divided into multiple pre-stylized regions. The erased memory cell group i (example 50 as shown in the figure) is divided into pre-programmed regions 1, 2, ..., i...N-2, N-1, N. By splitting a memory cell into multiple pre-programmed regions, pre-programming can be performed on a portion of the memory cell group rather than on the entire erase memory cell group. In multiple erase programs, in each subsequent Different pre-programmed areas can be selected for pre-programming in the program, so that each pre-programmed area has the opportunity to be pre-programmed.

Figure 4 is an example flow diagram of an erase or erase cycle having a particular pre-programmed region selected for selective pre-programming in the erase state memory cell as shown in Figure 3.

At step 34, the integrated circuit with the memory array receives an erase command. This erase command specifies that one or more memory cells are to be erased. A memory cell group can be a memory cell group that is to be erased together, such as a segment, a block, or a segment. This memory cell group can also be the entire memory array.

In step 36, selective memory is performed on the memory cells selected to be erased from the erased memory cell group. Such pre-stylization is optional, so that pre-stylization is only performed by erasing a portion of the memory cells in the memory cell population. As shown in Figure 3, this erased memory cell is divided into multiple pre-programmed regions. This pre-programming is only done on the memory cells of at least one particular pre-programmed area in the erase group. Such selective pre-stylization differs from full pre-stylization in that it erases all memory cells in the memory cell that have been erased. In selective pre-programming, only the memory cells in the memory sector that have been erased in the specific pre-programmed region are pre-programmed. Even in this memory cell, the memory cells outside the specific pre-programmed area of the erased state are not pre-programmed.

Because pre-programming is only done by erasing a portion of the memory cells in the memory cell population, this pre-stylization is faster than the entire erasing of all memory cells in the memory cell population.

At step 38, all memory cells in the erased memory cell population are erased. At step 40, an erase verification is performed to check if the previous erase operation is sufficient to erase all of the memory cells in the memory group selected to be erased. At step 42, if the verification is not passed, the erase algorithm returns to step 38 to repeat the erase. In step 42, if the verification is erased, the erase algorithm goes down. Row. At step 44, the memory cells that are over-erased in the memory group to be erased are soft-programmed. At step 46, the erase command is ended.

In the erasing procedure of Fig. 4, the pre-stylization of step 36 is not performed on the memory cell in which the memory cell group to be erased has been erased. In a multiple erase program, if the same memory cell is repeatedly erased without being pre-programmed, the memory cell becomes an unacceptably low threshold voltage. However, this problem can be prevented by changing the pre-programmed memory cells in Figure 5. Figure 5 is an example flow diagram of an erase program that has a particular pre-programmed area selected for pre-programming.

At step 52, the integrated circuit with the memory array receives an erase command. This erase command specifies that one or more memory cells are to be erased.

Step 54 determines if the erase program is the first erase program after powering up. In various embodiments, the eraser program is the entire array or is executed first in a particular memory cell group that is designated to be erased by an erase command. If the erase program is the first erase program after booting, a pre-programmed region is randomly selected from the erased memory cell group at step 56. In another embodiment, the first pre-programmed area is determined upon power up. If the erase program is the second or subsequent erase program after booting, then in step 58, the next pre-programmed region is selected from the pre-programmed regions of the erased memory cell group.

At step 60, pre-stylization is performed on the selected pre-stylized regions. At step 62, all memory cells in the erased memory cell population are erased. The dotted portion indicates that other steps are performed on the memory cell after erasing, such as erase verification and soft stylization discussed in FIG.

Figure 6 shows a simplified block diagram of a memory integrated circuit having a memory array and the improvements described herein in accordance with an embodiment of the present invention. The integrated circuit 150 includes a memory array 100. A word line (column) decoder and block selection decoder 101 and a plurality of word lines arranged along the column direction of the memory array 100 102 coupling and electrical communication. A bit line (row) decoder and driver 103 are coupled and electrically communicated with a plurality of bit lines 104 arranged along the row direction of the memory array 100 to read data and write from the memory cells of the memory array 100. data. The address is supplied from the bus bar 105 to the word line decoder 101 and the bit line decoder 103. The sense amplifier and data input structure in block 106 is coupled to the bit line decoder via bus bar 107. The data is supplied to the data input line 111 from the input/output port on the integrated circuit 150 to the data input structure in block 106. The data is provided by the sense amplifier in block 106, via the data output line 115, to the input/output ports on the integrated circuit, or to other internal/external data sources of the integrated circuit 150. The stylizing, erasing, and reading adjustment bias state mechanism 109 controls the application of the bias adjustment supply voltage 108 and performs selective pre-programming upon erasing. State mechanism circuit 109 also includes a memory 140 that determines the next pre-programmed region to be erased. The memory 140 can be a non-volatile memory, a counter, or a register in a control circuit.

Figure 7 is a block diagram showing the arrangement of complex array word lines in a different pre-stylized area in a memory bank.

More specifically, a column decoder 201 is coupled to different pre-programmed regions via different sets of word lines. The first word line 211 couples the column decoder 201 to the first pre-stylized region 221. The second word line 212 couples the column decoder 201 to the second pre-stylized region 222. The N-2th word line 214 couples the column decoder 201 to the N-2 pre-stylized area 224. The N-1th word line 215 couples the column decoder 201 to the N-1 pre-stylized area 225. The Nth word line 216 couples the column decoder 201 to the Nth pre-stylized region 226.

Different sets of word lines 211, 212, 214, 215, and 216 contain one or more word lines. The pre-programmed regions 221, 222, 224, 225, and 226 shown here belong to the same erased memory cell group as shown, for example, in FIG. Additional erase memory cells with additional pre-programmed regions can be configured by configuring this additional complex array character to erase additional pre-programmed regions in the memory cell population The line is coupled to the column decoder 201.

Figure 8 is a block diagram showing the arrangement of complex array bit lines in a different pre-stylized area in a memory bank.

More specifically, a row decoder 203 is coupled to different pre-programmed regions via different sets of bit lines. The first bit line 251 couples the row decoder 203 to the first pre-stylized region 261. The second bit line 252 couples the row decoder 203 with the second pre-stylized region 262. The N-1th bit line 255 couples the row decoder 203 to the N-1 pre-stylized region 265. The Nth bit line 256 couples the row decoder 203 to the Nth pre-stylized region 266.

Different sets of bit lines 251, 252, 255, and 256 contain one or more bit lines. The pre-programmed regions 261, 262, 265, and 266 shown here belong to the same erased memory cell group as shown, for example, in FIG. The same erased memory cell group can include memory cells on a single bit line or on multiple bit lines. Multiple pre-programmed regions can include memory cells on a single bit line or on multiple bit lines. An additional erase memory bank having an additional pre-programmed region can be coupled to row decoder 203 via a complex array bit line that configures this additional pre-programmed region of the erased memory cell.

Only one stylized state is shown in the figure, but other embodiments include multiple stylized states, such as multi-level memory cells with two bits and three stylized quasi-located memory locations, and three bits. Meta or seven stylized multi-level memory cells located in each memory location.

The techniques disclosed in the preferred embodiments of the present invention can be applied to non-volatile memory arrays such as reverse OR (NOR) gate arrays. An example of a non-volatile memory element can be a floating gate element or a dielectric charge trapping memory element.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

48‧‧‧ memory array

50‧‧‧Erase memory cells

150‧‧‧ integrated circuit

100‧‧‧Non-volatile memory cell array

101‧‧‧ column decoder

102‧‧‧ character line

103‧‧‧ line decoder

104‧‧‧ bit line

105‧‧‧ busbar

107‧‧‧ data bus

106‧‧‧Sense Amplifier/Data Entry Structure

109‧‧‧Programming, erasing (selectively stylized) and reading the adjustment bias state mechanism

140‧‧‧ Logic for storing pre-programmed location data

108‧‧‧ bias adjustment supply voltage

111‧‧‧ data input line

115‧‧‧ data output line

201‧‧‧ column decoder

211, 212, 214, 215, 216‧‧ ‧ character lines

221, 222, 224, 225, 226 ‧ ‧ pre-stylized areas

203‧‧ ‧ row decoder

251, 252, 255, 256‧ ‧ bit lines

261, 262, 265, 266‧ ‧ pre-stylized areas

Figure 1 is an example flow diagram of an erase program showing a series of threshold voltage distributions of memory cells that are not used in a erase step without a pre-programmed erase step.

Figure 2 is an example flow diagram of an erase program showing a series of threshold voltage distributions of memory cells using a complete pre-programmed erase step in an erase program.

Figure 3 is a block diagram of a memory cell, showing a memory array divided into a plurality of multiple erase groups, and a memory cell segment is divided into a plurality of pre-programmed regions.

Figure 4 is an example flow diagram of an erase program or erase cycle having a particular pre-programmed region selected for selective pre-programming in the erase state memory cell as shown in Figure 3.

Figure 5 is an example flow diagram of an erase program that has a particular pre-programmed area selected for pre-programming.

Figure 6 shows a simplified block diagram of a memory integrated circuit having a memory array and the improvements described herein in accordance with an embodiment of the present invention.

Figure 7 is a block diagram showing the arrangement of complex array word lines in a different pre-stylized area in a memory bank.

Figure 8 is a block diagram showing the arrangement of complex array bit lines in a different pre-stylized area in a memory bank.

Claims (20)

An integrated circuit comprising: a non-volatile memory array having a plurality of memory cells each of a plurality of threshold voltage ranges, the plurality of threshold voltage ranges including at least one erased threshold voltage range and a stylized threshold voltage range And a control circuit responsive to a erase command to erase a group of memory cells in the non-volatile memory array, and the erasing has a plurality of stages including at least: a pre-programming stage, wherein the threshold voltage of the group of memory cells is programmed The first group of memory cells in the threshold voltage range is erased, and the threshold voltage in the group of memory cells is not programmed in a second group of memory cells within the erased threshold voltage range; and an erasing phase, After the pre-stylization phase, the entire group of memory cells is erased. For example, in the integrated circuit of claim 1, wherein the group of memory cells is divided into a plurality of pre-stylized regions, and the first group of memory cells that are programmed in the pre-stylization phase are only the plurality of memory cells. One of the pre-programmed areas of the pre-programmed area. For example, in the integrated circuit of claim 1, wherein the group of memory cells is divided into a plurality of pre-stylized regions, and the first group of memory cells that are programmed in the pre-stylization phase are only the plurality of memory cells. One of the pre-programmed areas of the pre-programmed area; and the integrated circuit further includes a memory for storing pre-programmed location data, and the control circuit reads the pre-programmed location data to determine the pre-stylization region. For example, in the integrated circuit of claim 1, wherein the group of memory cells is divided into a plurality of pre-programmed regions, and the first group of memory cells that are programmed in the pre-stylization phase are only the plurality of pre-programmed One of the pre-programmed regions of the stylized region, wherein the pre-stylized region is one of the plurality of pre-stylized regions. For example, in the integrated circuit of claim 1, wherein the group of memory cells is divided into a plurality of pre-programmed regions, and the first group of memory cells that are programmed in the pre-stylization phase are only the plurality of pre-programmed One of the pre-programmed regions of the stylized region, wherein the pre-programmed region is selected from the plurality of pre-stylized regions to erase the first time in response to the erase command when the integrated circuit is turned on Group memory. For example, in the integrated circuit of claim 1, wherein the group of memory cells is divided into a plurality of pre-programmed regions, and the first group of memory cells that are programmed in the pre-stylization phase are only the plurality of pre-programmed One of the pre-programmed areas of the stylized area, wherein the control circuit changes the pre-programmed area to the next pre-stylized area each time the erase command is responded to erase the group of memory cells. For example, in the integrated circuit of claim 1, wherein the group of memory cells is divided into a plurality of pre-programmed regions, and the first group of memory cells that are programmed in the pre-stylization phase are only the plurality of pre-programmed One of the pre-programmed regions of the stylized region, wherein the pre-programmed region is selected from the plurality of pre-stylized regions to erase the first time in response to the erase command when the integrated circuit is turned on a group memory cell, and wherein the control circuit changes the pre-programmed area to the next pre-stylized area to erase the group each time the second and subsequent times after the integrated circuit is turned on, in response to the erase command Memory cell. The integrated circuit of claim 1, wherein the non-volatile memory array is divided into a plurality of erase groups, and the erase command selects the group of memory cells from the plurality of erase groups for erasing. For example, the integrated circuit of claim 1 of the patent scope, wherein: The pre-stylization phase does not program a third set of memory cells in the group of memory cells having a threshold voltage within the programmed threshold voltage range, and the erase phase is for the first group of memory cells, the second The group of memory cells and the third group of memory cells were erased. A method of erasing memory cells in an erase cycle, the memory cells being arranged in a memory array having a plurality of word lines, the method comprising: performing a pre-stylization phase in the erase cycle, Only a portion of a set of memory cells in an erased state is programmed; and an erase phase is performed during the erase cycle, which erases all memory cells in the set of memory cells. The method of claim 10, wherein the group of memory cells are distributed over a plurality of word lines, and the portion of the memory cells of the group of memory cells are distributed over a portion of the plurality of word lines. The method of claim 10, wherein the method is responsive to a erase command to erase a group of memory cells in the memory array, and the data in the memory cells belongs to one of a plurality of threshold voltage ranges, The plurality of threshold voltage ranges includes at least one erase threshold voltage range representing the erase state and a programmed threshold voltage range representing the stylized state. The method of claim 10, wherein the portion of the memory cells of the group of memory cells that are programmed in the pre-stylization phase is only divided into one of a plurality of pre-stylized regions. Stylized area. The method of claim 10, wherein the stylization of the portion of the memory cells of the group of memory cells in the pre-stylization phase is only a pre-stylization of the group of memory cells into a plurality of pre-stylized regions. The area, and further includes: reading the pre-programmed location data stored in a memory to determine the pre-programmed area. The method of claim 10, wherein the stylization of the portion of the memory cells of the group of memory cells in the pre-stylization phase is only a pre-stylization of the group of memory cells into a plurality of pre-stylized regions. The area, and further includes: selecting the pre-programmed area from the plurality of pre-stylized areas. For example, in the method of claim 10, the stylization of the portion of the memory cells of the group of memory cells in the pre-stylization phase is only the division of the group of memory cells into a pre-programmed region of the plurality of pre-stylized regions. And further comprising: receiving an erase command for the first time when the integrated circuit of the memory array is turned on, to select the pre-programmed region from the plurality of pre-stylized regions. For example, in the method of claim 10, the stylization of the portion of the memory cells of the group of memory cells in the pre-stylization phase is only the division of the group of memory cells into a pre-programmed region of the plurality of pre-stylized regions. And further includes: changing the pre-programmed area to the next pre-stylized area each time an erase command is received. For example, in the method of claim 10, the stylization of the portion of the memory cells of the group of memory cells in the pre-stylization phase is only the division of the group of memory cells into a pre-programmed region of the plurality of pre-stylized regions. And more include: Receiving an erase command for the first time when the integrated circuit having the memory array is turned on, selecting the pre-programmed region from the plurality of pre-stylized regions, and turning on the integrated circuit having the non-volatile memory array The second and subsequent times, each time the erase command is received, the pre-programmed area is changed to the next pre-stylized area. The method of claim 10, wherein: the pre-stylization stage does not program a second group of memory cells having a threshold voltage within the programmed threshold voltage range of the group of memory cells, and the erasing The stage erases the portion of the memory cells of the group of memory cells, the other portions of the memory cells of the group of memory cells, and the second group of memory cells. An integrated circuit comprising: a non-volatile memory array having a threshold voltage of a plurality of memory cells, each memory cell having an erased state or a stylized state; and a control circuit for erasing the non-volatile memory during an erase cycle Array of memory cells, the erase cycle comprising at least: a pre-programming stage that only programs a portion of the memory cells of the memory cells in the erased state; and a erase phase in which the pre-stylization After the stage, the erasing stage erases all memory cells in the group of memory cells.