TWI467762B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

This invention relates to an integrated circuit and, more particularly, to a semiconductor component.

With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the integration of integrated circuits must be continuously improved to meet the trend of light, thin, short and small electronic components. In order to increase the degree of integration, the area occupied by the semiconductor element must be reduced.

1A is a top plan view of a conventional semiconductor device. Fig. 1B is a schematic cross-sectional view taken along line I-1' of Fig. 1A. As shown in FIG. 1A and FIG. 1B, conventional gate-structures 102a, 102b having metal stripe elements 101a, 101b, respectively, are disposed on the substrate 100. In the substrate 100 on both sides of the gate structures 102a, 102b, there are drains 104a, 104b and sources 106a, 106b extending in the direction of the parallel gate structures 102a, 102b, respectively. A doped region 108 extending in the direction of the parallel gate structures 102a, 102b is disposed in the substrate 100 between the source 106a of the MOS element 101a and the source 106b of the MOS element 101b, and the doped region 108 It is a base end which is common to the MOS devices 101a and 101b. The contact window 110 commonly connects the source 106a, the doped region 108, and the source 106b in a manner of vertical gate structures 102a, 102b.

However, such a design in which the strip-shaped MOS devices 101a, 101b are connected in series by a plurality of contact windows 110 requires a large layout area and a large area of the occupied wafer. That is, such a layout tends to cause poor component accumulation, which is not only disadvantageous for wafer shrinkage but also requires high wafer cost. Therefore, how to find other design methods to achieve a small layout area under a limited wafer area, and to enable semiconductor components to maintain a certain level of component performance, will be an extremely important issue at present.

In view of the above, the present invention provides a semiconductor device having a small layout design and a method of fabricating the same.

The present invention provides a semiconductor device including a substrate having a first conductivity type, a first doping region having a second conductivity type, at least one second doping region having a first conductivity type, and a second conductivity type A three-doped region, a gate structure, and at least one contact window. The first doped region and the second doped region are disposed in the substrate, and the first doped region surrounds the periphery of each of the second doped regions. The third doped region is disposed in a substrate other than the first doped region. The gate structure is disposed on the substrate between the first doped region and the third doped region. The contact window is disposed on the substrate, and each contact window alternately connects the first doped region and the second doped region in a parallel gate structure.

In an embodiment of the invention, each of the contact windows alternately connects at least three connected first doped regions and second doped regions in a parallel gate structure.

In one embodiment of the invention, when the semiconductor component includes a plurality of second doped regions, the second doped regions are arranged in a parallel gate structure.

In one embodiment of the invention, when the semiconductor component includes a plurality of contact windows, the contact windows are arranged in a parallel gate structure.

In an embodiment of the invention, the first doped region is a common source of the semiconductor component and another adjacent semiconductor component.

In an embodiment of the invention, the semiconductor component is a MOS device.

In an embodiment of the invention, the semiconductor component is a high voltage component or a low voltage component.

In an embodiment of the invention, a bi-carrier bonded transistor is further included, wherein the bi-carrier bonding transistor shares a contact window with the semiconductor component. The bipolar junction transistor and the semiconductor element share, for example, a second doped region and a third doped region. The semiconductor component can be a sidewall metal MOS (sidewall MOS) component.

In an embodiment of the invention, when the first conductivity type is a P type, the second conductivity type is an N type; when the first conductivity type is an N type, the second conductivity type is a P type.

The present invention provides a semiconductor device including a substrate having a first conductivity type, a first doping region having a second conductivity type, at least one second doping region having a first conductivity type, and a second conductivity type A three-doped region, a gate structure, and at least one contact window. The first doped region and the second doped region are disposed in the substrate. The third doped region is disposed in a substrate other than the first doped region. The gate structure is disposed on the substrate between the first doped region and the third doped region. The contact window is disposed on the substrate, and each contact window alternately connects at least three connected first doped regions and second doped regions in a parallel gate structure.

In one embodiment of the invention, when the semiconductor component includes a plurality of second doped regions, the second doped regions are arranged in a parallel gate structure. In one embodiment of the invention, when the semiconductor component includes a plurality of contact windows, the contact windows are arranged in a parallel gate structure.

In an embodiment of the invention, the first doped region is a common source of the semiconductor component and another adjacent semiconductor component.

In an embodiment of the invention, the semiconductor component is a MOS device.

In an embodiment of the invention, the semiconductor component is a high voltage component or a low voltage component.

In an embodiment of the invention, a bi-carrier bonded transistor is further included, wherein the bi-carrier bonding transistor shares a contact window with the semiconductor component. The bipolar junction transistor and the semiconductor element share, for example, a second doped region and a third doped region. The semiconductor component can be a sidewall metal oxide semiconductor component.

In an embodiment of the invention, when the first conductivity type is a P type, the second conductivity type is an N type; when the first conductivity type is an N type, the second conductivity type is a P type.

The present invention further provides a method of fabricating a semiconductor device. A substrate having a first conductivity type is provided and a gate structure is formed on the substrate. A first doped region and a second doped region having a second conductivity type are respectively formed in the substrates on both sides of the gate structure. At least one third doped region having a first conductivity type is formed in the substrate. Thereafter, at least one contact window is formed on the substrate, and each contact window alternately connects at least three connected first doped regions and third doped regions in a parallel gate structure.

In an embodiment of the invention, the first doped region surrounds the periphery of each of the second doped regions.

In an embodiment of the invention, when the first conductivity type is a P type, the second conductivity type is an N type; when the first conductivity type is an N type, the second conductivity type is a P type.

Based on the above, the semiconductor device of the present invention surrounds each of the second doped regions by surrounding the first doped region in the source region, and configures the contact window in a parallel gate structure to connect at least three conductive patterns. And the connected first and second doped regions can thus reduce the layout area of the source region to obtain a smaller component size.

Furthermore, the method of fabricating the semiconductor device of the present invention can be applied to all MOS structures, and the process is simple and can be integrated with existing semiconductor processes.

The above described features and advantages of the present invention will be more apparent from the following description.

Next, embodiments of the present invention will be described in further aspects and cross-sectional views. 2A is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along line II-II' of Fig. 2A. It should be noted that the following embodiment shows the first conductivity type in the P type and the second conductivity type in the N type, but the invention is not limited thereto. Those skilled in the art will appreciate that the present invention may also replace the first conductivity type with an N type and the second conductivity type with a P type to form a semiconductor element. Referring to FIGS. 2A and 2B, the semiconductor device 201 of the present invention is, for example, a metal-oxide semiconductor (MOS) device disposed on a substrate 200 having a first conductivity type. Substrate 200 is, for example, a P-type substrate, which may be a germanium substrate or other semiconductor substrate. In an embodiment, a P-type well region (not shown) may also be disposed in the substrate 200. The semiconductor component 201 includes a gate structure 204, a drain region 206, a source region 208, and a contact window 210.

The gate structure 204 is located on the substrate 200 between the drain region 206 and the source region 208. The gate structure 204 includes a gate 204a and a gate dielectric layer 204b. The gate dielectric layer 204b is disposed between the gate 204a and the substrate 200. In one embodiment, the gate structure 204 is arranged in an elongated structure extending in the Y direction. The material of the gate 204a is, for example, doped polysilicon. The material of the gate dielectric layer 204b is, for example, hafnium oxide.

The drain region 206 includes a doped region 206a disposed in the substrate 200 on one side of the gate structure 204. The doped region 206a has a second conductivity type, which is, for example, an N+ doped region. In an embodiment, the layout of the doped regions 206a is an elongated structure extending in the Y direction.

The source region 208 is, for example, disposed separately from the drain region 206. The source region 208 includes a doped region 208a and at least one doped region 208b disposed in the substrate 200 on the other side of the gate structure 204. Doped regions 208a surround the perimeter of each doped region 208b.

In view of the above, the doped region 208a has a second conductivity type, which is, for example, an N+ doped region. In an embodiment, the layout of the doped regions 208a is an elongated structure extending in the Y direction. Doped region 208b has a first conductivity type, which is, for example, a P+ doped region. The bottom of the doped region 208b is electrically connected to the substrate 200, for example, as an external end of the substrate 200. When the source region 208 includes a plurality of doped regions 208b, the doped regions 208b are, for example, dispersedly disposed in the source region 208. In one embodiment, the plurality of doped regions 208b are arranged in a parallel gate structure 204. That is, the layout of the plurality of doped regions 208b is arranged along the Y direction.

The contact window 210 is disposed within the source region 208. The contact window 210 connects at least three alternating and connected doped regions 208a and doped regions 208b in a parallel gate structure 204 for connection to an external circuit. In detail, the layout of the contact window 210 is, for example, arranged along the Y direction, and at least three connected doped regions are connected in the Y direction, wherein at least three connected doped regions are doped by the doped region 208a. The doped regions 208b are formed and connected together to the same contact window 210 in a conductive configuration. In addition, at least one contact window (not shown) is also disposed in the drain region 206 to connect the doped region 206a for connection with an external circuit. The material of the contact window 210 is, for example, a metal or other suitable conductor material.

It is explained here that since the doping region 208a and the doping region 208b are simultaneously connected by the contact window 210 as a common bonding contact, that is, the doping region 208a and the doping region 208b are connected by using a sharing rule. Therefore, the source terminals of the semiconductor elements 201 will have the same potential as the substrate terminals. In addition, in the embodiment of the present invention, the doping region 208b used as the substrate end is disposed in the source region 208 in a block-like manner, and the periphery of the doping region 208b is doped as a source terminal. Area 208a is surrounded. Since the contact window 210 simultaneously connects the doping region 208a and the doping region 208b along the Y direction, the layout design of the source region 208 can be reduced. As such, the semiconductor component 201 of one embodiment of the present invention has a smaller component size than conventional semiconductor structures.

3 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention. In FIG. 3, the same members as those in FIG. 2A are denoted by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 3, the main components constituting the semiconductor element 201a are substantially the same as the main components constituting the semiconductor element 201 shown in FIG. 2A, but the difference between the two is mainly that the semiconductor element 201a includes a plurality of contact windows 210a. The plurality of contact windows 210a are arranged in the Y direction, for example, in the manner of parallel gate structures 208. Each contact window 210a extends in the Y direction and connects three alternating and connected doped regions 208a and doped regions 208b for connection to an external circuit. When the semiconductor element 201a has a plurality of contact windows 210a, the plurality of contact windows 210a, for example, form a discontinuous structure connecting the doped regions 208a and the doped regions 208b along the Y direction on the source regions 208.

As shown in FIG. 3, each contact window 210a is, for example, sequentially connected to three adjacent doped regions 208a, doped regions 208b, and doped regions 208a. In an embodiment, each contact window 210a may also sequentially connect three adjacent doped regions 208b, doped regions 208a, and doped regions 208b. Of course, in other embodiments, when there are multiple contact windows 210a, each contact window 210a may also be connected to at least three alternating and connected doped regions 208a and doped regions 208b, and the present invention does not impose any restrictions thereon. .

Next, the semiconductor element of the present invention will be described in detail by taking two elements as an example. It is to be noted that the embodiments described below are mainly intended to enable those skilled in the art to implement the present invention, but are not intended to limit the scope of the present invention, and the present invention does not particularly limit the number and arrangement of the components. 4 and 5 are top plan views, respectively, of a semiconductor device in accordance with another embodiment of the present invention. In FIGS. 4 and 5, the same members as those in FIGS. 2A and 3 are denoted by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 4, in an embodiment, adjacent semiconductor elements 201 and semiconductor elements 202 are disposed on substrate 200 at the same time. The structure of the semiconductor element 202 is, for example, the same as that of the semiconductor element 201. The semiconductor device 202 includes a gate structure 204, a drain region 206, a source region 208, and a contact window 210, and the component configuration of the semiconductor element 202 is also the same as that of the semiconductor device 201. Specifically, as shown in FIG. 4, the source region 208 is located between two adjacent semiconductor elements 201 and the two gate structures 204 of the semiconductor device 202, so that the two adjacent semiconductor devices 201, 202 share the source. Polar region 208. That is, the two adjacent semiconductor elements 201, 202 share the doped region 208a, the doped region 208b, and the contact window 210 connecting the doped regions.

Referring to FIG. 5, in another embodiment, adjacent semiconductor elements 201a and semiconductor elements 202a are disposed on the substrate 200 at the same time. It is explained here that the main components constituting the semiconductor element shown in FIG. 5 are substantially the same as the main components constituting the semiconductor element shown in FIG. 4, but the difference between the two is mainly because the semiconductor elements 201a, 202a respectively include Contact windows 210a.

In FIGS. 4 and 5, by using the arrangement of the doping regions 208a, 208b and the contact window 210 or 210a to reduce the size of each element, two semiconductor elements are simultaneously disposed on the substrate 200, and the two phases are made. The adjacent elements share the source region 208 and thus may also help to further reduce the area of use of the wafer.

Further, the above-described semiconductor element is, for example, a high voltage element or a low voltage element. When the semiconductor element is used as a high voltage element, its operating voltage is, for example, about 10-120V. When the semiconductor element is used as a low voltage element, it is operated, for example, under a normal voltage (about 2.5 to 5.0 V). The high voltage component may be a dynamic threshold metal-oxide semiconductor (DTMOS) device, a field drift metal-oxide semiconductor (FDMOS) device, or a double-diffused germanium oxide semiconductor (double). Diffuse drain metal-oxide semiconductor, DDDMOS). Next, an embodiment of the semiconductor element of the present invention as a high voltage element will be further described in a sectional view or a top view.

6A, 6B and 7 are schematic cross-sectional views showing a semiconductor device in accordance with another embodiment of the present invention. In FIGS. 6A, 6B, and 7, the same members as those in FIG. 2B and FIG. 4 are denoted by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 6A, the semiconductor device can be used as the high voltage device 601, 602, which is, for example, a field drift metal-oxide semiconductor (FDMOS) device. The high voltage elements 601, 602 are, for example, similar to the semiconductor elements 201, 202 as shown in FIG. 4, however, the difference between the two is mainly in the gate structure 604, and the high voltage elements 601, 602 further include the isolation structure 612 and have the second conductive Type well area 614.

Gate structure 604 is located on substrate 200 between drain region 206 and source region 208. The gate structure 604 includes a gate 604a, a gate dielectric layer 604b, and a spacer 604c. The gate dielectric layer 604b is disposed between the gate 604a and the substrate 200, and the spacer 604c is disposed on the sidewalls of the gate 604a and the gate dielectric layer 604b.

The isolation structure 612 is disposed between the gate structure 604 and the doped region 206a. In an embodiment, the gate 604a on the side adjacent to the drain region 206 will overlie a portion of the isolation structure 612, respectively. The isolation structure 612 is, for example, a field oxide layer (FOX) structure or a shallow trench isolation (STI) structure.

The well region 614 is disposed in the substrate 200 of the drain region 206, and the doped region 206a is disposed, for example, within the well region 614. In an embodiment, the well region 614 may also extend from the drain region 206 to the underlying substrate 200 of the partial gate structure 604. Well zone 614 is, for example, a high pressure N-type well zone (HVNW).

In view of the above, by configuring the isolation structure 612 and the well region 614 to be used to mitigate the hot carrier effect, the breakdown voltage of the drain region 206 and the source region 208 can be increased.

Referring to FIG. 6B, in another embodiment, the well region 614 having the second conductivity type in the high voltage elements 601a, 602a may also be changed to have a second conductivity type grade 616 and a second conductivity type, respectively. The drift zone (drift) 618.

The terrace 616 is disposed in the substrate 200 of the drain region 206 to surround the periphery of the doped region 206a. The terrace 616 is, for example, an N-type terrace. The drift region 618 is disposed under the partial isolation structure 612, and the drift region 618 is electrically connected to the gate structure 604 and the step region 616. The drift region 618 is, for example, an N-type drift region.

Referring to FIG. 7, the semiconductor element can be used as the high voltage element 701, 702, which is, for example, a double diffused drain metal-oxide semiconductor (DDDMOS). The high voltage elements 701, 702 are, for example, similar to the semiconductor elements 201, 202 as shown in FIG. 4, however, the difference between the two is mainly in the gate structure 704, and the high voltage elements 701, 702 further include the second conductivity type. 712.

Gate structure 704 is located on substrate 200 between drain region 206 and source region 208. The gate structure 704 includes a gate 704a, a gate dielectric layer 704b, and a spacer 704c. The gate dielectric layer 704b is disposed between the gate 704a and the substrate 200, and the spacer 704c is disposed on the sidewalls of the gate 704a and the gate dielectric layer 704b.

The step region 712 is disposed in the substrate 200 of the drain region 206, and the doped region 206a is disposed, for example, within the step region 712. In an embodiment, the step 712 may also extend from the drain region 206 to the underlying substrate 200 of the partial gate structure 704. The step region 712 is, for example, a high voltage N-type step region (HVNG).

Figure 8 is a top plan view showing the layout of a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 8, a semiconductor component can be used as the high voltage component 800, which is, for example, a power supply (high power) component. For the layout, a basic unit is constituted by, for example, four regular quadrilateral elements in Fig. 8, but the present invention does not impose any limitation on the number and shape of the elements. In the present embodiment, the four high voltage components 800 each have four individual drain regions 802 that are separately disposed, for example, in a 2x2 array. The distribution of gate structures 804 is, for example, around individual drain regions 802, and the four gate structures 804 are also spaced apart from one another. That is, the individual drain regions 802 have individual gate structures 804 that can be individually configured for use. The source region 806 is distributed, for example, around the outside of the four gate structures 804.

For a single high voltage component 800, the gate structure 804 and the source region 806 are disposed, for example, in a manner surrounding the perimeter of the drain region 802. That is, the gate structure 804 generally surrounds the drain region 802, while the source region 806 is substantially distributed around the outer circumference of the gate structure 804. Furthermore, as shown in FIG. 8, the source region 806 is located between the gate structures 804 of adjacent two high voltage components 800, such that adjacent high voltage components 800 share this source region 806.

In an embodiment, the drain region 802 includes a doped region having a second conductivity type disposed in a substrate having a first conductivity type. The source region 806 includes a doped region 806a having a second conductivity type and a doped region 806b having a first conductivity type disposed in the substrate. In source region 806, doped region 806a surrounds the perimeter of each doped region 806b. In one embodiment, the arrangement of doped regions 806b surrounds the outer circumference of gate structure 804 in a manner that is parallel to each side of gate structure 804. The gate structure 804 located in the drain region 802 and the source region 806 is disposed on the substrate.

Contact window 808 is disposed within source region 806. The contact window 808 connects at least three alternating and connected doped regions 806a and doped regions 806b in a parallel gate structure 804 for connection to an external circuit. That is, the doped region 806a and the doped region 806b are connected together by the conductor contact window 808 using a sharing rule. As shown in FIG. 8, in the case of a single high voltage component 800, the contact window 808 is continuously wound around the outer circumference of the gate structure 804, for example, in the manner of the sides of the parallel gate structure 804, thereby doping the periphery of the gate structure 804. Region 806a is fully coupled to doped region 806b. Additionally, there may be at least one contact window within each of the drain regions 802 for connection to an external circuit.

In addition, in another embodiment, a plurality of contact windows may be formed as a discontinuous structure, intermittently surrounding the outer ring of the gate structure 804 in a manner parallel to each side of the gate structure 804, and at least three conductive portions are segmentally connected. The doped regions 806a and doped regions 806b are alternately and connected. The present invention does not particularly limit the number of contact windows and the number of doped regions to which the respective contact windows are connected.

In an embodiment, the semiconductor component further includes a bipolar junction transistor (BJT). That is, the semiconductor element is, for example, integrated on the same wafer by the above MOS structure and the bipolar bonding transistor. Figure 9 is a cross-sectional view showing a semiconductor device in accordance with another embodiment of the present invention. It should be noted that the following embodiments represent the first conductivity type in the N type and the second conductivity type in the P type, but the invention is not limited thereto. It will be appreciated by those skilled in the art that the present invention can also replace the first conductivity type with a P type and the second conductivity type with an N type to form a semiconductor element.

Referring to FIG. 9, in an embodiment, the semiconductor device includes a substrate 900 having a first conductivity type, a MOS device 901, and a bipolar bonding transistor 902. The base 900 has a protruding platform portion 900a thereon. The substrate 900 is, for example, an N+ type substrate. In an embodiment, a doped region 906 having a first conductivity type and a doped region 908 having a second conductivity type are disposed in the substrate 900. The doped region 906 is, for example, an N-doped region disposed in the substrate 900 to serve as a body of the MOS device 901. The doped region 908 is, for example, a P-doped region disposed within the doped region 906, and the doped region 908 is substantially distributed in the protruding land portion 900a.

The MOS device 901 includes a gate structure 910, a drain region 912, a source region 914, and a contact window 916. In an embodiment, the MOS device 901 may be a sidewall MOS device. The gate structure 910 is on the substrate 900 between the drain region 912 and the source region 914, and the gate structure 910 is, for example, partially covered on the land portion 900a and its sidewalls. The gate structure 910 includes a gate 910a and a gate dielectric layer 910b. The gate dielectric layer 910b is disposed between the gate 910a and the substrate 900. The drain region 912 includes a doped region 912a disposed in the substrate 900 on one side of the gate structure 910. The doped region 912a has a second conductivity type, which is, for example, a P+ doped region to serve as the 汲 terminal of the MOS element 901. The source region 914 includes a doped region 914a and at least one doped region 914b disposed in the substrate 900 on the other side of the gate structure 910. In the following, a plurality of doped regions 914b will be exemplified, which are mainly for the purpose of enabling those skilled in the art to implement the present invention, but are not intended to limit the scope of the present invention. Doped regions 914a surround the perimeter of each doped region 914b, and a plurality of doped regions 914b are arranged in a parallel gate structure 910. The doped region 914a has a second conductivity type, which is, for example, a P+ doped region to serve as a source terminal of the MOS element 901. The doped region 914b has a first conductivity type, which is, for example, an N+ doped region to serve as a base end of the connection substrate 900. Contact window 916 is disposed within source region 914. Contact window 916 connects at least three alternating and connected doped regions 914a and doped regions 914b in parallel gate structure 910 for connection to external circuitry.

A doped region 918 having a first conductivity type is further included in the protruding land portion 900a. Doped region 918 is, for example, an N+ doped region disposed within doped region 908. As such, the doped regions 918, 908, 912a, 906, 914b form a vertical npn bipolar junction transistor 902. In detail, the doping region 918 is, for example, an emitter of the bipolar junction transistor 902, and the doping regions 908, 912a are, for example, commonly used as the base of the bipolar junction transistor 902. The doped regions 906, 914b are, for example, collectively used as a collector of the bi-carrier junction transistor 902.

In one embodiment, when the MOS device 901 and the bipolar bonding transistor 902 are integrated into the same wafer, the MOS device 901 and the bipolar bonding transistor 902 are, for example, a common gate structure 910 and a doped region. 912a, 914b. In addition, by connecting at least three alternating and connected doping regions 914a and doping regions 914b through the contact window 916, the source terminal (doping region 914a) of the MOS device 901 and the bipolar bonding transistor 902 can be bonded. The collector (doped region 914b) is electrically connected.

Specifically, in this embodiment, the layout design of the source region 914 may be a layout design of the source region 208 as shown in FIG. 2A or FIG. The doping region 914b is dispersedly arranged in the source region 914 along the arrangement direction of the parallel gate structure 910, and the periphery of the doping region 914b is surrounded by the doping region 914a having a different conductivity type, so that the contact The window 916 will simultaneously connect the doped region 914a and the doped region 914b along the arrangement direction of the parallel gate structure 910. Therefore, the use of the sharing rule to connect the doped region 914a and the doped region 914b formed by the special layout can help to reduce the layout design of the source region 914 to save the wafer area.

It is to be noted that the above-described embodiments may be combined with each other without being limited to the individual embodiments enumerated above. Furthermore, the present invention can be applied to the source region layout of all MOS structures to achieve the effect of reducing the size of components.

Of course, in other embodiments, adjacent semiconductor elements can also be designed with a common drain. That is to say, when the adjacent semiconductor elements share the drain, the layout design of the above embodiment for the source region can also be applied to the common drain region, so that the doped region as the drain is surrounded by the doping as the base end. Around the miscellaneous area.

11A and FIG. 12A are schematic top views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention. 11B and 12B are schematic cross-sectional views taken along line III-III' of Figs. 11A and 12A, respectively.

Referring to FIGS. 11A and 11B, a substrate 1100 having a first conductivity type, such as a P-type germanium substrate or an N-type germanium substrate, is provided. In an embodiment, a well region (not shown) of the first conductivity type may also be formed in the substrate 1100. Then, a dielectric layer and a conductor layer are sequentially formed on the surface of the substrate 1100. The method of forming the dielectric layer is, for example, performing a thermal oxidation process to form a ruthenium oxide layer. The material of the conductor layer is, for example, doped polysilicon, and the formation method thereof is, for example, a chemical vapor deposition method. Thereafter, the dielectric layer and the conductor layer are patterned to form gate dielectric layers 1102a, 1102b and gates 1104a, 1104b. The gate dielectric layer 1102a and the gate 1104a form a gate structure 1106a, and the gate dielectric layer 1102b and the gate 1104b form a gate structure 1106b. Thereafter, doped regions 1108a, 1108b, 1110 having a second conductivity type are formed in the substrate 1100 on both sides of the gate structures 1106a, 1106b, respectively. The doped regions 1108a, 1108b are, for example, the drains of the two semiconductor elements, respectively, and the doped region 1110 is, for example, a common source between two adjacent semiconductor elements.

Referring to FIGS. 12A and 12B, at least one doped region 1112 having a first conductivity type is formed in the substrate 1100 between the gate structures 1106a, 1106b. The doped region 1110 is, for example, surrounding the periphery of each doped region 1112. When a plurality of doped regions 1112 are formed, the plurality of doped regions 1112 are aligned along the direction of the parallel gate structures 1106a, 1106b. The doped region 1112 is, for example, an external end of the substrate 1100. Thereafter, a contact window 1114 is formed on the surface of the substrate 1100, for example, over the doped regions 1110, 1112. Contact window 1114 connects at least three alternating and connected doped regions 1110 and doped regions 1112 in a configuration of parallel gate structures 1106a, 1106b as a common contact window.

In particular, in the above embodiment, the description has been made by forming two semiconductor elements and the two adjacent semiconductor elements share the source. However, the present invention is not limited thereto. Those skilled in the art can adjust the process according to requirements, so the details are not described herein.

In order to confirm that the layout design of the semiconductor device of the present invention does not degrade the device performance, the characteristics will be described experimentally. The following experimental examples are merely illustrative of the effect of the layout design of the semiconductor device of the present invention on the gate voltage and current, but are not intended to limit the scope of the present invention.

Experimental example

Figure 10 is a graph showing the relationship between the drain voltage (V _D ) and the drain current (I _D ) according to an experimental example of the present invention.

In this experimental example, a gate voltage of the semiconductor device of the present invention and a gate of a conventional semiconductor device are respectively applied with different gate voltages (V _g ), and voltages (V _D ) and currents (I _D ) are measured at the 汲 extremes _. ), the results of which are shown in FIG. 10, the same applied gate voltage (V _g), the semiconductor device of the present invention and the conventional semiconductor device may have the same IV curve. Further, even if the applied gate voltage (V _g ) is changed, the semiconductor element of the present invention has the same IV curve as the conventional semiconductor element. As can be seen from the experimental examples, the semiconductor device of the present invention achieves the effect of reducing the size of the device by a special layout design, and the layout design does not affect the electrical properties of the device, and the semiconductor device of the present invention can be stably maintained. efficacy.

In summary, the semiconductor device of one embodiment of the present invention can be connected to at least three conductive patterns alternately and connected in a parallel gate structure by changing the doping region layout configuration of the source region. The doped regions can therefore help to reduce the layout area of the source regions.

In addition, the method of fabricating the semiconductor device of one embodiment of the present invention can be applied to all MOS structures, and can be integrated with the existing process through the change of the mask pattern, the process is simple, and unnecessary waste of the wafer area can be avoided.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 900, 1100. . . Base

101a, 101b, 901. . . Gold oxide semiconductor component

102a, 102b, 204, 604, 704, 804, 910, 1106a, 1106b. . . Gate structure

104a, 104b. . . Bungee

106a, 106b. . . Source

108, 206a, 208a, 208b, 806a, 806b, 906, 908, 912a, 914a, 914b, 918, 1108a, 1108b, 1110, 1112. . . Doped region

110, 210, 210a, 808, 916, 1114. . . Contact window

201, 201a, 202, 202a. . . Semiconductor component

204a, 604a, 704a, 910a, 1104a, 1104b. . . Gate

204b, 604b, 704b, 910b, 1102a, 1102b. . . Gate dielectric layer

206, 802, 912. . . Bungee area

208, 806, 914. . . Source area

601, 601a, 602, 602a, 701, 702, 800. . . High voltage component

604c, 704c. . . Clearance wall

612. . . Isolation structure

614. . . Well area

616, 712. . . Stage

618. . . Drift zone

900a. . . Platform department

902. . . Double carrier bonding transistor

1A is a top plan view of a conventional semiconductor device.

Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A.

2A is a top plan view of a semiconductor device in accordance with an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view taken along line II-II' of Fig. 2A.

3 is a top plan view of a semiconductor device in accordance with another embodiment of the present invention.

4 and 5 are top plan views, respectively, of a semiconductor device in accordance with another embodiment of the present invention.

6A, 6B and 7 are schematic cross-sectional views showing a semiconductor device in accordance with another embodiment of the present invention.

Figure 8 is a top plan view showing the layout of a semiconductor device in accordance with another embodiment of the present invention.

Figure 9 is a cross-sectional view showing a semiconductor device in accordance with another embodiment of the present invention.

Figure 10 is a graph showing the relationship between the drain voltage (V _D ) and the drain current (I _D ) according to an experimental example of the present invention.

11A and FIG. 12A are schematic top views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

11B and 12B are schematic cross-sectional views taken along line III-III' of Figs. 11A and 12A, respectively.

204. . . Gate structure

206a, 208a, 208b. . . Doped region

210. . . Contact window

201, 202. . . Semiconductor component

206. . . Bungee area

208. . . Source area

Claims (24)

A semiconductor device comprising: a substrate having a first conductivity type; a first doped region having a second conductivity type disposed in the substrate; and at least a second doping having the first conductivity type a region disposed in the substrate, the first doping region surrounding the periphery of each of the second doping regions; and a third doping region having the second conductivity type, the substrate disposed outside the first doping region a gate structure disposed on the substrate between the first doped region and the third doped region; and at least one contact window disposed on the substrate, each of the contact windows being parallel to the gate The first doped region and the second doped region are alternately connected in a structured manner. The semiconductor device of claim 1, wherein each of the contact windows alternately connects at least three connected first doped regions and the second doped region in parallel with the gate structure. The semiconductor device of claim 1, wherein when the semiconductor device comprises a plurality of second doped regions, the second doped regions are arranged in parallel with the gate structure. The semiconductor component according to claim 1, wherein when the semiconductor component comprises a plurality of contact windows, the contact windows are arranged in parallel with the gate structure. The semiconductor device of claim 1, wherein the first doped region is a common source of the semiconductor device and another adjacent semiconductor device. The semiconductor device according to claim 1, wherein the semiconductor device is a MOS device. The semiconductor component of claim 1, wherein the semiconductor component is a high voltage component or a low voltage component. The semiconductor device of claim 1, further comprising a dual carrier bonding transistor, wherein the bipolar bonding transistor shares the contact window with the semiconductor device. The semiconductor device of claim 8, wherein the bipolar junction transistor shares the second doped region and the third doped region with the semiconductor device. The semiconductor component of claim 8, wherein the semiconductor component is a sidewall MOS device. The semiconductor device according to claim 1, wherein when the first conductivity type is a P type, the second conductivity type is an N type; when the first conductivity type is an N type, the second conductivity type For the P type. A semiconductor device comprising: a substrate having a first conductivity type; a first doped region having a second conductivity type disposed in the substrate; and at least a second doping having the first conductivity type a third doped region of the second conductivity type disposed in the substrate outside the first doped region; a gate structure disposed in the first doped region On the substrate between the third doped regions; and at least one contact window disposed on the substrate, each of the contact windows alternately connecting at least three connected first doped regions in a manner parallel to the gate structure And the second doped region. The semiconductor component according to claim 12, wherein when the semiconductor component comprises a plurality of second doped regions, the second doped regions are arranged in parallel with the gate structure. The semiconductor component according to claim 12, wherein when the semiconductor component comprises a plurality of contact windows, the contact windows are arranged in parallel with the gate structure. The semiconductor device of claim 12, wherein the first doped region is a common source of the semiconductor device and another adjacent semiconductor device. The semiconductor component of claim 12, wherein the semiconductor component is a metal oxide semiconductor component. The semiconductor component of claim 12, wherein the semiconductor component is a high voltage component or a low voltage component The semiconductor device of claim 12, further comprising a dual carrier bonding transistor, wherein the bipolar bonding transistor shares the contact window with the semiconductor device. The semiconductor device of claim 18, wherein the bipolar junction transistor shares the second doped region and the third doped region with the semiconductor device. The semiconductor component of claim 18, wherein the semiconductor component is a sidewall MOS device. The semiconductor device of claim 12, wherein when the first conductivity type is a P type, the second conductivity type is an N type; and when the first conductivity type is an N type, the second conductivity type For the P type. A method of manufacturing a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a gate structure on the substrate; forming a second conductivity type in the substrate on both sides of the gate structure a first doped region and a second doped region; forming at least one third doped region having the first conductivity type in the substrate; and forming at least one contact window on the substrate, each of the contact windows The at least three connected first doped regions and the third doped region are alternately connected in parallel with the gate structure. The method of fabricating a semiconductor device according to claim 22, wherein the first doped region surrounds the periphery of each of the second doped regions. The semiconductor device of claim 22, wherein when the first conductivity type is a P type, the second conductivity type is an N type; and when the first conductivity type is an N type, the second conductivity type For the P type.