TWI466199B - Wafer level clip and process of manufacture - Google Patents

Description

Packaging method with wafer size patch

The present invention relates to a semiconductor packaging method, and more particularly to a packaging method having a wafer size patch.

In the semiconductor manufacturing process, a plurality of circuit structures are usually fabricated on one wafer, then the wafer is diced, the wafer is divided into individual wafers, and each wafer is connected to the substrate by a package process such as patch bonding for various products. Production and production.

As disclosed in Chinese Patent Publication No. CN 1945805A, a semiconductor packaging method is disclosed which includes the following steps: First, a wiring substrate having a first surface and a second surface is provided. Next, a solventless double-stage thermosetting compound is formed on the first surface of the line substrate. Then, the solventless double-stage thermosetting compound is partially cured to form a solvent-free B-stage adhesive layer on the first surface of the wiring substrate. Thereafter, the wafer is adhered to the first surface of the wiring substrate using the B-stage adhesive layer. Thereafter, the wafer is electrically connected to the wiring substrate, and then a sealing material is formed to seal the wafer. The invention also provides a carrier that can be applied to the above packaging method.

Further, as disclosed in Chinese Patent Publication No. CN1713362A, a semiconductor package structure and a method of fabricating the same are disclosed. The semiconductor package structure mainly includes a substrate and a semiconductor element and a flip chip connection disposed on the substrate. The semiconductor package structure of the present invention comprises a connection structure disposed between the semiconductor element and the substrate and extending only along an edge of the bottom surface of the semiconductor element for fixing the semiconductor element to the substrate, wherein the connection structure is formed by curing an adhesive. The connection structure has a fixing and supporting function, and can reduce stress between the semiconductor element and the substrate, so that the package structure is not affected by high stress and is peeled off. The semi-guide a method of packaging a semiconductor device on a substrate; connecting the semiconductor device to the substrate in a flip chip connection; coating an adhesive along an edge of the bottom surface of the semiconductor chip package structure to form at least one between the bottom edge of the semiconductor device and the substrate An adhesive structure; and curing the adhesive structure, thereby further fixing the semiconductor component to the substrate.

The above-described prior art package firstly dicing the semiconductor elements on the wafer, then placing the respective semiconductor elements on the substrate, drawing the semiconductor element electrodes through the leads, and then molding the semiconductor elements. The package cuts the wafer from the beginning, and then connects and encapsulates the electrodes of the semiconductor element. The process is numerous, and the individual package of each semiconductor element increases the volume of the package, and the cost of the package increases. In addition, the electrode of the semiconductor element The coating is encapsulated in the package, so that the heat dissipation performance of the semiconductor element is deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wafer size chip package method for drawing a top electrode of each wafer on a wafer through a wafer size patch, then molding the wafer size, and then grinding through the bottom of the wafer. Exposing the bottom electrode of the wafer wafer and finally cutting it simplifies the packaging process, reduces the package size of the wafer, and reduces the packaging cost; the electrodes of the wafer are exposed outside the package, which improves the heat dissipation performance of the wafer. The bottom grinding of the wafer reduces the substrate resistance of the wafer, and the internal interconnection of the chip makes the performance of the wafer more stable and reliable.

In order to achieve the above object, the technical solution of the present invention is: a package method having a wafer size patch, comprising: providing a wafer having a wafer top and a wafer bottom, wherein the crystal The dome portion is formed with a plurality of wafers, and a groove region corresponding to the wafer is disposed between the wafers at the top of the wafer, and a surface of each wafer is provided with a plurality of wafer top electrode contact regions; a patch is provided, and the sticker is provided The sheet is provided with a region corresponding to each wafer on the wafer, and in each region, the patch has a plurality of patch contact regions corresponding to the wafer top electrode contact regions, and the patch further has The patch connected to the patch contact area is connected to the rib, and the patch grows downwardly The square body ribs; the chip contact area is connected to the top electrode contact area of the wafer, and the patch ribs are disposed in the groove area of the wafer; and a plastic package is provided to encapsulate the top of the wafer, the wafer and the patch.

The above package method with a wafer size patch further includes thinning the bottom of the wafer until the bottom surface of the wafer is in the same plane as the bottom surface of the patch rib disposed in the groove region of the wafer.

The above package method with a wafer size patch further includes forming a bottom electrode contact region on the bottom surface of the wafer.

The above packaging method with a wafer size patch further includes cutting the entire plasticized wafer to obtain a molded body of each wafer.

The above packaging method with a wafer size patch, wherein at least one of the top electrode contact regions is formed into a plurality of partitions.

The above packaging method with a wafer size patch, wherein at least one of the patch contact regions is formed into a plurality of partitions.

A packaging method with a wafer size patch, comprising the following steps: Step 1: providing a wafer, fabricating a plurality of wafers on the wafer, the plurality of wafers having a plurality of top electrode contact regions and a bottom electrode contact region Step 2: etching a plurality of groove regions on the wafer; Step 3: providing a patch, the patch comprising a plurality of patch contact regions and a plurality of patch ribs connected to the patch contact regions, Bonding the patch contact area to the wafer electrode contact area while placing the patch ribs in the recessed area of the wafer; Step 4: molding the packaged wafer top, wafer and patch; step 5: aligning the crystal The bottom of the circle is thinned to form an electrode of the contact area at the bottom of the wafer; Step 6: The entire molded body of the plurality of wafers is cut to obtain a molded body of each wafer.

The above package method with a wafer size patch, wherein the step 5 further includes Next step: Step 5.1: Metal deposition at the bottom of the wafer; Step 5.2: Mask the bottom of the wafer to protect the exposed wafer electrodes at the bottom of the wafer.

The above package method with a wafer size patch, wherein in the step 3, the patch further comprises a patch frame, the patch frame dividing the patch into corresponding to each wafer on the wafer Various areas.

The above packaging method with a wafer size patch, wherein, in the step 1, the method further comprises electroplating forming a plurality of wafer top electrode contact regions on each of the wafers.

In the above method for packaging a wafer size patch, in the step 3, the plurality of patch contact regions are disposed corresponding to the plurality of wafer electrode contact regions, and the plurality of patch contact regions are corresponding to the conductive bonding material. The plurality of wafer electrode contact regions are bonded together and extend through the patch ribs out of the electrode at the top contact area of the wafer.

In the above package method with a wafer size patch, in step 6, the electrode of the bottom contact region of the wafer exposed at the bottom of the thinned wafer is on the same plane as the bottom surface of the patch rib.

The above package method with a wafer size patch, wherein the wafer is a power semiconductor field effect transistor having a top contact region and a bottom contact region, and an electrode of a bottom contact region of the wafer is a drain, The electrodes in the top contact area of the wafer are respectively a source and a gate, and the source and the gate are extended by the patch ribs so that the source, the gate and the drain of the wafer are on the same plane.

The above packaging method having a wafer size patch, wherein the groove region divides a plurality of wafers into individual wafer units.

The package with the wafer size patch of the invention and the manufacturing method thereof have the following advantages and positive effects compared with the prior art by adopting the above technical solutions:

1. The present invention simplifies the process steps, saves packaging materials, and reduces the process by first mounting the wafers on the wafers, then performing the packaging and the division of the individual wafers on the wafer. The cost of packaging.

2. The present invention electrically connects the top electrodes of the respective wafers on the wafer through a wafer-sized patch, and extracts the top electrode of the wafer through the patch ribs disposed in the groove of the wafer, so that the electrodes of the wafer are in the wafer size. The area is coplanar, reducing the size of the chip package.

3. The present invention exposes the electrodes of the wafer by cutting or grinding the bottom of the wafer. On the one hand, the thickness of the wafer substrate is reduced, the substrate resistance of the wafer is lowered, and on the other hand, the electrodes of the wafer are exposed. The outer surface of the package improves the heat dissipation performance of the wafer.

The present invention provides a package having a wafer size patch comprising a wafer 1, a patch 2 and a molding 3.

As shown in FIGS. 1A and 1B, respectively, a side view of the wafer and a top view of the wafer, the wafer 1 having a wafer top 11 and a wafer bottom 12. A plurality of wafers 111 are formed on the top 11 of the wafer, and groove regions 112 are disposed between the wafers 111 at the top of the wafer 11. Each of the wafers 111 corresponds to a groove region 112, and adjacent groove regions are separated from each other. , can also extend the connection. In a preferred embodiment, the recessed regions 112 divide the plurality of wafers 111 into individual wafer units in both the longitudinal and transverse directions between the wafers 111. In another preferred embodiment, the recessed regions 112 are disposed in only one direction (not shown). The upper surface of each wafer is provided with a plurality of wafer top electrode contact regions 1111 and 1112. When the area of the top electrode contact area is large, a top electrode contact area can also be formed into a plurality of sections, such as the wafer top electrode contact area 1112 shown in FIGS. 1A and 1B. The bottom of the preferred wafer may be provided with a wafer bottom electrode or no bottom electrode. In a preferred embodiment, the wafer 111 is a power semiconductor field effect transistor having a top electrode and a bottom electrode, that is, the wafer top electrode contact region 1111 is the gate of the semiconductor field effect transistor, and the wafer top electrode contact region 1112 is a semiconductor. The source of the field effect transistor. In another preferred embodiment, all of the electrodes of wafer 111 are located on top of the wafer.

As shown in FIGS. 2A and 2B, a patch 2 includes a patch frame 21, a plurality of patch contact regions 22 connected to the patch frame 21, and a plurality of patches connected to the patch contact regions. Connected to the ribs 23. The patch frame 21 divides the patch 2 into respective regions corresponding to each wafer on the wafer. As shown in FIG. 2B, the patch ribs 23 are formed into rectangular ridges, and the patch ribs 23 have a patch rib bottom plane 231 which is parallel to the plane of the patch contact area. And the patch rib bottom plane 231 of each patch rib 23 is on the same plane. When the contact area of the patch is large, a patch contact area can be formed into a plurality of partitions, and each partition can be connected to the same patch, as shown in Figures 2A and 2B. In each of the regions, as shown in FIGS. 3A and 3B, a plurality of patch contact regions 22 and a plurality of wafer top electrode contact regions 1111 and 1112 are bonded by a conductive material, and a conductive material such as silver paste or tin is used. Solder paste, etc. A plurality of patch ribs 23 are correspondingly coupled to the wafer top electrode contact regions 1111, 1112 and disposed within the recess region 112. In a preferred embodiment, the wafer to which the patch is to be connected is a power semiconductor field effect transistor having a top electrode and a bottom electrode, the top electrode contact region 1111 of the wafer being the gate of the semiconductor field effect transistor, and the top electrode contact of the wafer Region 1112 is the source of the semiconductor field effect transistor. Since the patch rib 23 is connected to the patch contact region 22, the chip contact region 22 is connected to the gate and the source of the wafer, so that the patch ribs 23 respectively lead to the gate and the source of the top contact region of the wafer, that is, The gate and source of the wafer are exposed on the same plane as the bottom of the patch rib 23 and are disposed in the recessed region 112.

As shown in FIG. 4, a plastic package 3 molds the top of the wafer 1, the wafer and the chip 2, and the plastic body fills the gap between the chip 2 and the top of the wafer and the wafer, and is subjected to wafer molding to form a wafer. The entire package of dimensions. Since it is necessary to obtain a single package wafer in practical applications, it is also necessary to perform wafer bottom polishing on the entire package to expose the wafer electrode and the cutting of the package, as shown in Figures 5, 6, 7, and 8, specifically in the following fabrication method. A detailed description.

The present invention provides a method for fabricating a wafer size chip package, as shown in FIGS. 1 to 9 , comprising the steps of: providing a wafer 1 and fabricating a plurality of wafers 111 on the wafer 1 in one In a preferred embodiment, the plurality of wafers 111 are power semiconductor field effect transistors having a top electrode and a bottom electrode, the bottom electrode of the wafer is a drain, and the top electrodes of the wafer are respectively a source and a gate. pole. First, a plurality of groove regions 112 are etched on the wafer 1, and each of the wafers 111 corresponds to a groove region 112. In a preferred embodiment, the recessed regions 112 extend in the longitudinal and transverse directions between the wafers 111 to divide the plurality of wafers 111 into individual wafers. Then, Ni/Au plating is performed on the wafer top contact area of each wafer, a plurality of wafer top electrode contact regions 1111, 1112 are plated, and the top electrode contact region having a larger contact area is formed into a plurality of sections. It is of course also possible to perform Ni/Au plating before etching the plurality of recess regions 112, even if the wafer 1 itself is provided with the wafer top electrode contact regions 1111, 1112 and this step is omitted. Next, a conductive material such as silver paste, solder paste or the like is coated on the plurality of wafer top electrode contact regions 1111, 1112. Then, a patch 2 is provided. The patch 2 includes a patch frame 21, a plurality of patch contact regions 22, and a plurality of patch ribs 23 connected to the patch contact regions 22. The patch frame 21 facilitates the patch and the wafer. In alignment, the patch frame 21 separates the patches into respective regions corresponding to each wafer on the wafer. Conversely, the conductive material can also be pre-coated or printed on the patch contact area 22. In each of the regions, the patch contact region 22 is bonded to the wafer top electrode contact regions 1111, 1112 whose surface is coated with a conductive material, and the patch ribs 23 are formed into rectangular ridges in the recess region 112. The bottom plane of the patch tie 23 is parallel to the plane in which the patch contact area is located. Since the patch ribs 23 are electrically connected to the patch contact regions 22, and the patch contact regions 22 are bonded to the wafer top electrode contact regions 1111, 1112, the patch ribs 23 extend the wafer top electrode contact regions 1111, 1112 to The same plane is disposed in the recessed area 112. The wafer and the chip are then molded on the top 11 of the wafer for wafer molding. After molding, the bottom portion 12 of the wafer is thinned, for example, ground, or cut until the electrode 1113 of the bottom contact region of the wafer exposed at the bottom portion 12 of the wafer is on the same plane as the bottom surface of the patch rib 23. Grinding or cutting the bottom of the wafer exposes the electrodes at the bottom of the wafer on the one hand; on the other hand, a wafer such as 0.15 mm, 0.1 mm or even thinner is obtained, thereby reducing the substrate resistance, thereby obtaining better product performance. In a preferred embodiment, since the wafer is a power semiconductor field effect transistor having a top contact region and a bottom contact region, the electrode 1113 of the bottom contact region of the wafer is a drain, and the bottom surface of the patch via 23 is provided with an extension. The gate and source that come out, therefore, the source and gate of the wafer The poles and drains are in the same plane at the bottom of the wafer. Metal deposition is then performed at the bottom 12 of the wafer, and a mask etch is performed on the bottom of the wafer to protect the electrodes at the bottom contact area of the wafer exposed at the bottom of the wafer. When all of the electrodes of the packaged wafer are located at the top of the wafer, the step of fabricating the electrode at the bottom contact area of the wafer may be omitted. Finally, the entire plastic body of the plurality of wafers is cut to obtain a molded body of each of the wafers, and the bottom surface of the molded body of each of the wafers is respectively provided with a source, a gate and a drain, and the electrode can be connected to the substrate and radiated through the substrate. , enhance the heat dissipation performance of the wafer.

The invention has a wafer size chip package, and a groove area is reserved on the wafer for distinguishing each wafer, interconnecting through a wafer size patch, and extending the electrode of the wafer through the patch into the trench, first The overall package then performs a package cut of a single wafer, which simplifies the process flow, saves packaging material, and reduces the size of a single wafer package due to the tighter space between individual wafer packages throughout the package.

Of course, it is to be understood that the foregoing description has been described in connection with the preferred embodiments of the present invention, and many modifications of the invention are possible without departing from the spirit and scope of the appended claims.

The present invention is by no means limited to the details and methods shown in the above description or the drawings. The invention is capable of other embodiments and of various embodiments. In addition, you must also understand that the words and terms used herein and the abstracts are for the purpose of illustration only and are by no means limited.

As such, those skilled in the art will appreciate that the present invention is based on the teachings of the present invention as well as other structures, methods and systems. Therefore, it is essential that the scope of the appended claims be construed as including all such equivalents,

1‧‧‧ wafer

2‧‧‧SMD

3‧‧‧plastic body

11‧‧‧ Wafer top

12‧‧‧ wafer bottom

21‧‧‧SMD frame

22‧‧‧SMD contact area

23‧‧‧Strips

111‧‧‧ wafer

112‧‧‧ Groove area

231‧‧‧Spliced bottom plane

1111‧‧‧ wafer top electrode contact area

1112‧‧‧ wafer top electrode contact area

1113‧‧‧electrode

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

Figure 1A is a side view of the wafer structure of the present invention.

Figure 1B is a front elevational view of the wafer structure of the present invention.

Fig. 2A is a top view of the patch structure of the present invention.

Fig. 2B is a view showing the lower surface of the patch structure of the present invention.

Fig. 3A is a top view showing the placement of the patch on the top of the wafer in the present invention.

Fig. 3B is a side view showing the placement of the patch on the top of the wafer in the present invention.

Figure 4 is a side elevational view of the wafer and patch on top of the plastic wafer of the present invention.

Figure 5 is a side view of the molded body after the bottom of the wafer is ground according to the present invention.

Figure 6 is a view of the lower surface of the molded body after the bottom of the wafer is ground according to the present invention.

Figure 7 is a top plan view of the package structure of a single wafer obtained after cutting according to the present invention.

Figure 8 is a bottom view of the package structure of a single wafer obtained after cutting according to the present invention.

Figure 9 is a flow chart of the manufacturing method of the present invention.

Claims (14)

A packaging method with a wafer size patch, comprising: providing a wafer having a wafer top and a wafer bottom, forming a plurality of wafers on top of the wafer, and in the crystal a groove area corresponding to the plurality of wafers is disposed between the plurality of wafers of the dome portion, and a surface of each of the wafers is provided with a plurality of wafer top electrode contact regions; a patch is provided, and the chip is disposed on the wafer Corresponding regions of the respective wafers, in each region, the patch has a plurality of patch contact regions corresponding to the top electrode contact regions of the wafer, and the patch further has a plurality of connection regions with the plurality of patch contacts Patches are connected to the ribs, and the plurality of patches are connected to the ribs downwardly; the plurality of patch contact regions are connected to the top electrode contact regions of the wafer, and the plurality of patch ribs are disposed on the crystal a circular recessed area; providing a plastic body to encapsulate the top of the wafer, the plurality of wafers, and the patch. The method for packaging a wafer size patch according to claim 1, further comprising thinning the bottom of the wafer until the bottom surface of the wafer and the plurality of patches disposed in the groove region of the wafer The bottom of the rib is on the same plane. The method of packaging a wafer size patch according to claim 2, further comprising forming a bottom electrode contact region on the bottom surface of the wafer. The method of packaging a wafer size patch as described in claim 2 or 3, further comprising cutting the entire plasticized wafer to obtain a molded body of each wafer. The method of packaging having a wafer size patch as described in claim 1, wherein the at least one top electrode contact region is formed into a plurality of sections. The package method with a wafer size patch according to claim 1, wherein at least one of the patch contact regions is formed into a plurality of partitions. A packaging method with a wafer size patch, comprising the steps of: providing a wafer, fabricating a plurality of wafers on the wafer, the plurality of wafers having a plurality of top electrode contact regions and a plurality of a bottom electrode contact region; step 2: etching a plurality of groove regions on the wafer; Step 3: providing a patch, the patch comprising a plurality of patch contact regions and a plurality of patch ribs connected to the plurality of patch contact regions, the plurality of patch contact regions being bonded to the wafer electrode contact regions And simultaneously, the plurality of patch ribs are disposed in the plurality of groove regions of the wafer; step 4: the molding body molds the top of the package wafer, the plurality of wafers and the patch; step 5: aligning the crystal The bottom of the circle is thinned to form an electrode of the contact area at the bottom of the wafer; Step 6: The entire molded body of the plurality of wafers is cut to obtain a molded body of each wafer. The method for packaging a wafer size patch according to claim 7 of the patent application, the step 5 further comprising the steps of: step 5.1: performing metal deposition at the bottom of the wafer; and step 5.2: mask etching the bottom of the wafer Thereby protecting the exposed wafer electrodes at the bottom of the wafer. The method of packaging a wafer size patch according to claim 7, wherein in the step 3, the patch further comprises a patch frame, the patch frame distinguishing the patch from the wafer. Each area corresponding to each wafer. The method of packaging a wafer size patch according to claim 7, wherein in the step 1, the method further comprises electroplating forming a plurality of wafer top electrode contact regions on each of the wafers. The method of packaging a wafer size patch according to claim 7, wherein in step 3, the plurality of patch contact regions are disposed corresponding to the plurality of wafer electrode contact regions, and the plurality of patch contacts The regions are bonded to their corresponding plurality of wafer electrode contact regions via a conductive bonding material and extend through the plurality of patch ribs out of the electrodes at the top contact area of the wafer. The method for packaging a wafer size patch according to claim 7, wherein in step 6, the electrode of the bottom contact area of the wafer exposed at the bottom of the wafer is thinned and the bottom surface of the plurality of patch ribs is On the same plane. The package method with a wafer size patch according to claim 1 or 7, wherein the plurality of wafers are power semiconductor field effect transistors having a top contact region and a bottom contact region, the bottom of the plurality of wafers The electrode of the contact region is a drain, and the top contact region of the plurality of wafers The electrodes are respectively a source and a gate, and the source and the gate are extended through the plurality of patch ribs such that the source, the gate and the drain of the plurality of wafers are on the same plane. A package method having a wafer size patch as described in claim 1 or 7, wherein the plurality of groove regions divide the plurality of wafers into individual wafer units.