TWI464847B - Electronic device package and fabrication method thereof - Google Patents

Description

Electronic component package and method of manufacturing same

The present invention relates to an electronic component package, and more particularly to a stress relief structure of an electronic component package and a method of fabricating the same.

Generally, a solder ball is usually disposed on the back surface of the chip package to electrically connect with a bonding pad on a printed circuit board (PCB), and the solder ball is usually soldered on the back surface of the chip package. In the opening of the solder mask.

FIG. 1A is a partial plan view showing a conventional chip package in which a solder ball 12 is disposed. Since the solder balls 12 and the solder resist film 10 are different in material, the coefficient of thermal expansion (CTE) of the solder balls 12 is not matched, and in the temperature cycling test environment, the solder balls 12 and the solder resist film 10 are The joint 14 is prone to cracks, causing the conventional chip package to create a reliability problem. Please refer to FIG. 1B, which is a partial cross-sectional view showing the chip package along the section line B-B' in FIG. 1A. A solder resist film 10 is formed on the wafer 16, and the solder ball 12 is disposed on the solder mask. In the opening of the 10, the crack 14 generated at the junction of the solder ball 12 and the solder resist film 10 is located in the solder resist film 10.

Referring to FIG. 2, a partial cross-sectional view of a conventional chip package is shown in which a polymer ring 18 is formed at the junction of the solder ball 12 and the solder resist film 10, and the crack is prevented by the polymer ring 18. . However, the formation of the polymer ring 18 at the junction of the solder ball 12 and the solder resist film 10 requires additional materials and processes, and the material cost thereof is high, so that the manufacturing cost of the chip package is increased.

Therefore, there is a need in the industry for an electronic component package that avoids cracks at the junction of the solder ball and the solder mask, and achieves a more economical manufacturing cost.

The present invention provides an electronic component package comprising: a semiconductor substrate including a plurality of electronic component wafers, the protective layer being disposed on the semiconductor substrate, having a first opening, the conductive bumps being disposed in the first opening of the protective layer, and The stress relief structure is disposed within the protective layer and surrounds the conductive bumps.

In addition, the present invention also provides a method of fabricating an electronic component package, comprising: providing a semiconductor substrate including a plurality of electronic component wafers, forming a protective layer on the semiconductor substrate, patterning the protective layer, forming a first opening, and a plurality of The second opening surrounds the first opening and forms a conductive bump in the first opening, wherein the second openings form a stress relief structure surrounding the conductive bump.

In order to make the above objects, features, and advantages of the present invention more comprehensible, the following detailed description is made in conjunction with the accompanying drawings.

The invention will be described in detail below with reference to the accompanying drawings, in which the same or the same parts are used in the drawings. In the drawings, the shape or thickness of the embodiment may be expanded to simplify or facilitate the marking. In addition, the components of the drawings will be described in the description, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art. In addition, the specific embodiments are merely illustrative of specific ways of using the invention, and are not intended to limit the invention.

In the embodiment of the electronic component package of the present invention, it can be applied to various electronic components including integrated circuits such as active or passive elements, digital circuits or digital circuits. Electronic components), for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or physical quantity changes such as heat, light, and pressure. Physical Sensor (Physical Sensor). In particular, it is possible to use a wafer scale package (WSP) process for image sensor, light-emitting diodes (LEDs), solar cells, and radio frequency components ( RF circuits), accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads The semiconductor wafer is packaged.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to an electronic component package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

The invention provides an electronic component package and a manufacturing method thereof. A stress relief structure is arranged around the conductive bump around the conductive bump of the electronic component package, and the stress relief structure is formed in the protective layer, thereby reducing the conductive bump and the protective layer. The degree of thermal expansion coefficient mismatch, and the cracks generated in the protective layer can be prevented from continuing to spread.

Please refer to FIGS. 3A-3H, which are partial plan views showing an electronic component package according to various embodiments of the present invention, showing the arrangement relationship between the opening 110 filling the conductive bumps and the stress relief structure 112 in the protective layer 104. Wherein the stress relief structure 112 is disposed around the opening 110 filling the conductive bumps, and various types of stress relief structures 112 are shown in FIGS. 3A through 3H, respectively. Next, referring to Fig. 4, there is shown a partial cross-sectional view of an electronic component package along section lines 4-4' of Figs. 3A to 3E and 3H, in accordance with an embodiment of the present invention. As shown in FIG. 4, the front surface of the semiconductor substrate 100 has a plurality of electronic component wafers (not shown), an insulating layer 102 is formed on the back surface 100b of the semiconductor substrate 100, and a wiring layer 106 is formed on the insulating layer 102. The layer 106 is covered with a protective layer 104. The material of the protective layer 104 may be a photosensitive insulating material such as a solder mask having a coefficient of thermal expansion of usually about 30 ppm/° C.

A first opening 110 is formed in the protective layer 104 to expose the wire layer 106, and the first opening 110 is filled with a conductive bump 108. The material of the conductive bump 108 may be a conductive metal, such as tin-lead alloy, tin-silver-copper alloy. Or other alloy materials, the conductive bumps 108 typically have a coefficient of thermal expansion of about 24.5 ppm/°C. Since the thermal expansion coefficients of the conductive bumps 108 and the material of the protective layer 104 do not match, cracks are easily generated at the junction of the conductive bumps 108 and the protective layer 104, and the cracks may spread in the protective layer 104, so that the electronic component package is at a temperature. A problem of poor reliability occurs in a cyclical environment.

Therefore, according to an embodiment of the present invention, one or more second openings 112 are formed around the first opening 110, and the second opening 112 can serve as a stress relief structure, thereby reducing the conductive bumps 108 and the protective layer 104. The degree of thermal expansion does not match, and cracks generated in the protective layer 104 can be prevented from continuing to spread. In addition, in an embodiment of the present invention, the buffer material may be filled in the second opening 112 as a stress relief structure, and the buffer material may be a soft plastic material such as silicone.

In an embodiment of the present invention, the shape of the first opening 110 filling the conductive bump may be a circle or a polygon, and the polygon is, for example, a quadrangle (including a square, a rectangle or a diamond), a pentagon, a hexagon or another polygon. The circular first opening 110 is as shown in FIGS. 3A to 3C, 3G, and 3H, and the quadrilateral first opening 110 is as shown in FIGS. 3D to 3F.

In an embodiment of the present invention, when the conductive bumps 108 are filled in the circular first opening 110, the stress generated by the difference in thermal expansion coefficient between the conductive bumps 108 and the protective layer 104 is a circular opening. The center of the circle is uniformly diverged in all directions of the circumference, so that the second opening 112 surrounding the circular first opening 110 as a stress relief structure is preferably uniformly or symmetrically distributed around the first opening 110, such as 3A to 3C. Figure and Figure 3G. Further, the second opening 112 surrounding the circular first opening 110 as a stress relief structure may also be an arcuate opening or an annular opening having an opening, as shown in FIG. 3H.

In one embodiment, when the conductive bumps 108 are filled in the first opening 110 of the quadrilateral, the stress generated by the difference in thermal expansion coefficient between the conductive bumps 108 and the protective layer 104 is from the center of the quadrilateral opening toward the quadrilateral quad. The corners diverge, so that the second opening 112 surrounding the first opening 110 of the quadrilateral as the stress relief structure is preferably disposed adjacent the four corners of the first opening 110, as shown in Figures 3D and 3F. Further, in another embodiment, the second opening 112 surrounding the first opening 110 of the quadrilateral may also be uniformly or symmetrically distributed around the first opening 110 as shown in FIG. 3E.

The shape of the second opening 112 may be circular, square, rectangular, curved or an annular or other shape with an opening. In an embodiment, the second opening 112 may be disposed at a distance from the first opening 110, such as Figures 3A to 3E and 3H are shown. In another embodiment, the second opening 112 may also be interconnected with the first opening 110, as shown in FIGS. 3F and 3G.

Next, please refer to FIGS. 5A to 5E, which are cross-sectional views showing a manufacturing method of a stress relief structure for forming an electronic component package according to an embodiment of the present invention. As shown in FIG. 5A, a semiconductor substrate 100, such as a semiconductor wafer, is first provided, and a plurality of electronic component wafers (not shown) are included on the front side 100a of the semiconductor substrate 100.

Next, referring to FIG. 5B, an insulating layer 102 is formed on the back surface 100b of the semiconductor substrate 100. In an embodiment, the insulating layer 102 may be an epoxy, a solder mask, or the like. An insulating material such as a cerium oxide layer of an inorganic material, a tantalum nitride layer, a cerium oxynitride layer, a metal oxide or a combination thereof, or a polyimine resin (PI) or a benzocyclobutene of an organic high-molecular material. (butylcyclobutene; BCB), parylene, polynaphthalenes, fluorocarbons, accrylates, etc., and the insulating layer 102 may be coated by means of, for example, spin coating. Spin coating, spray coating or curtain coating, or other suitable deposition methods, such as liquid phase deposition, physical vapor deposition (PVD) , chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposi) (PECVD), rapid thermal chemical vapor deposition (RTCVD) or atmospheric pressure chemical vapor deposition (APCVD) to form a semiconductor substrate 100 and subsequently formed wiring layers 106.

Next, a wire layer 106 is formed on the insulating layer 102, and the wire layer 106 can be compliantly deposited, for example, by copper, aluminum, or silver (PV) by, for example, physical vapor deposition (PVD) or sputtering. A conductive layer of Ag), nickel (Ni) or an alloy thereof is formed on the insulating layer 102, and the conductive layer is patterned by a photolithography process to form the wiring layer 106. The wire layer 106 is electrically connected to the electronic component wafer on the front side 100a of the semiconductor substrate 100. Then, a passivation layer 104 is formed on the back surface 100b of the semiconductor substrate 100 to cover the wire layer 106 and the insulating layer 102. The protective layer 104 is a photosensitive insulating material such as a solder mask.

Referring to FIG. 5C, a reticle 120 is disposed over the protective layer 104. The reticle 120 has patterns 122 and 124. The reticle pattern 122 corresponds to the first opening 110 filling the conductive bump, and the reticle pattern 124 is Corresponding to the second opening 112 forming the stress relief structure. The protective layer 104 is patterned by using the mask 120 to expose and develop the protective layer 104. As shown in FIG. 5D, the first opening 110 is formed in the protective layer 104 to expose the wiring layer 106, and one or more layers are formed. The second opening 112 surrounds the first opening 110 , wherein the openings 110 and 112 both penetrate the protective layer 104 .

Then, referring to FIG. 5E, a solder is filled in the first opening 110 by electroplating or screen printing, and a re-flow process is performed to A conductive bump 108 is formed, for example, as a solder ball or a solder paste. Thereafter, the wafer-level package is divided along the scribe line between the respective electronic wafers to separate the electronic component wafers, thereby completing the electronic component package of the present invention. Although not described in the above embodiments, it is understood by those skilled in the art that the electronic component package of the present invention and the method of manufacturing the same may include other components and other processes, such as packaging. A layer, a spacer, a conductive pad, etc., and other components are processed to form the electronic component package of the present invention.

In one embodiment of the invention, the stress relief structure may be one or more second openings 112 surrounding the first opening 110 filling the conductive bumps 108, as shown in FIG. 5E. In addition, in another embodiment of the present invention, as shown in FIG. 6, the buffer material 114 may be filled in the second opening 112 as a stress relief structure, and the buffer material 114 may be a soft plastic material such as silicone.

According to the embodiment of the present invention, the stress relief structure may be formed in the protective layer of the electronic component package to surround the conductive bump, and the stress relief structure may reduce the degree of mismatch of the thermal expansion coefficient of the junction between the conductive bump and the protective layer, and Cracks generated in the protective layer can be prevented from continuing to spread. The stress relief structure may be formed in the protective layer together with the opening filling the conductive bumps, no additional process is required, and other materials may not be filled in the stress relief structure, and therefore, the electronic component package of the present invention is economical to manufacture.

Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

10. . . Solder mask

12. . . Solder ball

14. . . crack

16. . . Wafer

18. . . Polymer ring

100. . . Semiconductor substrate

100a. . . Front side of the semiconductor substrate

100b. . . Back side of semiconductor substrate

102. . . Insulation

104. . . The protective layer

106. . . Wire layer

108. . . Conductive bump

110. . . First opening

112. . . Second opening

114. . . Cushioning material

120. . . Mask

122, 124. . . Mask pattern

Figure 1A shows a partial plan view of a conventional chip package.

Fig. 1B is a partial cross-sectional view showing the chip package taken along the section line B-B' in Fig. 1A.

Figure 2 is a partial cross-sectional view showing another conventional chip package.

3A-3H are partial plan views showing an electronic component package in accordance with various embodiments of the present invention.

Figure 4 is a partial cross-sectional view showing the electronic component package along section lines 4-4' of Figures 3A through 3E and 3H, in accordance with an embodiment of the present invention.

5A to 5E are cross-sectional views showing a method of manufacturing a stress relief structure for forming an electronic component package in accordance with an embodiment of the present invention.

Figure 6 is a partial cross-sectional view showing an electronic component package in accordance with another embodiment of the present invention.

100. . . Semiconductor substrate

100b. . . Back side of semiconductor substrate

102. . . Insulation

104. . . The protective layer

106. . . Wire layer

108. . . Conductive bump

110. . . First opening

112. . . Second opening

Claims (21)

An electronic component package comprising: a semiconductor substrate comprising a plurality of electronic component wafers; a protective layer disposed on the semiconductor substrate and having a first opening; and a conductive bump disposed on the protective layer And a stress relief structure disposed in the protective layer and surrounding the conductive bump, wherein the stress relief structure comprises a plurality of second openings formed in the protective layer and separated from each other, and the plurality of openings Two openings surround one of the conductive bumps. The electronic component package of claim 1, wherein the second openings extend through the protective layer, and each of the openings of the second openings has a shape including a circle, a square, a rectangle or an arc. The electronic component package of claim 1, further comprising a buffer material filled in the second openings. The electronic component package of claim 3, wherein the buffer material comprises a soft plastic material. The electronic component package of claim 1, wherein the shape of the first opening comprises a circle or a polygon. The electronic component package of claim 1, wherein the stress relief structure is symmetrically distributed around the conductive bump. The electronic component package of claim 1, wherein the stress relief structure is disposed in a manner separated from the first opening The spacing is interconnected with the first opening. The electronic component package of claim 1, wherein the shape of the first opening is a polygon, and the stress relief structure is disposed corresponding to a plurality of corners of the polygon. The electronic component package of claim 8, wherein the stress relief structure is disposed in such a manner as to be interconnected with the corners of the polygon or at a distance from the corners of the polygon. A method of fabricating an electronic component package, comprising: providing a semiconductor substrate comprising a plurality of electronic component wafers; forming a protective layer over the semiconductor substrate; patterning the protective layer to form a first opening and a plurality of separate openings The second opening surrounds the first opening; and a conductive bump is formed in the first opening, wherein the second openings form a stress relief structure surrounding the conductive bump. The method of manufacturing an electronic component package according to claim 10, wherein the shape of the first opening comprises a circle or a polygon. The method of manufacturing an electronic component package according to claim 10, wherein the second openings are symmetrically distributed around the first opening. The method of manufacturing the electronic component package of claim 10, wherein the second openings are disposed to be interconnected with the first opening or spaced apart from the first opening. The method of manufacturing an electronic component package according to claim 10, wherein the step of patterning the protective layer comprises an exposure and development process. The method for manufacturing an electronic component package according to claim 10, further comprising filling a buffer material in the second openings. The method of manufacturing an electronic component package according to claim 15, wherein the buffer material comprises a soft plastic material. The method of manufacturing an electronic component package according to claim 10, wherein the shape of the first opening is a polygon, and the second openings are disposed corresponding to a plurality of corners of the polygon. The method of manufacturing an electronic component package according to claim 17, wherein the second openings are disposed in such a manner as to be interconnected with the corners of the polygon or at a distance from the corners of the polygon. The method of manufacturing the electronic component package of claim 10, wherein the first opening and the second openings extend through the protective layer, and each of the openings of the second openings comprises a circular shape. Square, rectangular or curved. An electronic component package comprising: a semiconductor substrate comprising a plurality of electronic component wafers; a protective layer disposed on the semiconductor substrate and having a first opening; and a conductive bump disposed on the protective layer And a stress relief structure disposed in the protective layer and surrounding the conductive bump, wherein the stress relief structure comprises an annular opening having a notch, and the annular opening having a notch and the conductive bump The spaces are separated by the protective layer. The electronic component package of claim 20, further comprising a buffer material filled in the annular opening having a gap, wherein the buffer material comprises a soft plastic material.