TWI462106B - Method and apparatus for reducing erase disturb of memory circuit by using recovery bias - Google Patents

Description

Method and apparatus for reducing erasure interference in memory by using a return bias

This invention relates to non-volatile memory, and more particularly to methods and apparatus for reducing erase interference in non-volatile memory.

The erasure algorithm of the non-volatile memory cell pre-programs the erased memory cell to a stylized state, then erases it, and then follows a soft stylization of over-erasing the memory cell. This pre-stylization and soft stylization is an extra step in addition to the erase operation and corrects the critical voltage distribution of the selected memory cell portion of the memory array. However, this erase algorithm does not correct the erase interference that is not selected to erase the memory cells. Erasing interference refers to the effect of being erased to some extent although it is not selected to erase the memory cells.

The techniques described herein provide an integrated circuit having a non-volatile memory array and control circuitry. The non-volatile memory array is segmented into a plurality of memory groups. The control circuit is responsive to an erase command to erase one or more memory groups of the first group and does not erase one or more memory groups of the second group, and applies a return adjustment bias to adjust a threshold voltage of a memory cell in at least one memory group of the one or more memory groups of the second group; the return adjustment bias voltage may be applied to one or more memory groups of the second group The threshold voltage change response caused by erasing one or more memory groups of the first group in at least one memory group. This erase adjustment bias is applied prior to the return adjustment bias.

By applying a reset adjustment bias to at least one of the one or more memory groups of the second group, the erase interference (at least a portion) can be corrected upon application of the reset adjustment bias. Wiping out the interference will be due to a same well area by (i) the first The one or more memory groups of the group and (ii) the at least one memory group of the one or more memory groups of the second group are shared, and occur when the erase adjustment bias is applied.

In the embodiment described herein, the integrated circuit also has logic to maintain a reply setting for indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state. For example, the reply setting may indicate that the address range of the memory cells of a well area is shared in the memory group. The number of memory cells is increased several times when the return adjustment bias is applied (e.g., to the non-volatile memory array or to a particular memory group).

In the embodiment described herein, a wipe verification bias is applied prior to applying the return adjustment bias. In response to the erase verify that the bias voltage has indicated that at least one of the one or more memory banks of the second group is experiencing erase interference, the control circuit applies the reset adjustment bias. The techniques disclosed herein also include a method. The method includes at least the steps of: erasing one or more memory groups of one of the first group of non-volatile memory arrays in response to an erase command and not erasing one of the second groups of the non-volatile memory array Or a plurality of memory groups, and applying a reply adjustment bias to adjust a threshold voltage of the memory cells in at least one of the one or more memory groups of the second group.

Many different embodiments are described herein.

Figure 1 is a flow chart showing an example of a replied erase algorithm with no reply erased memory cells in the memory group. In step 10, the integrated circuit with the memory array receives an erase command. This erase command specifies that one or more memory groups are to be erased. A memory group can be a group of memory cells, such as segments, blocks, or paragraphs, to be erased together. This memory cell group can also be the entire memory array. This erase algorithm performs more on one or more memory groups selected to be erased Steps, and then perform multiple steps on one or more memory groups that are not selected for erasure. First, multiple steps are performed on one or more memory groups that are selected to be erased.

In step 12, the memory group to be erased is selected to perform pre-stylization on all memory cells or a subset of the erased state. Such pre-stylization brings the memory cells in this memory group to a shared stylized state and prevents the memory cells in the erased state from being erased again. In step 14, the stylized state of all the memory cells in the memory group to be erased from the memory cells in the memory group is erased to the shared memory of the memory cells in the memory group. In addition to the status. At step 16, an erase verify is performed to check if the previous erase operation is sufficient to erase all of the memory cells in the memory group selected to be erased. At step 18, if the verification is not passed, the erase algorithm returns to step 14. At step 18, if the verification is done by erasing, the erase algorithm proceeds downward. In step 20, the memory cells that are over-erased in the memory group to be erased are selected for soft programming.

These previous steps are performed on one or more memory groups selected to be erased. The next step is to perform one or more memory groups that are not to be erased. In the erase operation of step 14, in addition to erasing one or more memory groups to be erased, as described in FIG. 2, one or more selections are not erased. The phenomenon of erasing interference occurs in the memory group. Erasing the interference is to select an unexpected erase that also occurs in the memory group that is not to be erased. At step 22, a reply stylization is performed to repair the erased interference memory cells in the memory group selected for not being erased. At step 24, the erase command is ended.

Figure 1 shows a stylized state represented by a high threshold voltage distribution, but other embodiments include multiple stylized states, such as having two bits and three stylized quasi-locations at each memory location. A meta-memory, and a multi-level memory cell with three bits or seven stylized quasi-locations at each memory location.

Figure 2 shows a doped well region shared by multiple memory groups including both selected erased memory groups and selected memory groups that are not to be erased. Unfortunately, regardless of whether only one group is selected for erasure, multiple memory groups sharing the well region 26 are exposed to the same high erase potential during erasing. This well 26, which is a p-type well (which may be an n-type well in other embodiments), is isolated from other such wells. Thus, the isolation in the well interval solves the problem of erasing interference between memory groups in different well areas, but does not solve the problem of erasing interference between memory groups sharing the same well area. This isolation structure and the smaller number of erase memory groups in each well region inevitably increase the size of this array.

One exemplary mechanism for erasing interference is Fowler-Nordheim (FN) electron or hole tunneling between a well region of a non-volatile memory cell and a charge storage element (eg, a floating gate and a dielectric charge trapping element). Such erase interference can occur even under different bias conditions of the word line or gate between the selected erased memory group and the selected memory group that is not to be erased.

Figure 3 is a graph 32 of the drain current I _D and the gate voltage V _G , showing the erased state in the low threshold voltage erase state, the high threshold voltage stylized state, and the high threshold voltage stylized state. Memory cell. Figure 4 is a diagram 34 of the drain current and gate voltage, shown in the low threshold voltage erase state, in the high threshold voltage stylized state, and back to the high threshold voltage as the recovery is programmed to correct the erase interference. Stylized state of memory cells.

In Figures 3 and 4, the high threshold voltage memory cell is in a stylized state and maintains a logic "0" data, while the low threshold voltage memory cell is in the erase state and maintains a logic "1" data. When erasing a memory group to be erased, other memory cells will be erased, so that even a memory group that is not to be erased will still be erased to some extent. In Fig. 3, a logical "0" data belonging to a memory cell in which the memory group is not erased has a stylized high threshold voltage state. As discussed in Figure 2, the erase interference occurs because both the selected erased memory group and the selected memory group that is not erased share the same well region.

Therefore, in Fig. 3, a threshold voltage shift caused by the erase interference caused by the logic "0" data of the memory cell in the memory group having the programmed high threshold voltage state is selected. . This erase interference memory cell exhibits a negative threshold voltage shift due to the net positive charge offset of the charge stored in the charge storage element that interferes with the memory cell. For example, the electrons can be erased from the charge storage element that interferes with the memory cell to the shared well region (or the hole moves from the shared well region to the charge storage element that erases the interfering memory cell). In this example, the shared well region has a relatively high positive voltage that can attract electrons from which the charge storage elements that erase the interfering memory cells move into the shared well region.

In Fig. 4, a threshold voltage shift caused by the self-response stylization of the erase interference memory cell in Fig. 3 is shown. This replies to the stylized memory cell exhibits a positive threshold voltage shift due to the net negative charge offset of the charge stored in the charge storage element of the stylized memory cell. For example, the electrons can move from the shared well region to the charge storage element of the regenerated stylized memory cell (or the hole from which the charge storage element of the stylized memory cell is moved to the shared well region). In this example, the shared well region has a relatively high negative voltage that can repel electrons from the charge storage element of the reprogrammed memory cell into the shared well region.

Figures 5 and 6 are further details showing an alternative embodiment of the reply stylization step 22 in the erase algorithm, e.g., in FIG. Figure 5 is a portion of an example flow diagram of a reply stylization that determines the response to a stylized slope based on static settings. The sixth picture is part of an example flow chart with a reply stylization that determines the response to the stylized slope based on the dynamic settings.

In Fig. 5, step 36 performs erasing. The dotted line indicates that the memory group to be erased is selected for other steps, such as pre-stylization, erase verification, and soft stylization discussed in FIG.

The subsequent steps are performed on a memory group that is not to be erased. At step 38, a reply verification is performed. If the reply is verified, no reply stylization is required and the reply stylization operation (and the erase algorithm) is ended in step 40. It is very small to verify that the erase interference in the stylized memory cell is small, so that the threshold voltage shift caused by the erase interference is not severe and needs to be reprogrammed. If the verification is not verified, continue to reply to the stylization. At step 42, the static settings of this reply stylized operation are read. This static setting indicates the number of memory cells that need to be reprogrammed, such as the memory cell address range of the memory group sharing the well zone. This static setting can be determined based on the semiconductor process of the non-volatile memory array or its application. This static setting can be stored in a memory such as a non-volatile memory or a fuse. In step 44, the reply stylization operation is performed on the erase interference memory cell according to the static setting.

In Fig. 6, step 46 performs erasing. The dotted line indicates that the memory group to be erased is selected for other steps, such as pre-stylization, erase verification, and soft stylization discussed in FIG. At step 48, the dynamic setting of the resume stylized operation is updated to, for example, a non-volatile memory, a counter in the controller, or a memory of the scratchpad. This dynamic setting reflects the number of erase operations that have been performed (eg, in a memory array). The memory array will degrade due to a certain number of stylized-erase cycles. As the number of erase operations performed increases, this dynamic setting also increases the number of memory cells that are executed by the stylized operation in a memory group that is not to be erased, or a larger address range. And increase.

The subsequent steps are performed on a memory group that is not to be erased. At step 50, reply verification is performed in the form of a memory cell followed by a memory cell. If the verification is verified by reply, no reply stylization is required, and the reply stylization operation (and the erase algorithm) is ended in step 52. It is very small to verify that the erase interference in the stylized memory cell is small, so that the threshold voltage shift caused by the erase interference is not severe and needs to be reprogrammed. If it is not verified by the reply, it will continue to reply to the stylization operation by means of a memory cell followed by a memory cell. At step 54, the dynamic settings of this reply stylized operation are read. This dynamic setting reflects the number of memory cells that need to be reprogrammed, such as the memory cell address range of the memory group sharing the well zone. This dynamic setting can be determined based on the semiconductor process of the non-volatile memory array or its application. This dynamic setting can be stored in a memory such as a non-volatile memory or a fuse. In step 56, the reply stylization operation is performed on the erase interference memory cell according to the dynamic setting.

In Figure 7, step 58 performs the erase. The dotted line indicates that the memory group to be erased is selected for other steps, such as pre-stylization, erase verification, and soft stylization discussed in FIG. Or the steps taken on the memory group that is not to be erased.

The following is an example of this dynamic setting update. In some embodiments, this dynamic setting reflects the starting position or starting memory address of the reply stylized operation.

Step 60 determines if the eraser is the first eraser after booting. In various embodiments, the eraser program is executed first by the entire array or by a particular memory group that is designated to be erased by the erase command. If the erasing procedure is the first erasing procedure after the booting, in step 62, the dynamic setting is selected from the memory group sharing the well area, for example, a starting memory address is selected, for example, as shown in FIG. . If the erase process is the second or subsequent erase process after booting, then in step 64, the next start memory address is selected from a series of memory groups sharing the well zone, for example, the second Shown in the figure.

Figure 8 shows a simplified block diagram of a memory integrated circuit having a memory array and the improvements described herein in accordance with an embodiment of the present invention. The integrated circuit 150 includes a memory array 100. A word line (column) decoder and block selection decoder 101 is coupled and electrically coupled to a plurality of word lines 102 arranged along the column direction of the memory array 100. A bit line (row) decoder and driver 103 are coupled and electrically communicated with a plurality of bit lines 104 arranged along the row direction of the memory array 100 to read data and write from the memory cells of the memory array 100. data. The address is supplied from the bus bar 105 to the word line decoder 101 and the bit line decoder 103. The sense amplifier and data input structure in block 106 is coupled to bit line decoder 103 via bus bar 107. The data is supplied to the data input line 111 from the input/output port on the integrated circuit 150 to the data input structure in block 106. The data is provided by the sense amplifier in block 106, via the data output line 115, to the input/output ports on the integrated circuit, or to other internal/external data sources of the integrated circuit 150. The stylizing, erasing, and reading adjustment bias state mechanism 109 controls the application of the bias adjustment supply voltage 108 and applies a return adjustment bias during erasing. State mechanism circuit 109 also includes logic 140 that stores the reply settings and determines the range of return biases (e.g., the range of memory cells) at the time of erasing.

The techniques disclosed in the preferred embodiments of the present invention can be applied to non-volatile memory arrays such as reverse OR (NOR) gate arrays. An example of a non-volatile memory element can be a floating gate element or a dielectric charge trapping memory element.

The technique disclosed in the preferred embodiment of the present invention applies a return adjustment bias which adjusts the threshold voltage to become larger or smaller depending on the embodiment.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

150. . . Integrated circuit

100. . . Non-volatile memory cell array

101. . . Column decoder

102. . . Word line

103. . . Row decoder

104. . . Bit line

105. . . Busbar

107. . . Data bus

106. . . Sense amplifier / data input structure

109. . . Stylize, erase (with reply) and read the logic of the adjustment bias state mechanism to store the reply settings

108. . . Bias adjustment supply voltage

111. . . Data input line

115. . . Data output line

Figure 1 is a flow chart showing an example of a replied erase algorithm with no reply erased memory cells in the memory group.

Figure 2 shows a doped well region shared by multiple memory groups including both selected erased memory groups and selected memory groups that are not to be erased.

Figure 3 is a graphical representation of the drain current and gate voltage, showing the memory cells that are experiencing erase interference in the low threshold voltage erase state, in the high threshold voltage stylized state, and because of the high threshold voltage stylized state.

Figure 4 is a diagram of the drain current and gate voltage, showing the low threshold voltage erase state, the high threshold voltage stylized state, and the return to the high threshold voltage program because it is undergoing a reprogramming to correct the erase interference. The memory cell of the state.

Figure 5 is a portion of an example flow diagram of a reply stylization that determines the response to a stylized slope based on static settings.

Figure 6 is a portion of an example flow diagram that is responsive to the dynamic setting to determine the response to the stylized slope.

Figure 7 is a portion of an example flow diagram that is responsive to dynamic settings to determine the response to a stylized slope.

Figure 8 shows a simplified block diagram of a memory integrated circuit having a memory array and the improvements described herein in accordance with an embodiment of the present invention.

Claims (20)

An integrated circuit comprising: a non-volatile memory array having a plurality of memory groups; a control circuit for erasing one or more memory groups of a first group without erasing one or more of the second group a memory group, and applying a reply adjustment bias to adjust a threshold voltage of the memory cells in at least one of the one or more memory groups of the second group. For example, the integrated circuit of claim 1 further includes: maintaining a logic for indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state. The number of memory cells receives the reply adjustment bias to freely erase the threshold voltage change caused by the one or more memory groups of the first group. For example, the integrated circuit of claim 1 further includes: maintaining a logic for indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state. The number of memory cells receives the reply adjustment bias to freely erase the threshold voltage change caused by the one or more memory groups of the first group, and the number of memory cells when the return adjustment bias is applied Increased several times. For example, the integrated circuit of claim 1 further includes: maintaining a logic for indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state. The number of memory cells receiving the reply adjustment bias to freely erase a threshold voltage change caused by the one or more memory groups of the first group, and when applying the return adjustment bias to the non-volatile memory array The number of memory cells will increase several times. The integrated circuit of claim 1, wherein the control circuit responds to an erase command by applying an erase adjustment bias before the reset bias is applied. An integrated circuit of claim 1, wherein the same well region is comprised of (i) one or more memory groups of the first group and (ii) one or more memory groups of the second group The at least one memory group is shared. The integrated circuit of claim 1, wherein the control circuit applies an erase adjustment bias to the one or more memory groups of the first group by adjusting the bias voltage, and the second group One or more memory groups may cause erase interference during the erase adjustment bias period, and the erase interference is at least partially corrected during the reset adjustment bias period in response to an erase command. An integrated circuit of claim 1, wherein the same well region is comprised of (i) one or more memory groups of the first group and (ii) one or more memory groups of the second group Sharing by the at least one memory group, wherein the control circuit applies an erase adjustment bias before adjusting the bias due to the reply, and because it is shared with one or more memory groups of the first group being erased One or more memory groups of the second group of the same well region are not being erased, and erasing interference occurs during the erase adjustment bias period, and the erase is performed during the recovery adjustment bias period. The interference is at least partially corrected and responds to a erase command. The integrated circuit of claim 1, wherein the control circuit adjusts the bias voltage by applying a verification, and the control circuit adjusts the bias voltage by applying the return to respond to the one or more memories indicating the second group At least one of the memory cells in the group has been subjected to the verification adjustment bias affected by the erase interference, and in response to an erase command. The integrated circuit of claim 1, wherein the application of the return adjustment bias is a change from a threshold voltage change of a memory cell in at least one of the one or more memory groups of the second group The change in threshold voltage is caused by erasing one or more memory groups of the first group. A method of operating a memory, comprising: responding to an erase command to erase one or more memory groups of a first group of a non-volatile memory array and not erasing one of the second group of the non-volatile memory array One or more memory groups, and applying a reply adjustment bias to adjust a threshold voltage of the memory cells in at least one of the one or more memory groups of the second group. The method of claim 11, wherein the applying the reset bias is based on a reply setting indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state, The number of memory cells receives the reply adjustment bias to freely erase the threshold voltage change caused by the one or more memory groups of the first group. The method of claim 11, wherein the applying the reset bias is based on a reply setting indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state, The number of memory cells receives the reply adjustment bias to freely erase the threshold voltage change caused by the one or more memory groups of the first group, and the number of memory cells when the return adjustment bias is applied Increased several times. The method of claim 11, wherein the applying the reset bias is based on logic indicating that a certain number of memory cells in the one or more memory groups of the second group are in a stylized state Retrieving the reply adjustment bias to freely erase the threshold voltage change caused by the one or more memory groups of the first group, and applying the reset adjustment bias to the non-volatile memory array The number of memory cells will increase several times. The method of claim 11, further comprising: responding to the erase command by applying a wipe adjustment bias to the one or more memory groups of the first group prior to adjusting the bias. The method of claim 11, wherein the same well region is comprised of (i) one or more memory groups of the first group and (ii) one or more memory groups of the second group At least one memory group is shared. The method of claim 11, wherein the interference is at least partially corrected during the reset bias period, wherein an erase bias is applied to the one or more memories of the first group prior to the reset adjustment bias The group causes one or more memory groups of the second group to have erase interference during the erase adjustment bias period. The method of claim 11, wherein the erasing bias is at least partially corrected during the resetting bias period, wherein an erase bias applied before the return adjustment bias causes one or more of the second group The memory group may cause erase interference during the erase adjustment bias period, the erase interference being due to sharing the same well region with one or more memory groups of the first group being erased One or more memory groups of the second group do not occur while being erased. The method of claim 11, wherein at least one of the one or more memory groups of the second group has been erased by responding to a verification adjustment bias by applying the erase adjustment bias Impact. In the method of claim 11, the application of the reply adjustment bias is a change from a threshold voltage change of a memory cell in at least one of the one or more memory groups of the second group, the threshold The change in voltage is caused by erasing one or more memory groups of the first group.