TWI459389B - Semiconductor memory devices, reading program and method for memory devices - Google Patents

Description

Semiconductor memory device, memory device reading program and method

The present invention relates generally to a semiconductor memory device, and more particularly to a data reading method for a NAND type flash memory.

In recent years, flash memory with SPI or Serial Peripheral Interface applications requires high-density integration of 512MB, 1GB or more. At the same time, it is also necessary to reduce the unit price of the memory. The NAND type flash memory has the same similar problem.

Even for the NAND-type flash memory of the smallest sized array, the address change is still slower than that of the NOR type memory. Therefore, problems occur in continuous wraparound read operations. Figures 9a-9d are one embodiment of a wraparound read operation. The wraparound read operation, for example, as shown in Fig. 9a, the nth page (word line) of the memory array MA is selected, and the data read from the nth page is transferred to the page register PB. (page buffer), and then as shown in FIG. 9b, the data temporarily stored in the page register PB is continuously transmitted to the outside. Then, as shown in FIG. 9c, the n+1th page is selected, and the data read from the n+1th page is transferred to the page register PB. As shown in FIG. 9d, the page register is temporarily stored. The data is continuously transmitted to the outside. As a result, the data on page n+1 must wait for the end of the data reading on page n. That is to say, when the data read on the nth page is continuously outputted to approximately end, the n+1th page is selected. Regarding the management data D1 of the data included on the n+1th page, if the nth page is present, the waiting time required to acquire the management data D1 becomes longer.

SUMMARY OF THE INVENTION The object of the present invention is to solve the above mentioned problems and to provide a semiconductor memory that is more flexible and quickly reads data.

A semiconductor memory device according to the present invention includes: a memory cell array having at least two memory groups simultaneously accessible, the memory groups including a plurality of memory cells arranged in a matrix, the memory The gates of the columns of the unit are commonly coupled to the corresponding word line, and the rows of the memory unit are coupled to the corresponding bit line; a first receiving device is configured to receive the address information; and a second receiving device is used. Receiving one of the related access actions; a word line selecting means for decoding a column address message received by the first receiving device, and selecting a word line according to the decoding result; and a control device according to The command received by the second receiving device controls the word line selecting device; wherein the control device causes the word line selecting device to perform a first reading operation according to a first read command, according to a second The read command causes the word line selection device to perform a second read operation; the first read operation selects an nth word line from a group of the memory groups, and is in the memory group Another group selects an n+1th or n-1th word line; the second read operation selects an nth word line in a group of the memory groups, and is in the memory group The other group selects the nth character line.

A memory device reading program according to the present invention is applicable to a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array having at least two memory groups simultaneously accessible, the memory groups The method includes a plurality of memory cells arranged in a matrix, the gates of the columns of the memory cells are commonly coupled to corresponding word lines, and each row Coupling to the corresponding bit line, and having a word line selecting means selecting the word line according to the decoding result of the column address information, the step comprising: determining that the received read command is a first read command or a second read command; if it is determined to be the first read command, the word line selection device performs a first read operation; and if it is determined to be the second read command, the word line Selecting means for performing a second read operation; wherein the first read operation selects an nth word line in one of the groups of memory groups, and selects nth in another set of the memory groups +1 or n-1th character line; and the second read operation selects an nth character line in one of the groups of memory groups, and selects another set of the other memory groups n word lines.

A semiconductor memory reading method is provided for a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array having at least two memory groups simultaneously accessible, the memories The group includes a plurality of memory cells arranged in a matrix, the gates of the columns of the memory cells are commonly coupled to corresponding word lines, and each row is coupled to a corresponding bit line, and has a word line selection device Selecting a word line according to the decoding result of the column address information, the step of: determining that the received read command is a first read command or a second read command; if the first read command is determined And the word line selection device performs a first read operation; and if the second read command is determined, the word line selection device performs a second read operation; wherein the first read The operation selects an nth word line in one of the groups of memory groups, and selects an n+1th or n-1th word line in another group of the groups of memory; and the second The read operation is tied to the memory One of the groups of groups selects the nth character line, and the other of the groups of memory selects the nth word line.

According to the present invention, by selectively using the first and second reading operations, a more flexible reading operation can be performed, and data can be read more quickly.

The following detailed description is in accordance with the embodiments of the invention

Fig. 1 is a schematic block diagram showing a NAND type semiconductor memory according to an embodiment of the present invention. The semiconductor memory 10 in this embodiment includes a memory array 100, a plurality of memory cells arranged in a matrix, an input/output buffer 110, and temporary storage of input and output data connected to an external input/output terminal I/O. The register 120 receives the address data of the input/output buffer 110, the data register 130, temporarily stores the input and output data, the controller 140 receives the command data from the input/output data buffer 110, and controls each according to the command. The unit, word line selection circuit 150 performs block selection and word line selection according to the decoding result of decoding the column address information Ax from the address register 120, the page register/detection circuit 160, the temporary word The data selected by the page selected by the line selection circuit 150 temporarily stores the data written by the selected page, and the row selection circuit 170 performs the bit decoding according to the decoding result of the row address information Ay from the address register 120. For line selection, the internal voltage generating circuit 180 generates voltages necessary for reading, stylizing, and deleting data.

The memory array 100 of one embodiment of the present invention includes two memory banks 100L, 100R that are simultaneously accessible. in order to For convenience, the memory group on the left side of the figure is identified by "L" or "left side", and the memory group on the right side is identified by "R" or "right side". The memory groups 100L and 100R are composed of substantially the same cell layout, that is, the memory group 100L has m+1 blocks BLK(L)1, BLK(L)2, ..., BLK in the row direction. (L) m+1, and the memory 100R has m+1 blocks BLK(R)1, BLK(R)2, ..., BLK(R)m+1 in the row direction.

Fig. 2 is a view showing a general circuit configuration of the memory group 100L in the memory array 100 shown in Fig. 1. The memory group 100L has a plurality of blocks BLK(L)1, BLK(L)2, ..., BLK(L)m+1 in the direction of the bit line BL, each of which is electrically connected Bit line BL of n bits. A memory block BLK(L)1 has a plurality of NAND cell groups (hereinafter referred to as cell groups NU), wherein the cell group NU is a plurality of memory cells connected in series, and these cell groups NU are arranged in a row direction. As shown in the figure, each cell group NU includes a plurality of memory cells MCi (in this embodiment, i=0, 1, . . . , 31) connected in series, and is electrically connected to the tandem complex memory. The selection transistor TR1 and the selection transistor TR2 are formed at both ends of the cell, and each cell group NU is electrically connected to the corresponding bit line BL, respectively. The drain of the transistor TR1 is selected to be coupled to the bit line BL, and the source of the selection transistor TR2 is coupled to the common source line SL.

The control gates of the memory cells MCi in the cell group NU are electrically connected to the corresponding word lines WLi, respectively. The gates of the selection transistors TR1, TR2 are electrically connected to the selection gate lines SGD, SGS parallel to the word line WL, respectively. As shown in the figure, one block is composed of n+1 unit groups NU, and the complex memory unit is shared by each word line in the block. Collections that make up a page. That is, one page on one side has n+1 bits. Further, the set of n+1 cell groups NU shared by the word line WL and the selection gate lines SGD and SGS constitutes a block as a deletion data unit. In addition, the word line selection circuit 150 turns on the selection transistors TR1 and TR2 by the selection gate signals SGS, SGD of the block when the block is selected. Further, the memory group 100R not shown in the figure has the same memory array composition as the memory group 100L.

The bit lines BL1, BL2, . . . , BLn, BLn+1 electrically connected to the cell groups NU of the memory bank 100L are electrically connected to the page register/detection circuit 160 through the bit line selection. Amplifier circuits SA1, SA2, ..., SAn, SAn+1. The row selection circuit includes an odd bit line selection transistor TRo for selecting an odd bit line and an even bit line selection transistor TRe for selecting an even bit line. An odd bit line selection transistor TRo is coupled between the detection amplifier circuits (SA1, SA3, . . . , and SAn) corresponding to the odd bit lines (BL1, BL3, ..., BLn), and the odd bit line selection transistor is coupled to the transistor. TRo controls its conduction/non-conduction by the odd bit line selection signal BLSo coupled to its gate. The even-numbered bit lines (BL0, BL4, ..., BLn+1) are coupled to the sense amplifier circuits (SA0, SA2, .., San+1) to couple even bit lines to select the transistor TRe, even bits. The line selection transistor TRe controls its conduction/non-conduction by the even bit line selection signal BLSe to which the gate is coupled. The even bit line selection signal BLSe and the odd bit line selection signal BLSo are driven by the controller 140 or the row selection circuit 170. When the selection signals BLSo and BLSe are driven by the high voltage level, the even and odd bits are turned on. Line select transistor TRe, TRo, sense amplifier circuit, check The data read by the bit line is used as a page register to temporarily write to the memory unit data. The memory bank 100R, not shown, is also coupled to the page register/detection circuit 160 having n+1 bits.

Referring again to FIG. 1, the input/output data buffer 110 transfers data between the address data 120, the data register 130, and the controller 140. The command, data, and address information transmitted from the memory controller (not shown) are supplied to the controller 140, the address register 120, and the data register 130 through the input/output data buffer 110. Further, at the time of reading, the data read from the page register/detection circuit 160 is transferred to the input/output data buffer 110 through the data register 130.

The controller 140 controls the programs such as reading, programming, or deletion based on the command data received from the input/output data buffer 110. For example, the controller 140 recognizes the address information and the write data according to the command data. The former is transmitted by the word line selection circuit 150 or the row selection circuit 170 through the address register 120, and the latter is transmitted through the data register 130. Transmitted by page register/detection circuit 160.

The word line selection circuit 150 decodes the upper bits of the column address information from the address register 120, and turns on the selection transistors TR1, TR2 by selecting the gate signals SGS, SDS based on the decoding result. Therefore, a pair of blocks in the same column direction of the left and right memory groups 100L and 100R can be simultaneously selected. In addition, the word line selection circuit 150 decodes the remaining bits in the column address information, selects a word line in a pair of blocks according to the decoding result, and provides the selected word line and the unselected word line. The required voltage. Selected in the two memory groups 100L, 100R according to the above manner Select each page within a pair of blocks. In summary, the word line selection circuit 150 simultaneously accesses two pages.

In the present embodiment, the word line selection circuit 150 performs different reading operations correspondingly according to the control signal C1 of the controller 140. In a preferred embodiment of the present invention, a memory controller (not shown) can transmit two opposite read commands to the semiconductor memory 10. The first type of read command is for flexible page selection to select pages of adjacent columns of the selected pair of blocks. The second read command is a traditional standard selection to select the pages of the same column in the selected pair of blocks.

The page register/detection circuit 160, as shown in FIG. 1, is coupled to the data register 130 for transmitting the read data to the data register 130 according to the read write command, and then receiving the data. The write data transmitted by the register 130. The row selection circuit 170 decodes the row address information Ay from the address register 120 and selects the data or bit line temporarily stored by the page register/detection circuit 160 according to the decoding result.

The internal voltage generating circuit 180 generates an internal voltage necessary for each access operation by the control of the controller 140. For example, the write voltage Vpgm is used for the selected word line and the voltage Vpass, and is used for the unselected word line during the stylization, and generates a read voltage for providing the unselected word line and the selected gate line when reading. Vread, which provides the erase voltage Vers of the P well formed by the memory cell array upon deletion. Further, the voltage Vpass of the selection gate line is different from the voltage Vread, and the Vsg generation circuit is further prepared in order to sufficiently turn on the other driving voltage Vsg of the selection transistor.

Write voltage Vpgm for select memory with channel set to 0V The unit is the necessary voltage to inject electrons from the channel to the floating gate by FN tunnel (Fowler-Nordheim tunneling). The voltage Vpass and the read voltage Vread are necessary voltages for turning on data stored in an unselected memory unit. The voltages Vpass, Vread, and the driving voltage Vsg are necessary voltages for sufficiently turning on the selection transistor. The write voltage Vpgm corresponding to the output in the operation mode of the internal voltage generating circuit 180, the write voltage Vpass, the read voltage Vread, and the drive voltage Vsg are related to the selected word line selection circuit 150 according to the input address information and the operation mode. The word line corresponding to the memory cell array and the selected gate lines SGS and SDS.

For example, when the page of the word line WL30 of the block BLK(L) is read in FIG. 2, the read voltage Vread of 0V is supplied to the selected word line WL30, and the read voltage Vread of 4.5V is supplied to the page. The word line of the selected word line WL30 provides 4.5V to the select gate line SGD, provides 4.5V to the select gate SGS, and provides 0V to the common source line SL. In addition, when writing the page of the word line WL30, the write voltage Vpgm of 15~20V is supplied to the selected word line WL30, and the voltage Vpass of 10V is supplied to the unselected word line, and the voltage Vcc is supplied to the selected gate line. SGD, providing 0V to select gate SGS, provides 0V to common source line SL. The list in Fig. 3 is an embodiment showing voltage conditions at the time of deletion, writing, and reading operations. Where F represents floating.

Figure 4 shows a portion of a word line selection circuit 150 in an embodiment of the present invention. The word line selection circuit 150 has a decoding portion 152 for decoding the column address information Ax, and selects the block selection portions 154L, 154R of the block according to the decoding result of the decoding portion 152 and according to the decoding portion 152. The decoding result drives the word line drive sections 156L, 156R of the word line.

The block selection sections 154L and 154R turn on the selection transistors TR1 and TR2 through the gate selection signals SGD and SGS in order to select one of the memory banks 100L and 100R. Thereby, n+1 cell groups NU in the selected block are electrically connected to the bit lines BL1, BL2, . . . , BLn+1.

In addition, regarding the controller 140, when the first read command is sent, that is, when the flexible page is read, the flag is set to logic "1", and when the second read command is sent, that is, the standard page is read. At the time, the flag is set to logic "0". Control signal C1 provides the logical value corresponding to the flag set by decoding portion 152.

The decoding portion 152 performs elastic page reading when receiving the control signal C1 of logic "1". Figure 5a shows an embodiment of an elastic page reading. The decoding portion 152 selects the nth word line (ie, the nth page) in the selected block BLK(L)1, and selects the n+1th word line in the selected block BLK(R)1 ( That is, the n+1th page). As the above reaction, the word line driving portion 156L supplies 0V to the nth word line, providing 4.5V as the read voltage Vread to the unselected word line, and the word line driving portion 156R, providing 0V to the first n+1 word lines provide 4.5V as the read voltage Vread to the unselected word line (refer to the list in Figure 3).

The decoding portion 152 performs standard page reading when receiving a control signal of logic "0". Figure 5b shows an embodiment of standard page reading. The selected nth word line is selected in the selected blocks BLK(L)1, BLK(R)1, and the word line driving portions 156L, 156R provide 0V. To the first n word lines providing 4.5V to unselected word lines.

The decoding portion 152 includes, for example, a counter controlled by the control signal C1, and the control signal C1 is in a logic "1" state, and the order of the selected character lines of the selected block BLK(L)1 is in order. Incremental or sequential decrement, and in the case where the control signal C1 is logic "0", it can be set as an increment or decrement for stopping the counter. Of course, the decoding portion 152 can be composed of circuits other than the counter, and contiguous word line switching of n+1 or n-1 can be performed. In addition, the order of the right page can be changed to n+1 or n-1, and the order of the left page can be changed to n+1 or n-1.

Next, a flowchart of FIG. 6 will be referred to to explain a read operation of a semiconductor memory according to an embodiment of the present invention. First, the controller 140 interprets the received read command "00h" according to the command latch enable signal (S101), and then sets the column address and the row address to the address register 120 according to the address latch enable signal. (S102). Next, the controller 140 determines whether the received row address information Ay belongs to the row address range 0000-00FF of the left page of the memory bank 100L (S103).

The controller 140 sets the flag to 0 when the row address is determined to belong to the condition of the left page (S104), and when the row address is determined not to belong to the situation of the left page, that is, the read When the row address is judged to belong to the situation on the right page, the flag is set to 1 (S105). The controller 140 is then preset to the read mode (S106).

Then, the controller 140 receives the start command read according to the command latch enable signal (S107), and determines whether the command is the first read command "3?h" or the second read command "30h" (S108). ), in the second reading When the command "30h" is taken, the address of the word line of the word line selection circuit 150 is set (S109). In other words, the controller 140 selects the left page and the nth word line of the right page (S110). On the other hand, at the first read command, the word line selection circuit 150 selects the nth word line of the left page and selects the n+1th word line of the right page according to the control signal C1 ( S112). The reading of the left and right side pages is performed in accordance with the selection of the character line (S113). The data transmitted by the page buffer is sequentially transferred to the data register 130 according to the increment of the page address.

Figures 7a-7d are diagrams showing an embodiment of an operation for flexible page reading in accordance with the present invention, and Figures 8a-8d are diagrams showing standard page reading operations. Figure 7a shows an embodiment in which each page of memory banks 100 L, 100 R has 256 bytes. Regarding the wraparound read operation, when the latency is set to 512 bytes, the two pages of data stored in the page register are sequentially transferred to the outside. For this reason, the time for setting the row address, transferring the page selected by the memory banks 100L, 100R to the page register is about 12 μs, and if the frequency of outputting the 1-bit data from the page register is 50 MHz, then the frequency is 50 MHz. It takes 10 μs to output 512 bits. Thus, as shown in Fig. 7c, it takes about 22 μs to read the selected page.

In the 7th figure, when the flexible page is read, the left page selects the second page, and the right page selects the first page. If the data is read from the row address "0140", as shown in Fig. 7d, the time required to read the data is 22 μs.

The reading in Figures 8a-8b corresponds to 7a-7b. As shown in Fig. 8b, in the case of wraparound reading from page 1 to page 2, as shown in Fig. 8d, it takes 12 μs to read the first page, in case If the page address "0140" is output sequentially, 3.5 μs is required, and then it takes 12 μs to read the second page. This data output requires 5 μs, which takes 10.5 μs.

According to the semiconductor memory of the embodiment of the invention, the elastic page reading or the standard page reading can be selectively performed, so that the fast page reading can be completed.

In the above embodiment, regarding the elastic page reading, although the nth page and the adjacent n+1th page are selected, the similar combination of the nth page and the n+2th page may also be used. .

In the above embodiment, although the two memory groups are simultaneously accessed by way of example, the number of memory groups simultaneously accessed may be two or more. For example, the flash memory of the four memory groups that can be simultaneously accessed can be different pages, such as the nth page, the n+1th page, the n+th page in the case of performing elastic page reading. 2 pages, n+3 pages, or partial page repetition, such as the combination of the nth page, the nth page, the n+1th page, and the n+1th page. The combination of pages can also be selected as needed.

While the preferred embodiment of the present invention has been described in detail, the invention is not limited thereto, and various modifications and changes can be made without departing from the scope of the invention.

10‧‧‧Semiconductor memory

100‧‧‧Memory Cell Array

110‧‧‧Input and output buffers

120‧‧‧ address register

130‧‧‧data register

140‧‧‧ Controller

150‧‧‧word line selection circuit

152‧‧‧Decoding part

154L, 154R‧‧‧ block selection

156L, 156R‧‧‧ character line drive part

160‧‧‧Page register/detection circuit

170‧‧‧ row selection circuit

180‧‧‧Internal voltage generation circuit

Ax‧‧‧ column address message

Ay‧‧‧ address information

BL1, BL2, BLn, BLn+1‧‧‧ bit line

BLK(L)1, BLK(L)2, BLK(L)m+1, BLK(R)1, BLK(R)2, BLK(R)m+1‧‧‧ blocks

BLSo, BLSe‧‧‧ selection signal

C1, C2, C3‧‧‧ control signals

MA‧‧‧ memory array

MC0, MC29, MC30, MC31‧‧‧ memory unit

NU‧‧ unit group

PB‧‧‧ page register

SA1, SA2, SAn, SAn+1‧‧‧ Sense amplifier circuit

SDS, SGD, SGS‧‧‧ select gate line

SL‧‧‧Common source line

TR1, TR2, TRe, TRo‧‧‧ select transistor

Vcc, Vers, Vpgm, Vread, Vpass‧‧‧ voltage

WL0, WL29, WL30, WL31, WLn-1, WLn, WLn+1‧‧‧ character lines

Fig. 1 is a block diagram showing the general composition of a semiconductor memory device according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing the composition of a typical unit group of the memory cell array shown in Fig. 1.

Figure 3 shows the deletion, writing and reading of semiconductor memory. A list of one of the embodiment of the voltage conditions during operation.

Figure 4 is a block diagram showing the construction of an embodiment of a word line selection circuit in accordance with an embodiment of the present invention.

Figures 5a-5b are diagrams showing an elastic page reading operation and a standard page reading operation in accordance with an embodiment of the present invention.

Figure 6 is a flow chart showing the reading operation of the embodiment of the present invention.

Figures 7a-7d are timing diagrams showing elastic readings in accordance with embodiments of the present invention.

Figures 8a-8d show timing diagrams for traditional standard page reads.

Figures 9a-9d are diagrams showing the reading operation of a conventional flash memory.

S101~S103‧‧‧ Process steps

Claims (11)

A semiconductor memory device comprising: a memory cell array having at least two memory banks simultaneously accessible, the memory groups comprising a plurality of memory cells arranged in a matrix, the gates of the columns of the memory cells Couplingly coupled to the corresponding word line, and each row is coupled to the corresponding bit line; a first receiving device for receiving the address information; and a second receiving device for receiving one of the related access actions a word line selecting means for decoding a column address message received by the first receiving device, and selecting a word line according to the decoding result thereof; and a control device according to the second receiving device The command controls the word line selection device; wherein the control device causes the word line selection device to perform a first read operation according to a first read command, and selects the word line according to a second read command The device performs a second read operation; the first read operation selects an nth word line in one of the groups of memory groups, and selects an n+1th in another group of the memory groups Or the n-1th word a second line; the second read operation selects an nth word line in one of the groups of memory groups, and selects an nth word line in another group of the memory groups. The semiconductor memory device of claim 1, wherein the nth word line and the n+1th or n-1th word line are in two The groups of memory are adjacent in the column direction. The semiconductor memory device of claim 1, wherein the control device further determines whether a row address message received by the first receiving device is included in a row address range of another group of the memory groups. And when the row address information is judged to be included in the range of the row address, the character line selecting means performs the first reading operation according to the first read command. The semiconductor memory device of claim 1, wherein the control device, when determining that the row address information is not included in the row address range of another group of the memory groups, is not based on the A read command causes the word line selection device to perform the second read operation. The semiconductor memory device of claim 1, further comprising: a first page register and a second page register coupled to each of the memory groups via a bit line, wherein the first page The temporary register and the second page register are configured to temporarily store the first read operation and the data read by the second read operation. The semiconductor memory device of claim 1 further includes a row selecting device for decoding a row address signal, and selecting the first page register and the second page register according to the decoding result thereof. data. The semiconductor memory device of claim 1, wherein the semiconductor memory is a NAND type flash memory. A memory device reading program is applicable to a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array having at least two memory groups simultaneously accessible, the memory groups a plurality of memory cells arranged in a matrix, the gates of the columns of the memory cells are commonly coupled to corresponding word lines, and each row is coupled to a corresponding bit line, and has a word line selection device according to The decoding result of the column address message selects the word line, and the step includes: determining that the received read command is a first read command or a second read command; if the first read command is determined, Then, the word line selecting means performs a first reading operation; and if it is determined to be the second reading command, the word line selecting means performs a second reading operation; wherein the first reading operation Selecting an nth word line in one of the groups of memory groups, and selecting an n+1th or n-1th word line in another of the groups of memory groups; and the second read The fetch operation selects the nth word line from one of the groups of memory groups, and selects the nth word line in another set of the memory groups. The memory device reading program of claim 8 further includes: determining whether a row address message received by the first receiving method is included in a row address range of another group of the memory groups; And when the row address message is determined to be included in the row address range, setting a first flag message, and when the row address message judgment is not included in the row address range, setting a second flag a first message, wherein the first read operation is performed when the first read command and the first flag message are set; The second read operation is performed when the second read command and the second flag message are set. A semiconductor memory device reading method is applicable to a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array having at least two memory groups simultaneously accessible, and the memory groups include a matrix a plurality of memory cells, wherein the gates of the columns of the memory cells are commonly coupled to the corresponding word line, and each row is coupled to the corresponding bit line, and the word line selection device has a message according to the column address The decoding result selects the word line, and the step includes: determining that the received read command is a first read command or a second read command; if the first read command is determined, the character is The line selecting means performs a first reading operation; and if it is determined to be the second reading command, the word line selecting means performs a second reading operation; wherein the first reading operation is performed One of the groups of memory groups selects the nth word line, and selects the n+1th or n-1th word line in another group of the groups of memory; and the second read operation is One of the groups of memory groups selects nth Yuan line, and selects the n-th word lines in the other group of those memory group. The method for reading a semiconductor memory device according to claim 10, further comprising: determining whether a row address message received by the first receiving method is included in a row address range of another group of the memory groups ;as well as When the row address message is determined to be included in the row address range, a first flag message is set, and when the row address message judgment is not included in the row address range, a second flag is set. a message, wherein the first read operation is performed when the first read command and the first flag message are set; the second read operation is performed by the second read command and the The operation is performed when the two flag message is set.