TWI453661B - Low power column bypass multiplier, low power line bypass multiplier, row bypass addition unit, column bypass addition unit - Google Patents

Description

Low power column bypass multiplier, low power row bypass multiplier, row bypass addition unit, column bypass addition unit

The present invention relates to a multiplier, a unit, and more particularly to a low power column bypass multiplier, a low power row bypass multiplier, a row bypass adder, and a column bypass adder.

Conventional array multipliers have the problem of large dynamic power consumption, so in the literature [1] "J.Ohban, VG Moshnyaga, and K. Inoue, "Multiplier Energy Reduction Through Bypassing of Partial Products," Asia-Pacific Conf.on Circuits and Systems. vol. 2, pp. 13-17, 2002., [2] "MCWen, SJ Wang and YMLin, "Low Power Parallel Multiplier with Column Bypassing," IEEE International Symposium on Circuits and Systems, Pp.1638-1641, 2005." respectively, an existing column bypass multiplier and an existing row bypass multiplier for solving the problem of large dynamic power consumption, and the column bypass multiplier has multiple column bypasses The addition unit CB, as shown in FIG. 1, has three tri-state buffers t1 to t3, a full adder FA, and a selector 10. Further, the operation of the tristate buffers t1 to t3, the full adder FA, and the selector 10 of the column bypass addition unit CB can be referred to the literature [1], and therefore will not be repeated.

The row bypass multiplier has a plurality of row bypass addition units RB. As shown in FIG. 2, the row bypass addition unit RB has two tristate buffers t1~t2, a full adder FA, and a selection. Device 11. In addition, the tristate buffers t1~t3, the full adder FA, and the selector 11 of the bypass adder unit RB can be operated by themselves. Reference [2], so it is not repeated.

However, the disadvantages of existing column bypass multipliers and row bypass multipliers are: Since the column bypass addition unit CB and the row bypass addition unit RB use a tristate buffer, a floating node problem occurs, which causes leakage power consumption to rise. It also causes the transistor (not shown) in the full adder FA to be incompletely closed, resulting in an increase in leakage power consumption (or static power consumption).

Accordingly, it is a first object of the present invention to provide a low power column bypass multiplier that addresses floating point problems to reduce power consumption.

The low power column bypass multiplier is adapted to multiply a multiplicand multiplicand by a multi-bit multiplier to produce a multi-bit product, the low power column bypass multiplier comprising: a portion of the product Generating a module, generating a plurality of partial products according to the multiplicand and the multiplier, each partial product being a result of multiplying one of the multiplicands by one of the multipliers; and one column of bypass processing The module is processed according to the multiplier and a part of the partial products to obtain a set of processing results, the column bypass processing module includes at least one column bypass adding unit, and the column bypass adding unit has: And an adder for receiving three input signals and performing addition to obtain a carry signal and an add signal; a power gate controller electrically connected to the full adder and receiving a control signal, and supplying power according to the control signal The full adder and the non-power supply switch between the full adder; and an output selector that receives the control signal and is electrically connected to the full adder to receive the carry signal and the add signal, and according to the control signal Logical level Selecting an output between the carry signal and a carry value as a carry output, and selecting an output between the add signal and one of the three input signals as an add output according to a logic level of the control signal; The carry value of the output selector of each column bypass adder unit is a combination of the carry output selected from the remaining column bypass adder units and a logic 0; the three inputs of the full adder of each column bypass add unit The signal is selected from the partial product, the carry output of the remaining column bypass addition unit, and the combination of the output and the logic 0; the control signal of each column bypass addition unit is from one of the multipliers a bit result; the processing result is selected from the combination of the carry output and the added output; an adding module performs addition according to the partial product and a part of the set of operation results to obtain a set of addition results; Wherein, each element of the product is a combination selected from the partial product, the set of processing results, and the set of addition results.

A second object of the present invention is to provide a low power line bypass multiplier that addresses floating point problems to reduce power consumption.

The low power row bypass multiplier is adapted to multiply a multiplicand multiplicand by a multi-bit multiplier to produce a multi-bit product, the low power row bypass multiplier comprising: a portion of the product Generating a module, generating a plurality of partial products according to the multiplicand and the multiplier, each partial product being a result of multiplying one of the multiplicands and one of the multipliers; one line of bypass processing The array is processed according to the multiplicand and a part of the partial products to obtain a set of processing results, the processing module includes at least one row bypass adding unit, and the row bypass adding unit has: a full adder, For receiving three input signals and performing addition to obtain a carry output and an add signal; a power gate controller electrically connected to the full adder and receiving a control signal, and supplying power to the full add according to the control signal And not supplying power to the full adder; and an output selector receiving the control signal and electrically connecting to the full adder to receive the carry signal and the plus signal, and according to a logic level of the control signal In that Selecting an output between the signal and one of the three input signals as an additive output; the three input signals of the full adder of each line of the bypass addition unit are selected from the partial products, and the remaining line bypass additions The carry output of the unit, the combination of the output and a logic 0; the control signal of each line of the bypass addition unit is one of the bits from the multiplicand; the result of the processing is selected from the carry output and the a combination of equal addition and output; an addition module performs addition according to the partial product and a part of the operation result of the group to obtain a set of addition results; wherein each element of the product is selected from the partial product, A combination of the set of processing results and the set of addition results.

A third object of the present invention is to provide a column bypass addition unit that solves the floating point problem to reduce power consumption.

The column bypass addition unit comprises: a full adder for receiving three input signals and performing addition to obtain a carry signal and an add signal; a power gate controller electrically connected to the full adder and receiving a control a signal, and switching between supplying power to the full adder and not supplying power to the full adder according to the control signal; and an output selector receiving the control signal and electrically connecting the full adder to receive the carry signal and And adding a signal according to a logic level of the control signal to select an output between the carry signal and a carry value as a carry output, and according to a logic level of the control signal, the plus signal and the three inputs An output is selected between one of the signals as an additive output.

A fourth object of the present invention is to provide a line bypass addition unit that solves the floating point problem to reduce power consumption.

The line bypass adding unit comprises: a full adder for receiving three input signals and performing addition to obtain a carry output and an add signal; a power brake device electrically connected to the full adder and receiving one Controlling a signal and switching between supplying power to the full adder and not supplying power to the full adder according to the control signal; and an output selector receiving the control signal and electrically connecting to the full adder to receive the carry signal And adding the signal, and selecting an output between the added signal and one of the three input signals as an added output according to a logic level of the control signal.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

<Low power column bypass multiplier>

As shown in Figures 3 and 4, a preferred embodiment of the low power column bypass multiplier RMUL of the present invention is applicable to a multiplicand multiplicand (Y = y _{m - 1} y _{m - 2} ... y ₀ , m>1) is multiplied by a multi-bit multiplier (X=x _n-1 x _n-2 ... x ₀ , n>1) to produce a multi-bit product (P=p _m+n-1 p _m+n-2 ... p ₀ ), and in FIG. 4, m=n=4 is taken as an example. The low power column bypass multiplier RMUL includes: a partial product generation module PM, and a column of bypass processing modules. RBM, and an additive module AM.

The partial product generation module PM generates a plurality of partial products according to the multiplicand and the multiplier (y _i x _j , i=0, 1, ..., m-1, j=0, 1, ... , n-1), each partial product is the result of multiplying one of the multiplicands by one of the multipliers. In this embodiment (not shown), the AND gate is used. And the one bit of the multiplicand is summed with one of the bits of the multiplier to obtain the partial product.

The column bypass processing module RBM processes the multiplier and a part of the partial products (in this embodiment, except for x ₀ , y ₀ x ₀ , y _m-1 x _n-1 ) to obtain As a result of the processing, the column bypass processing module RM includes at least one column of the bypass addition unit RBU. As shown in FIG. 5, the column bypass addition unit RBU has a full adder FA and a power brake 20. And an output selector 21.

The full adder FA is configured to receive three input signals and perform addition operations to obtain a carry signal and an add signal.

The power gate controller 20 is electrically connected to the full adder FA and receives a control signal, and switches between supplying power to the full adder FA and not supplying power to the full adder FA according to the control signal, and the power gate The controller 20 has an inverter INV, a first switch M1, and a second switch M2.

The inverter INV receives the control signal and inverts the logic of the control signal to obtain an inverted signal.

The first switch M1 has a first end receiving a bias voltage VDD, a second end electrically connected to the corresponding full adder FA, and an electrical connection to the inverter INV to receive the inverted signal The control terminal switches the first and second ends between conduction and non-conduction according to the inverted signal.

The second switch M2 has a first end receiving a ground voltage GND, a second end electrically connected to the corresponding full adder FA, and a control end receiving the control signal, and according to the control signal The first and second ends are switched between conducting and non-conducting.

When the control signal turns on the first switch M1 and the second switch M2, the bias voltage VDD and the ground voltage GND are transmitted to the full adder FA to supply power to the full adder FA, and the control is performed. When the signal causes the first switch M1 and the second switch M2 to be non-conducting, the bias voltage VDD and the ground voltage GND are not transmitted to the full adder FA to supply power to the full adder FA.

In this embodiment, the first switch M1 is a P-type MOS field effect transistor, and the first end, the second end, and the control end of the first switch M1 are a source, a drain, and a gate, respectively. The second switch M2 is an N-type MOS field effect transistor, and the first end, the second end and the control end of the second switch M2 are a source, a drain and a gate, respectively.

The output selector 21 receives the control signal and is electrically connected to the full adder FA to receive the carry signal and the add signal, and select a one between the carry signal and a carry value according to the logic level of the control signal. The output is a carry output, and an output is selected as an add-on output between the plus signal and one of the three input signals according to a logic level of the control signal, the output selector 21 having a carry multiplexer CM, and one plus multiplexer SM.

The carry multiplexer CM receives the carry value, the carry signal, and the control signal. When the control signal is logic 1, the carry multiplexer CM selects the carry signal as the carry output, and when the control signal is logic At 0 o'clock, the carry multiplexer CM selects the carry value as the carry output.

The adder multiplexer SM receives the plus signal, one of the three input signals, and the control signal. When the control signal is logic 1, the adder multiplexer SM selects the plus signal as the added output. When the control signal is logic 0, the adder multiplexer SM selects one of the three input signals as the added output.

The carry value of the output selector 21 of each column bypass adder unit RBU is a combination of the carry output selected from the remaining column bypass adder units and a logical zero. The three input signals of the full adder FA of each column bypass addition unit RBU are selected from the partial output, the carry output of the remaining column bypass addition units, the combination of the added output and a logic 0. The control signal for each column bypass addition unit RBU is one of the bits from the multiplier. The result of the processing is selected from the combination of the carry output and the added output.

The adding module AM performs addition according to the partial products and a part of the set of operation results to obtain a set of addition results. Wherein, each element of the product is a combination selected from the partial product, the set of processing results, and the set of addition results.

As shown in Figures 6 and 7, a preferred embodiment of the low power row bypass multiplier CMUL of the present invention is applicable to a multiplicand multiplicand (Y = y _{m - 1} y _{m - 2} ... y ₀ , m>1) multiplied by a multi-bit multiplier (X=x _n-1 x _n-2 ... x ₀ , n>1) to produce a multi-bit product (P=p _{m +n-1} p _m+n-2 ... p ₀ ), and in FIG. 7 , m=n=4 is taken as an example. The low power row bypass multiplier CMUL includes: a partial product generation module PM, A row of bypass processing modules CBM, and an adder module AM.

The partial product generation module PM generates a plurality of partial products according to the multiplicand and the multiplier (y _i x _j , i=0, 1, ..., m-1, j=0, 1, ... , n-1), each partial product is the result of multiplying one of the multiplicands by one of the multipliers.

The row bypass processing module CBM processes according to the multiplicand and a part of the partial products (in this embodiment, except y _m , y ₀ x ₀ , y _m-1 x _n-1 ) Obtaining a set of processing results, the row bypass processing module CBM includes at least one row bypass addition unit CBU. As shown in FIG. 8, the row bypass addition unit CBU has: a full adder FA, and a power brake 20 And an output selector 21.

The full adder FA is configured to receive three input signals and perform addition operations to obtain a carry output and an add signal.

The power gate controller 20 is electrically connected to the full adder FA and receives a control signal, and switches between supplying power to the full adder FA and not supplying power to the full adder FA according to the control signal, and the power gate The detailed components of the controller 20 are as described above and will not be described again.

The output selector 21 receives the control signal and is electrically connected to the full adder FA to receive the carry signal and the plus signal, and according to the logic level of the control signal, in the plus signal and the three input signals An output is selected as an add-on output, and the output selector 21 has a multi-multiplexer SM.

The adder multiplexer SM receives the plus signal, one of the three input signals, and the control signal. When the control signal is logic 1, the adder multiplexer SM selects the plus signal as the added output. When the control signal is logic 0, the adder multiplexer SM selects one of the three input signals as the added output.

The three input signals of the full adder FA of each row of the bypass addition unit CBU are selected from the partial output, the carry output of the remaining line bypass addition units, the combination of the addition output and a logic 0. The control signal for each row of the bypass addition unit CBU is one of the bits from the multiplicand. The result of the processing is selected from the combination of the carry output and the added output.

The adding module AM performs addition according to the partial products and a part of the set of operation results to obtain a set of addition results. Wherein, each element of the product is a combination selected from the partial product, the set of processing results, and the set of addition results.

<Experimental results>

As shown in Figure 9, for the comparison of dynamic power consumption, where Base refers to the traditional array multiplier, [1] is the column bypass multiplier of the literature [1], and [2] is the row bypass of the literature [2]. The multiplier, P1 is the low power column bypass multiplier proposed in the above embodiment, and P2 is the low power row bypass multiplier proposed in the above embodiment, in order to calculate the average dynamic power consumption, respectively 4×4 bit, 8×8 bit, 16×16 bit multiplier input, using fifty random data to do the simulation test, the randomly generated multiplicand and multiplier, The probability of setting 0 and 1 each is about 50%. It can be seen from Fig. 9 that in the multiplier result of 16×16 bits, compared with [1], P1 can save 35.56%, and compared with [2], P2 can save 14.53%.

As shown in Fig. 10, it is a comparison of the number of transistors of each multiplier. In the 16×16-bit multiplier result, P1 can be reduced by 8% compared with [1], and P2 can be reduced by 4% compared with [2].

As shown in FIG. 11, it is a leakage power consumption simulation test result of a 16×16-bit multiplier. The simulation test of leakage current power consumption is divided into three cases, in order:

Best case: All input data bits are zero. Average case: Half of the input data bits are 0, and half of the input data is 1 worst case (worst case): all input data bits are 1.

In the long standby state (that is, when the input voltage of the circuit does not change for a long time), in the best case and average case, [1] and [2] have higher leakage current power. Consumption (or static power consumption) is due to the fact that they have a floating node problem. On average, compared with [1], P1 of this embodiment can save 51.83%. Compared with [2], P2 of this embodiment can save 59.19%.

In summary, the above embodiment has the following advantages:

1. The power gate controller 20 replaces the tristate buffer, which can solve the floating point problem and save more static power consumption.

2. The power gate controller 20 has a smaller number of transistors used relative to the tristate buffer, and can reduce dynamic power consumption.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

RMUL. . . Low power column bypass multiplier

CMUL. . . Low power line bypass multiplier

PM. . . Partial product generation module

RBM. . . Column bypass processing module

AM. . . Addition module

RBU. . . Column bypass addition unit

CBU. . . Line bypass addition unit

FA. . . Full adder

20. . . Power brake

M1. . . First switch

M2. . . Second switch

INV. . . inverter

twenty one. . . Output selector

CM. . . Carry multiplexer

SM. . . Add multiplexer

VDD. . . bias

GND. . . Ground voltage

1 is a circuit diagram of a conventional column bypass addition unit;

2 is a circuit diagram of a conventional line bypass addition unit;

3 is a circuit diagram of a preferred embodiment of the low power column bypass multiplier of the present invention;

4 is a circuit diagram of a 4x4 low power column bypass multiplier of the preferred embodiment;

Figure 5 is a circuit diagram of a column bypass addition unit of the preferred embodiment;

Figure 6 is a circuit diagram of a preferred embodiment of the low power row bypass multiplier of the present invention;

Figure 7 is a circuit diagram of a 4x4 low power line bypass multiplier of the preferred embodiment;

Figure 8 is a circuit diagram of the row bypass adding unit of the preferred embodiment;

Figure 9 is a comparison diagram of dynamic power consumption of various multipliers;

Figure 10 is a comparison of the number of transistors of various multipliers; and

Figure 11 is a graph comparing the leakage current power consumption of various multipliers.

RBU‧‧‧column addition unit

FA‧‧‧ full adder

20‧‧‧Power brakes

M1‧‧‧ first switch

M2‧‧‧ second switch

INV‧‧‧Inverter

21‧‧‧Output selector

CM‧‧‧ carry multiplexer

SM‧‧‧plus multiplexer

VDD‧‧‧ bias

GND‧‧‧ ground voltage

Claims (16)

A low power column bypass multiplier adapted to multiply a multiplicand multiplicand by a multiplicity multiplier to produce a multiplicity product, the low power column bypass multiplier comprising: a portion Generating a module, generating a plurality of partial products according to the multiplicand and the multiplier, each partial product being a result of multiplying one of the multiplicands by one of the multipliers; and one column bypassing Processing the module, processing according to the multiplier and a part of the partial products to obtain a set of processing results, the column bypass processing module includes at least one column bypass adding unit, the column bypass adding unit has: a full adder for receiving three input signals and performing addition to obtain a carry signal and an add signal; a power gate controller electrically connected to the full adder and receiving a control signal, and being powered according to the control signal Switching between the full adder and no power supply to the full adder; and an output selector receiving the control signal and electrically connecting to the full adder to receive the carry signal and the plus signal, and according to the control signal Logic Selecting an output between the carry signal and a carry value as a carry output, and selecting an output between the added signal and one of the three input signals as a plus according to a logic level of the control signal Output; the carry value of the output selector of each column bypass adder unit is a combination of the carry output selected from the remaining column bypass adder units and a logic 0; the full adder of each column bypass add unit The three input signals are selected from the partial products, the carry output of the remaining column bypass adder units, and the combination of the added output and the logic 0; the control signal of each column bypass adder unit is derived from the multiplier One of the elements; the processing result is selected from the combination of the carry output and the added output; an adding module, adding according to the partial product and a part of the set of operation results to obtain a set of addition a result; wherein each of the elements of the product is a combination selected from the partial product, the set of processing results, and the set of addition results. The low power column bypass multiplier of claim 1, wherein the power gate has: an inverter that receives the control signal and inverts logic of the control signal to obtain an inversion a first switch having a first end receiving a bias voltage, a second end electrically coupled to the corresponding full adder, and an electrical connection coupled to the inverter for receiving the inverted signal a control terminal, and switching the first and second ends between the conduction and the non-conduction according to the inverted signal to supply the bias to the full adder; and a second switch having a voltage for receiving a ground The first end is electrically connected to the corresponding second end of the full adder, and a control end receiving the control signal, and according to the control signal, the first end and the second end are between conducting and non-conducting Switch. The low power column bypass multiplier according to claim 2, wherein the first switch is a P-type MOS field effect transistor, and the first end, the second end, and the control of the first switch The terminals are source, drain and gate. The low power column bypass multiplier according to claim 2, wherein the second switch is an N-type MOS field effect transistor, and the first end, the second end, and the control of the second switch The terminals are source, drain and gate. The low power column bypass multiplier according to claim 1, wherein the output selector has: a carry multiplexer, receiving the carry value, the carry signal, and the control signal, when the control signal When it is logic 1, the carry multiplexer selects the carry signal as the carry output. When the control signal is logic 0, the carry multiplexer selects the carry value as the carry output; and a multiplexer receives The plus signal, one of the three input signals, and the control signal, when the control signal is logic 1, the adder multiplexer selects the plus signal as the added output, when the control signal is logic 0, The adder multiplexer selects one of the three input signals as the added output. A low power row bypass multiplier adapted to multiply a multiplicand multiplicand by a multibit multiplier to produce a multiplicity product, the low power row bypass multiplier comprising: a portion The product generation module generates a plurality of partial products according to the multiplicand and the multiplier, each partial product being a result of multiplying one of the multiplicands by one of the multiplicatives; Processing the array, processing according to the multiplicand and a part of the partial products to obtain a set of processing results, the processing module comprising at least one line bypass adding unit, the line bypass adding unit having: a full adder , for receiving three input signals and performing addition to obtain a carry output and an add signal; a power gate controller electrically connected to the full adder and receiving a control signal, and supplying power according to the control signal An adder and a non-power supply switch between the full adder; and an output selector that receives the control signal and is electrically connected to the full adder to receive the carry signal and the add signal, and according to a logic of the control signal Bit Selecting an output between the plus signal and one of the three input signals as an added output; the three input signals of the full adder of each line of the bypass addition unit are selected from the partial product, the remaining lines The carry output of the adder unit, the combination of the output and a logic 0; the control signal of each line of the adder unit is one of the bits from the multiplicand; the result of the processing is selected from the carry output a combination of the addition and output; an addition module, performing addition according to the partial product and a part of the operation result of the group to obtain a set of addition results; wherein each element of the product is selected from the parts A combination of the product, the set of processing results, and the set of addition results. The low power row bypass multiplier of claim 6, wherein the power gate has: an inverter that receives the control signal and inverts logic of the control signal to obtain a reverse a first switch having a first end receiving a bias voltage, a second end electrically coupled to the corresponding full adder, and an electrical connection coupled to the inverter for receiving the inverted signal a control terminal, and the first and second ends are switched between conducting and non-conducting according to the inverted signal to supply the bias voltage to the full adder; and a second switch having a receiving ground voltage The first end is electrically connected to the corresponding second end of the full adder, and a control end receiving the control signal, and the first and second ends are turned on and off according to the control signal. Switch between. The low power row bypass multiplier according to claim 7, wherein the first switch is a P-type MOS field effect transistor, and the first end, the second end, and the control of the first switch The terminals are source, drain and gate. The low power row bypass multiplier according to claim 7, wherein the second switch is an N-type metal oxide half field effect transistor, and the first end, the second end and the second switch of the second switch The terminals are source, drain and gate. The low power row bypass multiplier according to claim 6, wherein the output selector has: a multi-multiplexer, receiving the added signal, one of the three input signals, and the control signal When the control signal is logic 1, the adder multiplexer selects the plus signal as the added output. When the control signal is logic 0, the adder selects one of the three input signals as the plus Output. A column bypass adding unit comprises: a full adder for receiving three input signals and performing addition to obtain a carry signal and an add signal; a power brake device electrically connected to the full adder and receiving a Controlling a signal and switching between supplying power to the full adder and not supplying power to the full adder according to the control signal; and an output selector receiving the control signal and electrically connecting to the full adder to receive the carry signal And adding the signal, and selecting an output between the carry signal and a carry value as a carry output according to a logic level of the control signal, and according to a logic level of the control signal, the added signal and the three An output is selected between one of the input signals as an additive output. According to the bypass bypass adding unit of claim 11, the power gate controller has: an inverter, receiving the control signal and inverting logic of the control signal to obtain an inverted signal; a switch having a first end receiving a bias voltage, a second end electrically coupled to the corresponding full adder, and a control end electrically coupled to the inverter to receive the inverted signal, and And the first and second ends are switched between conducting and non-conducting according to the inverted signal to supply the bias to the full adder; and a second switch having a first end for receiving a ground voltage, An electrical connection is connected to the corresponding second end of the full adder, and a control end receiving the control signal, and the first and second ends are switched between conducting and non-conducting according to the control signal. According to the column bypass adding unit described in claim 11, the output selector has: a carry multiplexer, receiving the carry value, the carry signal, and the control signal, when the control signal is logic 1 The carry multiplexer selects the carry signal as the carry output. When the control signal is logic 0, the carry multiplexer selects the carry value as the carry output; and a add multiplexer receives the added signal, One of the three input signals, and the control signal, when the control signal is logic 1, the adder multiplexer selects the plus signal as the added output, and when the control signal is logic 0, the multiplication The device selects one of the three input signals as the added output. A line bypass adding unit comprises: a full adder for receiving three input signals and performing addition to obtain a carry output and an add signal; a power brake device electrically connected to the full adder and receiving one Controlling a signal and switching between supplying power to the full adder and not supplying power to the full adder according to the control signal; and an output selector receiving the control signal and electrically connecting to the full adder to receive the carry signal And adding the signal, and selecting an output between the added signal and one of the three input signals as an added output according to a logic level of the control signal. The line bypass adding unit according to claim 14, wherein the power gate controller has: an inverter receiving the control signal and inverting logic of the control signal to obtain an inverted signal a first switch having a first end receiving a bias voltage, a second end electrically coupled to the corresponding full adder, and a control electrically coupled to the inverter for receiving the inverted signal And supplying a bias voltage to the full adder according to the inverted signal, wherein the first and second ends are switched between conducting and non-conducting; and a second switch having a voltage for receiving a ground voltage One end, one electrically connected to the corresponding second end of the full adder, and a control end receiving the control signal, and switching the first and second ends between conducting and non-conducting according to the control signal . The line bypass adding unit according to claim 14, wherein the output selector has: a multi-adder, receiving the added signal, one of the three input signals, and the control signal, when When the control signal is logic 1, the adder multiplexer selects the plus signal as the added output. When the control signal is logic 0, the adder multiplexer selects one of the three input signals as the added output.