TWI441178B - Dual port sram - Google Patents

Description

Double-click static random access memory

The invention relates to a double random static random access memory (SRAM), in particular to a leakage current and can solve the conventional double-bit SRAM write with a single bit line. Enter the logical 1 difficult double-static static random access memory.

Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into non-volatile memory and volatile memory, non-volatile memory, and stored according to whether it can save data after the power is turned off. It will not disappear due to power off or interruption, and the data stored in volatile memory will be eliminated as the power is turned off or interrupted. Common volatile memory types are dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.

A conventional static random access memory (SRAM), as shown in FIG. 1a, mainly includes a memory array, which is composed of a plurality of memory blocks (MB ₁ , MB). _2, etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells, each column The memory cell and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory crystals One of the cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to one of the plurality of rows of memory cells And each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic diagram of a 6T static random access memory (SRAM) cell, in which PMOS transistors P1 and P2 are called load transistors, and NMOS transistors M1 and M2 are called drivers. Driving transistors, NMOS transistors M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bits, respectively. A complementary bit line, since the SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, cell ratio) is usually set at 2.2 to 3.5. There is a lack of high accumulation and high price.

The HSPICE transient analysis simulation results of the 6T SRAM cell in the write operation shown in Figure 1b, as shown in Figure 2, are simulated in a level 49 model using TSMC 0.18 micron CMOS process parameters. .

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width to length ratio of M2 and M3, there is a problem that writing logic 1 is quite difficult. Considering that node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the write bit line (WBL) alone, it is difficult to write the previously written logic 0 in node A as logic. 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.18 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

To date, many techniques have been proposed for a 5T SRAM cell with a single bit line, such as Non-Patent Document 1 (I. Carlson et al., "A high density, low leakage, 5T SRAM for embedded caches". , "Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 215-218, 2004.) The 5T SRAM is due to the redesign of the two of the unit cell, the two-load transistor And accessing the channel width-to-length ratio of the transistor to solve the problem of writing logic 1 is difficult, thereby causing damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus being susceptible to process variation; 5T SRAM of Non-Patent Document 2 (M. Wieckowski et al., "A novel five-transistor (5T) SRAM cell for high performance cache," IEEE Conference on SOC, pp. 1001-1002, 2005.) The access transistor of the long channel length is disposed between the two load transistors in the unit cell to solve the problem of difficulty in writing the logic 1, thereby causing a lack of access speed; Patent Document 3 (June 1, 1998) TW M358390) "When writing operation The low power supply voltage "SRAM" can effectively solve the problem of writing logic 1, but the write operation is due to the lack of an effective discharge path, resulting in low memory speed and/or high speed operation. Missing.

Next, we discuss the static random access memory (SRAM) and double-ended architecture. The 6T static random access memory (SRAM) cell in Figure 1b is the static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for the reading action, and the other bit line is responsible for the writing action, then the double-click static random access memory is designed. When the body is in memory, there is no need to add two transistors and another pair of bit lines. Memory cell area will be reduced a lot. The reason why the conventional double-squeezing static random access memory cell does not adopt this method is because the problem of writing logic 1 cannot be achieved as described above.

In view of this, the main object of the present invention is to provide a dual-turn static random access memory capable of effectively avoiding the existence of a write-on of a double-埠 static random access memory cell with a single bit line by a control circuit. Entering Logic 1 is quite a difficult problem.

A secondary object of the present invention is to provide a double-turn static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

The present invention provides a double-tweed static random access memory, which mainly comprises a memory array and a plurality of control circuits (2), the memory array is composed of a plurality of memory blocks, each memory block A control circuit is provided, and each memory block further includes a plurality of memory cells (1), and each memory cell (1) is composed of an NMOS access transistor (M3) and two NMOS driving transistors. (M1 and M2), two PMOS load transistors (P1 and P2) and a first and second read transistor (M4 and M5). Each control unit is connected to a source terminal of a second NMOS driving transistor of each memory cell in the corresponding memory block to control source voltages of the source terminals in response to different operating modes, in the write mode And setting a source of the driving transistor (M1) closer to the writing bit line (WBL) in the selected unit cell to a predetermined voltage higher than the ground voltage and selecting another driving transistor in the selected unit cell ( The source voltage of M2) is set to the ground voltage to prevent the difficulty of writing logic 1. In the standby mode, the source voltage of the driving transistor in all the memory cells is set to be higher than the ground voltage. The voltage is predetermined to reduce the leakage current; and in the read mode, the source voltage of the driving transistor in all of the memory cells is set to the ground voltage to maintain read stability. In summary, the double-click static random access memory proposed by the present invention can effectively avoid the problem that the write logic 1 of the SRAM with a single bit line is quite difficult, and can also be combined. Reduce leakage current in standby mode.

According to the above main object, the present invention provides a double-tweed static random access memory, which mainly includes a memory array, the memory array is composed of a plurality of memory blocks, and each memory block further includes There are a plurality of memory cells (1); and a plurality of control circuits (2), each of which is provided with a control circuit (2). It is worth noting here that the memory block can be as simple as a column of memory cells or a row of memory cells.

For convenience of explanation, the double-chip static random access memory shown in FIG. 6 has only one memory cell (1), one write word line (WWL), one bit line (WBL), A read word line (RWL), a read bit line (RBL), and a control circuit (2) are illustrated as embodiments. The memory cell (1) includes a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) and a second inverter (by the second PMOS transistor P2 and a second NMOS transistor M2, a third NMOS transistor (M3), a first read transistor (M4), and a second read transistor (M5), wherein the first The phase converter and the second inverter are connected in an alternating coupling, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter is (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node) B) is used to store the inverted data of the SRAM cell, the third NMOS transistor (M3) is connected between the storage node (A) and the write bit line (WBL), and the gate is connected The write word line (WWL) is used as an access transistor for the memory cell, and the source, gate and drain of the second read transistor (M5) are respectively connected to the ground. Voltage, the input of the second inverter (node B) and a source of the first read transistor (M4), and a source, a gate and a drain of the first read transistor (M4) are respectively connected to the second read The drain of the transistor (M5), the read word line (RWL), and the read bit line (RBL).

Referring again to FIG. 6, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. a crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), and an eleventh NMOS transistor (M28), the first The source of the four NMOS transistor (M21) is connected to the ground voltage, and the gate is connected to the drain and connected to a first low voltage node (VL1); the fifth NMOS transistor (M22) The source, gate and drain are respectively connected to the ground voltage and an inverted standby mode control signal ( And a second low voltage node (VL2), wherein the sixth NMOS transistor (M23) source, gate and drain are respectively connected to the second low voltage node (VL2), a standby mode control signal ( S) and the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) is connected to a ground voltage, the drain is connected to the first low voltage node (LV1), and the gate is connected to a drain of an eighth NMOS transistor (M25), a drain of a ninth NMOS transistor (M26), and a source of a tenth NMOS transistor (M27); a source of the eighth NMOS transistor (M25) a pole, a gate and a drain are respectively connected to a ground voltage, a write word line (WWL) and a gate of the seventh NMOS transistor (M24); a source of the ninth NMOS transistor (M26) The gate and the drain are respectively connected to the ground voltage, the standby mode control signal (S) and the gate of the seventh NMOS transistor (M24); the source and the gate of the tenth NMOS transistor (M27) Connected to the gate of the seventh NMOS transistor (M24) and the inverted word line respectively And a source of an eleventh NMOS transistor (M28); a source, a gate and a drain of the eleventh NMOS transistor (M28) are respectively connected to the tenth NMOS transistor (M27) Pole, the inverting standby mode control signal ( ) with a power supply voltage (V _DD ). It is worth noting here that the inverted standby mode control signal ( ) is obtained by the standby mode control signal (S) via an inverter, and an inverted write word line ( It is also obtained by the write word line (WWL) via an inverter.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and in the write mode, the first The low voltage node (VL1) is set to a predetermined voltage higher than the ground voltage and the second low voltage node (VL2) is set to the ground voltage to prevent the difficulty of writing the logic 1; in the standby mode, the The first low voltage node (VL1) and the second low voltage node (VL2) are set to be higher than the ground voltage by the predetermined voltage to reduce leakage current; and in the read mode, the first low voltage node is VL1) is set to a ground voltage with the second low voltage node (VL2) to maintain read stability. The detailed operating voltage level is shown in Table 1, where the voltage at node C is the gate voltage of the seventh NMOS transistor (M24), and Max (V _TM28 , V _TM27 ) represents the _comparison between V _TM27 and V _TM28 . In larger case, the _VTM27 and _VTM28 represent the threshold voltages of the tenth NMOS transistor (M27) and the eleventh NMOS transistor (M28), respectively, and _VTM21 represents the fourth NMOS transistor. The threshold voltage of (M21), it is worth noting here that the voltage of the first low voltage node (VL1) is V _TM21 when writing 1 and the voltage of the first low voltage node (VL1) when writing 0 It is 0V.

The working principle of the preferred embodiment of the present invention in FIG. 6 is as follows:

(I) Write mode

At this time, the write word line (WWL) is at a logic high level, and the standby mode control signal (S) is a logic low level, and the inverted standby mode control signal ( ) is a logic high level, the logic high level of the inverted standby mode control signal ( The fifth NMOS transistor (M22) in the control circuit (2) can be turned on (ON), and the logic low level of the standby mode control signal (S) causes the sixth NMOS transistor (M23) to be turned off. (OFF), then the voltage of the second low voltage node (VL2) can be pulled down to the ground voltage, and the voltage level of the first low voltage node (VL1) is equal to the fourth NMOS power before the write operation The level of the threshold voltage of the crystal (M21) is used to effectively prevent the problem of writing logic 1 difficult.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed in accordance with the four write states of the binary random access memory cell.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M1) is turned "ON". Since the first NMOS transistor (M1) is (ON), the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned off (OFF) To be ON, at this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M1) is turned "ON". Since the first NMOS transistor (M1) is (ON), when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), The voltage at the node A rises following the voltage of the write word line (WWL).

When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3), the third NMOS transistor (M3) is turned from OFF to ON. Because the write bit line (WBL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M1) is still ON and the node B is still at a voltage level close to the The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor P1 is still turned off (OFF), and the node A is quickly charged toward a divided voltage level, the divided voltage bit The quasi-equal (R _M1 + R _M21 ) / (R _M3 + R _M1 + R _M21 ) is multiplied by the power supply voltage (V _DD ), wherein the R _M3 represents the on-resistance equivalent resistance of the third NMOS transistor (M3) , R _M1 represents the on-resistance equivalent resistance of the first NMOS transistor (M1), and R _M21 represents the on-resistance equivalent resistance of the fourth NMOS transistor (M21), at this time because of the third NMOS transistor (M3) Still operating in the saturation region and the first NMOS transistor (M1) still operates in the triode region, although the conduction equivalent resistance (R _M3 ) of the third NMOS transistor ( _M3 ) will far Turned to the first NMOS transistor (M1) through the equivalent resistance (R _M1), but the system as a fourth NMOS transistor (M21) diodes is connected, thus to the first low voltage node (VL1) A voltage level equal to the gate-source voltage V _GS of the fourth NMOS transistor (M21) is provided, and the voltage-divided voltage level presented by the node A is lower than the conventional 5T of FIG. The voltage level of the node A of the SRAM cell is much higher. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M2), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance equivalent (R _M1 ) of an NMOS transistor (M1) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M1) obtains a higher voltage level at the node A. The higher voltage level of the node A is again caused by a second inverter (composed of the second PMOS transistor P2 and the second NMOS transistor M2), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again passed through a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1), so that the node A obtains a higher voltage level. In this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It should be noted here that the first low voltage node (VL1) has a voltage level equal to the threshold voltage of the fourth NMOS transistor (M21) after writing logic 1.

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P1) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WWL) is greater than the critical value of the third NMOS transistor (M3) At the time of voltage, the third NMOS transistor (M3) is turned from OFF (OFF) to ON (ON); at this time, since the write bit line (WBL) is High (the power supply voltage V _DD ), and because The first PMOS transistor (P1) is still ON, so the voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle. It should be noted here that the first low voltage node (VL1) has a voltage level equal to the threshold voltage of the fourth NMOS transistor (M21) after writing logic 1.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P1) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M3) When the threshold voltage is applied, the third NMOS transistor (M3) is turned from OFF to ON. At this time, since the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete the logic 0 write operation until the end of the write cycle. It is worth noting here that the first low voltage node (VL1) has a level of ground voltage after writing logic zero.

In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, is simulated by the level 49 model and using TSMC 0.18 micron CMOS process parameters. It can be confirmed from the simulation result that the double-turn static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) by writing logic 1, so as to effectively avoid the conventional It is quite difficult to write logic 1 in a double-bit static random access memory cell with a single bit line.

(II) Standby mode

At this time, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal ( ) is a logic low level, the logic low level of the inverted standby mode control signal ( The fifth NMOS transistor (M22) in the control circuit (2) can be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the sixth NMOS transistor (M23) Turning on (ON), the sixth NMOS transistor (M23) is used as an equalizer, so that the sixth NMOS transistor (M23) in an on state can be used to make the first low The voltage level of the voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), so the voltage levels are equal to the threshold voltage level of the fourth NMOS transistor (M21).

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 6, FIG. 6 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ and I ₄ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage is due to the standby mode) The voltage level of the node (VL2) is maintained at the threshold voltage level of the fourth NMOS transistor (M21), so the voltage level of the node A is the logic Low and the threshold voltage of the fourth NMOS transistor (M21) is also maintained. The level of the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Referring to the prior art of FIG. 5 and the embodiment of the present invention of FIG. 6, the comparison between the leakage current of the double-turn SRAM proposed by the present invention and the 8T SRAM of FIG. 5 is first described, firstly, regarding the flow through the third NMOS. The leakage current I _{1 of the} transistor (M3), because the voltage level of the node A in the standby mode is maintained at the threshold voltage level of the fourth NMOS transistor (M21), and the write word line is assumed (WWL) is set to the ground voltage in the standby mode, so the gate-source voltage V _GS of the third NMOS transistor (M3) of the present invention is a negative value, and in the standby mode, the NMOS transistor of the prior art of FIG. The gate-source voltage V _{GS of} (M3) is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or the third (A) and 3 of US Pat. No. 6,865,119, March 8, 2005 ( B) The results of the graph show that for the NMOS transistor, the sub-critical current when the gate-source voltage is -0.1 volt is about 1% of the sub-critical current when the gate-source voltage is 0 volts, which is caused by GIDL. the third NMOS transistor (M3) of the present invention caused to flow through the effect of the leakage current I ₁ is much smaller than the prior art of FIG. 5 NMOS transistor (M3) are; Furthermore, the third NMOS transistor (M3) of the drain source voltage V _DS of the present invention, the threshold voltage of the fourth NMOS deduct transistor (M21) for the power supply voltage V _DD In the standby mode, the 汲 source voltage V _DS of the NMOS transistor M3 of the conventional 5th FIG. 8T static random access memory is equal to the power supply voltage V _DD , and the energy barrier is reduced according to the drain (Drain- Induced Barrier Lowering (DIBL) effect, the leakage current I ₁ flowing through the third NMOS transistor (M3) of the present invention caused by the DIBL effect is also smaller than that of the prior art NMOS transistor (M3) of FIG. 5; The leakage current I ₁ flowing through the third NMOS transistor (M3) of the present invention is much smaller than that of the prior art NMOS transistor (M3) of FIG.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P1), the source of the first PMOS transistor (P1) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P1) is maintained at the threshold voltage level of the fourth NMOS transistor (M21), so the source drain voltage V _SD of the first PMOS transistor (P1) of the present invention is the power source. The supply voltage (V _DD ) deducts the threshold voltage level of the fourth NMOS transistor (M21), and the source drain voltage V _SD of the PMOS transistor (P1) of the prior art of FIG. 5 is equal to the standby mode. The power supply voltage (V _DD ) is based on the DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P1) is smaller than that of the prior art PMOS transistor (P1) of FIG. 5; The leakage current I3 of the second NMOS transistor (M2) is maintained at the threshold voltage of the fourth NMOS transistor (M21) due to the voltage level of the second low voltage node (VL2) in the standby mode, and the voltage of the node A level is also maintained at the threshold voltage level of the fourth NMOS transistor (M21), the line and the voltage level of the node B is equal to the power supply voltage (V _DD) and the Two NMOS transistors (M2) of the substrate is a ground voltage, and therefore the present invention the second NMOS transistor (M2) is the base-source voltage V _BS is negative, the source and drain of the second NMOS transistor (M2) of The pole voltage V _{DS is} the power supply voltage (V _DD ) deducting the threshold voltage level of the fourth NMOS transistor (M21), and the base source of the NMOS transistor (M2) of the prior art of FIG. 5 in the standby mode. The pole voltage V _BS is equal to 0, and the 汲 source voltage V _DS of the NMOS transistor (M2) is equal to the power supply voltage (V _DD ), according to the body effect and the DIBL effect, the second flowing through the present invention The leakage current I ₃ of the NMOS transistor (M2) is much smaller than that of the prior art NMOS transistor (M2) of FIG.

Finally, regarding the leakage current I ₄ flowing through the NMOS transistor M4, since the double-turn SRAM of the present invention is different from the conventional 8T dual-static static random access memory, and the double-turn SRAM standby mode of the present invention The read bit line RBL can be set to the ground voltage, and the conventional 8T double-click static random access memory is configured to prevent the voltage level of the node B from falling, and the read bit line RBL in the standby mode is set as the power supply. The voltage V _DD , therefore, does not compare the leakage current I ₄ flowing through the NMOS transistor M4. Based on the above analysis, the double-turn SRAM proposed by the present invention can effectively reduce leakage current in the standby mode.

(III) Read mode (Read mode)

The two stored data states of the double-sided SRAM cell indicate how the double-slice SRAM of Figure 6 completes the read operation.

(A) Node A stores logic 0

Before the read operation occurs (the read word line RWL is the ground voltage), the second NMOS transistor (M2) is turned off (OFF), and the second PMOS transistor (P2) is turned on (ON). , Node B is High (power supply voltage V _DD ). When the read operation starts, the read word line (RWL) is turned from Low (ground voltage quasi) to High (power supply voltage V _DD ), and when the read word line (RWL) voltage is greater than the When the threshold voltage of the first read transistor (M4) is read, the first read transistor (M4) is turned from off (OFF) to on (ON), at which time the node B is High (power supply voltage V) _DD ), the second read transistor (M5) is turned on (ON), and therefore, the read bit line (RBL), the first read transistor (M4), and the second read A current path is formed between the access transistor (M5) and the ground, and the current path reduces the voltage level of the read bit line (RBL), thereby sensing that node A stores logic 0. Data and complete the logic 0 read action.

(2) Node A stores logic 1

Before the reading operation occurs (the read word line RWL is a ground voltage), the second NMOS transistor (M2) is turned "ON", and the second PMOS transistor (P2) is turned "OFF". Node B is Low (ground voltage). When the read operation starts, the read word line RWL is turned from Low (ground voltage) to High (power supply voltage V _DD ), and when the voltage of the read word line (RWL) is greater than the first When the threshold voltage of the transistor (M4) is read, the first read transistor (M4) is turned from off (OFF) to on (ON), and at this time, since the node B is Low (ground voltage), The second read transistor (M5) is off, and therefore, is not in the read bit line (RBL), the first read transistor (M4), and the second read transistor ( A current path is formed between M5) and the ground. As a result, the voltage level of the read bit line (RBL) can be smoothly maintained in the High (power supply voltage V _DD ) state, thereby sensing the node A system storage. Logic 1 data, and complete the logic 1 read action.

As for the non-operation in the write, read and standby modes, since the source voltage of the driving transistor in all memory cells is set to the ground voltage, the working principle is the same as that of the conventional 8T double-埠SRAM cell. Repeatedly.

【Effects of invention】

The double-twist static random access memory proposed by the invention has the following effects:

(1) The problem of avoiding the difficulty of writing logic 1: The double-click static random access memory proposed by the present invention can be effectively activated by increasing the voltage level of the first low voltage node (VL1) during a write operation. It is quite difficult to avoid the existence of writing a logic 1 in a double-slot static random access memory cell with a single bit line;

(2) Low standby current: Since the double-pin static random access memory proposed by the present invention is in the standby mode, the sixth NMOS transistor (M23) in an on state can be used to make the first low voltage The voltage level of the node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the threshold voltage of the fourth NMOS transistor (M21), thus The 5T 單埠SRAM proposed by the present invention also has the effect of low standby current;

(3) Maintaining read stability: The double-twist static random access memory proposed by the present invention uses the source voltages of the driving transistors (M1 and M2) in all memory cells during the read operation. Set to ground voltage, so it can effectively maintain reading stability;

(4) Effectively reducing half-selected cell interference: the double-twist static random access memory proposed by the present invention uses a separate read/write path, and the read path is designed to be the first and second read The access transistors (M4 and M5) are connected in series between the read bit line (RBL) and the ground, and the inverting storage node (B) is connected to the second read transistor (M5) The gate, thus effectively reducing the half-selected cell disturbance, wherein the half selected cell is selected by the read word line (WBL) but not by the read bit line ( RBL) Selected unit cell.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

BL. . . Bit line

A. . . Storage node

B. . . Inverting storage node

I ₁ . . . Leakage current

I ₂ . . . Leakage current

I ₃ . . . Leakage current

I ₄ . . . Leakage current

S. . . Standby mode control signal

. . . Inverting standby mode control signal

VL1. . . First low voltage node

VL2. . . Second low voltage node

M21. . . Fourth NMOS transistor

M22. . . Fifth NMOS transistor

M23. . . Sixth NMOS transistor

M24. . . Seventh NMOS transistor

M25. . . Eighth NMOS transistor

M26. . . Ninth NMOS transistor

M27. . . Tenth NMOS transistor

M28. . . Eleventh NMOS transistor

M4. . . First read transistor

M5. . . Second read transistor

WWL. . . Write word line

. . . Inverted write word line

RBL. . . Read bit line

RWL. . . Read word line

1. . . SRAM cell

2. . . Control circuit

BL ₁ ^... BL _m . . . Bit line

WL ₁ ^... WL _n . . . Word line

BLB. . . Complementary bit line

MB ₁ ^... MB _k . . . Memory block

BLB ₁ ^... BLB _m . . . Complementary bit line

V _DD . . . Power supply voltage

Figure 1a shows a conventional static random access memory, and Fig. 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell;

Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;

Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;

Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;

Figure 5 is a schematic diagram showing a circuit of a conventional double-chip static random access memory cell;

Figure 6 is a circuit diagram showing a preferred embodiment of the present invention;

Fig. 7 is a timing chart showing the write operation of the preferred embodiment of the present invention in Fig. 6.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

WBL. . . Write bit line

A. . . Storage node

B. . . Inverting storage node

I ₁ , I ₂ . . . Leakage current

I ₃ , I ₄ . . . Leakage current

S. . . Standby mode control signal

. . . Inverting standby mode control signal

VL1. . . First low voltage node

VL2. . . Second low voltage node

M21. . . Fourth NMOS transistor

M22. . . Fifth NMOS transistor

M23. . . Sixth NMOS transistor

M24. . . Seventh NMOS transistor

M25. . . Eighth NMOS transistor

M26. . . Ninth NMOS transistor

M27. . . Tenth NMOS transistor

M28. . . Eleventh NMOS transistor

M4. . . First read transistor

M5. . . Second read transistor

WWL. . . Write word line

. . . Inverted write word line

RBL. . . Read bit line

RWL. . . Read word line

1. . . SRAM cell

2. . . Control circuit

V _DD . . . Power supply voltage

Claims (5)

A double-click static random access memory, comprising: a memory array, the memory array is composed of a plurality of memory blocks, each memory block further comprising a plurality of memory cells (1) And a plurality of control circuits (2), each memory block is provided with a control circuit (2); wherein each memory cell (1) further comprises: a first inverter, which is first a PMOS transistor (P1) is formed by a first NMOS transistor (M1) connected between a power supply voltage (VDD) and a first low voltage node (VL1); The second inverter is composed of a second PMOS transistor (P2) and a second NMOS transistor (M2) connected to the power supply voltage (VDD) and a second low Between the voltage nodes (VL2); a storage node (A) formed by the output of the first inverter; and an inverting storage node (B) connected by the output of the second inverter Forming a third NM positive OS transistor (M3) connected between the storage node (A) and a corresponding one of the write bit lines (WBL), and the gate is connected to the corresponding one of the writes a first read transistor (M4), the source, the gate and the drain of the first read transistor (M4) are respectively connected to a second read transistor a drain of (M5), a read word line (RWL) and a read bit line (RBL); and the second read transistor (M5), the second read transistor a source, a gate and a drain of (M5) are respectively connected to a ground voltage, an output of the second inverter (node B) and a source of the first read transistor (M4); wherein The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output end of the first inverter (ie, the storage node A) is connected to the input end of the second inverter, and the The output of the second inverter (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (M21) The source of the fourth NMOS transistor (M21) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); a fifth NMOS transistor (M22), the source of the fifth NMOS transistor (M22) The gate and the drain are respectively connected to the ground voltage and an inverted standby mode control signal ( And a second low voltage node (VL2); a sixth NMOS transistor (M23), the source, the gate and the drain of the sixth NMOS transistor (M23) are respectively connected to the second low voltage node (VL2), a standby mode control signal (S) and the first low voltage node (VL1); a seventh NMOS transistor (M24), the source of the seventh NMOS transistor (M24) is connected to the ground voltage The drain is connected to the first low voltage node (VL1), and the gate is connected to the drain of an eighth NMOS transistor (M25), the drain of a ninth NMOS transistor (M26), and a tenth NMOS. a source of the transistor (M27); the eighth NMOS transistor (M25), the source, the gate and the drain of the eighth NMOS transistor (M25) are respectively connected to the ground voltage, the word for writing a gate of the first line (WWL) and the seventh NMOS transistor (M24); the ninth NMOS transistor (M26), the source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to The ground voltage, the standby mode control signal (S) and the gate of the seventh NMOS transistor (M24); the tenth NMOS transistor (M27), the source and the gate of the tenth NMOS transistor (M27) Connected to the seventh NMOS battery separately from the drain Brake body (M24) of the pole, the write word line an inverter ( And a drain of an eleventh NMOS transistor (M28); and an eleventh NMOS transistor (M28), the source, the gate and the drain of the eleventh NMOS transistor (M28) are respectively connected To the drain of the tenth NMOS transistor (M27), the inverted standby mode control signal ( ) with the power supply voltage (V _DD ). The double-click static random access memory according to claim 1, wherein the inverted standby mode control signal ( ) is obtained by the standby mode control signal (S) via an inverter. The double-click static random access memory according to claim 1, wherein the inverted write word line ( ) is obtained by the write word line (WWL) via an inverter. The double-click static random access memory according to claim 1, wherein the memory block is a column of memory cells. The double-click static random access memory according to claim 1, wherein the memory block is a row of memory cells.