TWI427931B - Full digital fast lock pulse width lock loop - Google Patents

Description

Full digital fast lock pulse width lock loop

The present invention relates to a pulse width lock loop, and more particularly to a full digital fast lock pulse width lock loop for low power system wafer application designs operating in a wide frequency domain (500 MHz - 50 MHz).

As shown in FIG. 1A and FIG. 1B, the conventional technique uses a clock input signal clkin to generate a pulse signal pulse width via a time difference between the two ends of the path. Further, the digital control delay line circuit 1 (Digital Control Delay Line, DCDL) is passed through the narrow pulse wave generating circuit 2 (Narrow Pulse, NP) to generate a delay time difference DT through the signals of the path N1 and the path N2, and the time difference is utilized. After the RS flip flop, the pulse width is clipped by the S and R signals. Here, the digitally controlled delay line circuit 1 can be used to generate different delay times from different input digit codes, and the pulse width of the output clock signal clkout is changed. Therefore, how to design the digitally controlled delay line circuit 1 to achieve the circuit delay becomes one of the design priorities of the double-ended pulse signal control adjustment architecture.

Referring to FIG. 2, it is a multiplexer selection delay circuit, which is mainly used for controlling the delay time of the delay signal, and includes two delay units 4 and two multiplexers 5, which are digital code Control the C1 and C2 control multiplexers to select the delay line path through which the clock input signal clkin passes. This design method is more intuitive, and can be directly controlled by binary digit code, and the delay can be selected by using multiple sets of the multiplexer in series. The circuit achieves a long time delay effect, but if a longer delay time is required, more delay units 4 are still needed, which increases the area of the design circuit.

The main purpose of the present invention is to solve the problem that the pulse signal generator must increase the area of the delay unit when generating low frequency signals, resulting in an excessive circuit design area.

In order to achieve the above object, the present invention provides an all-digital fast-lock pulse width locking loop, which is applied to a pulse width generating circuit for receiving a clock input signal and converting it into a set broadband clock output signal. The full digital fast lock pulse width lock loop includes: a cyclic delay system and a pulse generator that receives an output signal of the cyclic delay system.

The clock input signal is input to the cyclic delay system and the pulse wave generator, and the cyclic delay system delays sending the clock input signal to generate a time difference from the clock input signal directly input to the pulse wave generator. The pulse wave generator generates the broadband clock output signal by the time difference trigger.

The cyclic delay system has a continuous triggering delay module (Retrigger Delay Module), two pre-multiplexers and a post-multiplexer respectively connected to the continuous triggering delay module, and one for switching a control module of the front multiplexer and the rear multiplexer, the front multiplexer and the rear multiplexer each have a first connection end, a second connection end, and a switch connection end. The switching connection end of the pre-multiplexer and the switching connection end of the rear multiplexer are respectively connected to two ends of the continuous trigger type delay module, and the second connection end and the rear side of the pre-multiplexer The second connection ends of the multiplexer are connected to each other, and the first connection end of the pre-multiplexer and the first connection end of the rear multiplexer are respectively an input end and an output end of the cyclic delay system, The control module is connected to the pre-multiplexer and the rear multiplexer for controlling the pre-multiplexer and the post-multiplexer.

As can be seen from the above description, the present invention utilizes the cyclic delay system to repeatedly use the continuous triggering delay module located in the cyclic delay system, thereby eliminating the need for a large number of signal delay circuits, thereby greatly saving circuit design area and increasing circuit design. Efficiency and reduce the amount of power consumed by the circuit.

The detailed description and technical contents of the present invention will now be described as follows:

3 and FIG. 4, FIG. 3 is a schematic diagram of a circuit architecture of a preferred embodiment of the present invention, and FIG. 4 is a schematic structural diagram of a preferred embodiment of the present invention. As shown in the figure: the present invention is a full The digital fast lock pulse width locking loop is applied to the pulse width generating circuit for receiving a clock input signal CKin and converting it into a set broadband clock output signal CKout, the full digital fast lock pulse The wave width locking circuit includes: a cyclic delay system 10 and a pulse wave generator 20 that receives the output signal of the cyclic delay system 10, which in this embodiment is an RS flip-flop, the clock The input signal CKin is input to the cyclic delay system 10 and the pulse wave generator 20, wherein a narrow pulse wave generating circuit 40 receives the clock input signal CKin and generates a narrow pulse signal output to the pulse wave generator 20 The cyclic delay system 10 delays the clock input signal CKin and generates a time difference from the narrow pulse signal directly input to the pulse generator 20, and the pulse generator 20 is triggered by the time difference. Clock output signal CKout at birth the broadband.

In addition, the pulse generator 20 is further connected to an over-cycle detecting unit 30, which is mainly used to prevent the pulse width of the wide-band clock output signal CKout from exceeding the period of the clock input signal CKin, resulting in an output. The clock frequency is different from the input frequency. Therefore, using this circuit to output the Over signal reduces the control code until the output pulse width is smaller than the output clock frequency.

The cyclic delay system 10 has a continuous triggering delay module 11 , two pre-multiplexer 12 and a post-multiplexer 13 respectively connected to the continuous triggering delay module 11 , and one for switching the front The control module 14 of the multiplexer 12 and the rear multiplexer 13 has a first connection end 121, 131 and a second connection end. 122, 132 and a switch connection end 123, 133, the switch connection end 123 of the pre-multiplexer 12 and the switch connection end 133 of the rear multiplexer 13 and the two ends of the continuous trigger type delay module 11 respectively The second connection end 122 of the pre-multiplexer 12 and the second connection end 132 of the rear multiplexer 13 are connected to each other. The first connection end 121 of the pre-multiplexer 12 and the rear end are connected to each other. The first connection end 131 of the multiplexer 13 is an input end and an output end of the cyclic delay system 10, and the control module 14 is connected to the pre-multiplexer 12 and the post-multiplexer 13 for use. The first connection ends 121 and 131 and the second connection ends 122 and 132 that switch the pre-multiplexer 12 and the post-multiplexer 13 are controlled in this embodiment. , The control module 14 includes a shift register 141, a RS flip-flop 142 and multiplexer 143 a temporary.

Please refer to FIG. 5 , and FIG. 5 is a schematic diagram of a rough delay adjustment block circuit according to a preferred embodiment of the present invention. The continuous trigger delay module 11 has a coarse delay adjustment block 15 for adjusting the delay time (Coarse). Delay Block) and a Fine Delay Block 16 having a complex delay unit 151A, 151B, 151C and a plurality of delay multiplexings connected across the delay units 151A, 151B, 151C The 152, 153, the plurality of delay multiplexers 152, 153 have a first connection end 152b, 153b, a second connection end 152c, 153c and a switch connection end 152a, 153a, two delay multiplexers 152, 153 The first connection ends 152b, 153b are respectively connected to the two ends of the delay units 151A, 151B, 151C, and the second connection ends 152c, 153c of the two delay multiplexers 152, 153 are connected to each other to form a multiplexer selection. a delay circuit in which the delay multiplexer 152 located before the delay units 151A, 151B, 151C is mainly used to prevent simultaneous transmission of two signals, causing delays at the back end of the delay units 151A, 151B, 151C. The worker 153 generates a repeated triggering malfunction when switching the control signal, and the plurality of delay units 151A, 151B, and 151C have different delay times. In the embodiment of the present invention, the three different delay times are utilized. The delay units 151A, 151B, and 151C are delayed in time by one delay unit, two delay units, and four delay units, respectively, applied to different time delay requirements, and can be utilized at both ends of the delay units 151A, 151B, and 151C. The delay multiplexers 152, 153 select to pass the delay of the first connection terminals 152b, 153b via the delay units 151A, 151B, 151C or directly pass the second connection terminals 152c, 153c without time delay. In the fine tuning part, the PMOS and NMOS gate-level capacitors plus an NMOS control micro-adjust the load size, thereby fine-tuning the delay time.

In summary, since the present invention utilizes the cyclic delay system 10 to repeatedly use the continuous trigger delay module 11 located in the cyclic delay system 10, a large number of signal delay circuits are not required, and the area of the circuit design can be greatly saved. The efficiency of the circuit design is increased, and the power consumed by the circuit is reduced. Moreover, the clock period of the output is prevented from being different from the input frequency by the excessive period detecting unit 30. Further, by being disposed in the delay units 151A, 151B, The two delay multiplexers 152 and 153 before and after the 151C switch the selection of the required delay time unit amount, and avoid the occurrence of repeated triggering malfunctions. Therefore, the present invention is highly progressive and conforms to the requirements of the applied for invention patent, and is applied according to law. The Prayer Council has granted patents as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

Conventional technology

1‧‧‧Digital Control Delay Line Circuit

2‧‧‧Narrow pulse generation circuit

3‧‧‧RS forward and reverse

N1, N2‧‧‧ path

DT‧‧‧delay time difference

Clk‧‧‧ clock input signal

Clkout‧‧‧ output clock signal

4‧‧‧Delay unit

5‧‧‧Multiplexer

C1, C2‧‧‧ digital code control

this invention

10‧‧‧Circular delay system

11‧‧‧Continuous Trigger Delay Module

12‧‧‧Pre-multiplexer

121‧‧‧First connection

122‧‧‧second connection

123‧‧‧Switching the connection

13‧‧‧After multiplexer

131‧‧‧First connection

132‧‧‧second connection

133‧‧‧Switching the connection

14‧‧‧Control Module

141‧‧‧Shift register

142‧‧‧RS forward and reverse

143‧‧‧Scratch multiplexer

15‧‧‧ coarse delay adjustment block

151A, 151B, 151C‧‧‧ delay unit

152, 153‧‧‧Delay multiplexer

152a, 153a‧‧‧Switching the connection

152b, 153b‧‧‧ first connection

152c, 153c‧‧‧ second connection

16‧‧‧fine delay adjustment block

20‧‧‧ Pulse generator

CKin‧‧‧ clock input signal

CKout‧‧‧ clock output signal

30‧‧‧Oversized period detection unit

40‧‧‧Narrow pulse generation circuit

FIG. 1A is a schematic diagram of a double-ended pulse wave signal generator architecture of the prior art.

FIG. 1B is a schematic diagram of signal timing of the prior art.

2 is a schematic diagram of a multiplexer selection delay circuit architecture of the prior art.

3 is a schematic diagram of a circuit architecture of a preferred embodiment of the present invention.

4 is a schematic diagram of a detailed structure of a preferred embodiment of the present invention.

FIG. 5 is a schematic diagram of a coarse delay adjustment block circuit in accordance with a preferred embodiment of the present invention.

10‧‧‧Circular delay system

11‧‧‧Continuous Trigger Delay Module

12‧‧‧Pre-multiplexer

121‧‧‧First connection

122‧‧‧second connection

123‧‧‧Switching the connection

13‧‧‧After multiplexer

131‧‧‧First connection

132‧‧‧second connection

133‧‧‧Switching the connection

14‧‧‧Control Module

20‧‧‧ Pulse generator

CKin‧‧‧ clock input signal

CKout‧‧‧ clock output signal

30‧‧‧Oversized period detection unit

40‧‧‧Narrow pulse generation circuit

Claims (6)

An all-digital fast-locking pulse width locking loop is applied to a pulse width generating circuit for receiving a clock input signal and converting it into a set broadband clock output signal, the full digital fast locking pulse The wave width locking loop includes:
a cyclic delay system and a pulse wave generator for receiving an output signal of the cyclic delay system, wherein the clock input signal is input to the cyclic delay system and a pulse wave generator, and the cyclic delay system will be the clock The input signal is delayed to be sent, and a time difference is generated between the clock input signal directly input to the pulse wave generator, and the pulse wave generator triggers the wide frequency clock output signal by the time difference;

The circulating delay system has a continuous triggering delay module, two pre-multiplexers and a post-multiplexer respectively connected to the continuous triggering delay module, and one for switching the pre-multiplexer And a control module of the rear multiplexer, the front multiplexer and the rear multiplexer each have a first connection end, a second connection end and a switch connection end, the pre-multiplexer The switching connection end of the device and the switching connection end of the rear multiplexer are respectively connected to two ends of the continuous trigger type delay module, and the second connection end of the front multiplexer and the second multiplexer of the front multiplexer The two connection ends are connected to each other, and the first connection end of the pre-multiplexer and the first connection end of the rear multiplexer are respectively an input end and an output end of the cyclic delay system, and the control module and the control module The pre-multiplexer and the post-multiplexer are connected to control the pre-multiplexer and the post-multiplexer.

The full digital quick lock pulse width lock loop according to claim 1, wherein the continuous trigger delay module has a coarse delay adjustment block for adjusting the delay time and a fine delay adjustment block. The full digital fast lock pulse width lock loop as described in claim 2, wherein the coarse delay adjustment block has a complex delay unit and a plurality of delay multiplexers connected at both ends of the delay unit. The full digital quick-lock pulse width lock loop according to claim 1, wherein the pulse generator is further connected with an over-cycle detection unit for preventing a pulse width of the broadband clock output signal. The period of the clock input signal is exceeded. The full digital quick lock pulse width lock loop according to claim 1, wherein the cyclic delay system further has a switch for switching the first connection end and the second connection end of the pre-multiplexer . The full digital quick lock pulse width lock loop as described in claim 5, wherein the switch is an RS flip flop.