TWI426694B - Soft switching power converter - Google Patents

Description

Flexible switching power converter

The present invention relates to a power converter, and more particularly to a flexible switched power converter.

Phase Shift Power Converter is a flexible switching power converter that includes full-bridge phase shift, asymmetrical half bridge and active clamp Active clamp architecture and so on. The advantages of phase-shifting power converters are high efficiency and low electromagnetic interference (EMI). In the recent developments, a number of phase shifting techniques have been proposed, for example: Christopher, P. Henze, Ned Mohan, and John G. Hayes, U.S. Patent No. 4,855,888, filed on August 8, 1989, entitled "Constant Frequency resonant power converter" With zero voltage switching"; Guichao C. Hua and Fred C. Lee, "Soft-switching PWM converters", U.S. Patent No. 5,442,540, filed on August 15, 1995; Yungtaek Jang and Milan M. Jovanovic in 2002 U.S. Patent No. 6,356,462, "Soft-switched full-bridge converters", which is filed on March 12, 2000; U.S. Patent No. 6,069,798, entitled "Asymmetrical power converter and method of operation thereof", filed on May 30, 2000. . In various phase-shifting power converters, the parasitic leakage inductance of the transformer and/or the applied magnetic component is used as a resonant inductor that is switched to generate a circulating current to achieve zero voltage switching ( Zero Voltage Switching, ZVS).

However, these phase shift power converters have the disadvantage of a narrow operating range. Accordingly, it is an object of the present invention to provide a control scheme that extends the operating range of the power converter and increases operating efficiency.

It is an object of the present invention to provide a power converter for expanding its operating range and increasing operational efficiency.

The power converter of the present invention comprises a resonant circuit, a plurality of transistors and a control circuit. The transistors are used to switch the resonant circuit, and the control circuit generates a plurality of switching signals to control the transistors. The pulse widths of the switching signals are modulated to adjust an output voltage of the power converter, and the control circuit detects the power. One of the input voltages of the converter, the frequency of the switching signal changes depending on the input voltage of the power converter or/and the output load of one of the power converters.

In order to provide a better understanding and understanding of the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description, as explained below: please refer to the first figure, A circuit diagram of a power converter in accordance with a preferred embodiment of the invention. As shown, a capacitor 50 and an inductive device (e.g., a transformer 30, its parasitic inductance 35 and load) form a resonant tank (Resonant Tank). The capacitor 50 is coupled between one end of the primary winding of the transformer 30 and the ground. Therefore, the capacitor 50 is coupled to the sensing device. The transistors 10, 20 are coupled to the resonant circuit to switch the resonant circuit. One of the transistors 10 is electrically coupled to an input voltage V _IN , and one source of the transistor 10 is connected to one of the drains of the transistor 20 . The source of the transistor 10 and the drain of the transistor 20 are coupled to the other end of the primary winding of the transformer 30 via a parasitic inductance 35. One source of the transistor 20 is coupled to the ground. The rectifiers 71 and 72 are connected to the secondary winding of the transformer 30 and are connected to the output voltage V _{O of the} power converter via an inductor 73. A capacitor 75 is used to generate the output voltage V _O .

A control circuit 100 generates switching signals S _H and S _L , and switching signals S _H and S _L are coupled to the gates of transistors 10 and 20, respectively, to control transistors 10 and 20. The pulse widths of the switching signals S _H and S _L are modulated according to the feedback signal V _FB to adjust the output voltage V _{O of the} power converter. The feedback signal V _{FB is} generated at a VFB terminal. A feedback circuit includes a Zener diode 80, a resistor 81 and an optocoupler 85 coupled to the output voltage V _O of the power converter to generate a feedback signal V _FB . In addition, one of the VA terminals of the control circuit 100 is coupled to the input voltage V _{IN of the} power converter via the resistors 61 and 62 and detects the input voltage V _IN . The resistor 61 is connected to the input voltage V _IN , and the resistor 61 and the resistor 62 are connected in series with each other. The VA terminal of the control circuit 100 is connected to a connection point of the resistor 61 and the resistor 62. The frequency of the switching signals S _H and S _L changes depending on the change of the input voltage V _IN and the feedback signal V _FB . Therefore, the power converter can be allowed to operate over a wide range of input voltage operating ranges.

The frequency of the switching signals S _H and S _L decreases as the input voltage V _IN decreases. The frequency of the switching signals S _H and S _L also decreases as the feedback signal V _FB increases. The change in the feedback signal V _FB is related to the output load of the power converter. Therefore, the control circuit 100 is configured to detect the output load of the power converter to reduce the frequency of the switching signals S _H and S _L according to the increase of the output load of the power converter. A resistor 53 is coupled to one of the RT terminals of the control circuit 100 to determine the delay time. The delay time is between the switching signals S _H and S _L to reach the flexible switching transistors 10 and 20. Therefore, the control circuit 100 further generates a delay time to achieve flexible switching. The resistor 53 is used as a delay time resistor to determine the delay time of the switching signals S _H and S _L . A resistor 51 is coupled to one of the RF terminals of the control circuit 100 to determine the maximum switching frequency of the switching signals S _H and S _L . The resistor 51 is used as a frequency setting resistor to determine the maximum switching frequency of the switching signals S _H and S _L . Another resistor 52 is coupled to one of the RM terminals of the control circuit 100, which determines the minimum switching frequency of the switching signals S _H and S _L . The resistor 52 is used as a frequency adjustment resistor to determine the minimum switching frequency of the switching signals S _H and S _L .

Referring to the second figure, a circuit diagram of a control circuit in accordance with a preferred embodiment of the present invention. As shown, it includes a feedback input circuit coupled to the output voltage V _O to receive the feedback signal V _FB to generate a level shift signal V _F . The level shift signal V _{F is} related to the feedback signal V _FB . The transistor 110 and the resistors 112, 115 and 116 form a feedback input circuit. One of the gates of the transistor 110 receives a supply voltage V _CC , and one of the gates of the transistor 110 is coupled to the VFB terminal to receive the feedback signal V _FB . The resistor 112 is connected between the drain of the transistor 110 and the gate. The resistor 115 is connected to one of the sources of the transistor 110. The resistor 116 is connected between the resistor 115 and the ground.

An oscillator (OSC) 200 detects the level shift signal V _F and detects the input voltage V _IN via the VA terminal to generate an oscillation signal PLS. Therefore, the oscillator 200 detects the feedback signal V _FB and the input voltage V _IN to generate the oscillation signal PLS. The resistor 51 at the RF terminal and the resistor 52 at the RM terminal are coupled to the oscillator 200 to determine the maximum frequency and the minimum frequency of the oscillation signal PLS. A pulse width modulation circuit (PWM) 300 is coupled to the oscillator 200 to generate a pulse width modulation signal S _W according to the oscillation signal PLS. The pulse width modulation circuit 300 modulates the pulse width of the pulse width modulation signal S _W according to the level shift signal V _F . Therefore, the pulse width of the pulse width modulation signal S _W is modulated with the feedback signal V _FB .

An output circuit (OUT) 500 is coupled to the pulse width modulation circuit 300 and generates switching signals S _H and S _L according to the pulse width signal S _W . In addition, the delay time is between the switching signals S _H and S _L to reach the flexible switching transistors 10 and 20. The resistor 53 at the RT terminal is coupled to the output circuit 500 to determine the value of the delay time. The delay time includes a first delay time and a second delay time. The first delay time is generated after the switching signal S _{H is} turned off and before the switching signal S _{L is} turned on. The second delay time is generated after the switching signal S _{L is} turned off and before the switching signal S _{H is} turned on.

Referring to the third figure, a circuit diagram of an oscillator in accordance with a preferred embodiment of the present invention. As shown, the oscillator 200 includes a frequency modulation circuit (M _IN -F) 210, a frequency generation circuit (FSW) 240, and an oscillating circuit. The frequency modulation circuit 210 is coupled to the VA terminal and receives the level offset signal V _F . The frequency modulation circuit 210 generates a frequency modulation signal V _M according to the feedback signal V _FB and the input voltage V _IN . The frequency generating circuit 240 generates a charging current I _C and a discharging current I _D according to the resistor 51 and the frequency modulation signal V _M . Referring to the first figure, the resistor 51 is coupled to the RF terminal of the control circuit 100. The frequency generating circuit 240 also generates a modulation current I _M to charge the RM terminal and flow through the resistor 52. Referring to the first figure, the resistor 52 is coupled to the RM terminal of the control circuit 100.

The oscillating circuit includes a capacitor 270, switches 271 and 272, comparators 275 and 276, NAND gates 281 and 282, and inverters 283 and 285. The first terminal of one of the switches 271 receives the charging current I _C to charge the capacitor 270. The second end of one of the switches 271 is coupled to a first end of the switch 272 and a first end of the capacitor 270. The second terminal of one of the switches 272 receives the discharge current I _D to discharge the capacitor 270. The second end of one of the capacitors 270 is coupled to the ground. One of the comparators 275 receives the upper threshold value V _{H at the} positive input. One of the negative input of comparator 275 and one of the positive input of comparator 276 is coupled to the first end of capacitor 270, the second end of switch 271, and the first end of switch 272. One negative input of comparator 276 receives a lower limit threshold value V _L, and the upper limit threshold value V _H is higher than the lower limit threshold value V _L.

The first end of one of the opposite gates 281 is coupled to one of the outputs of the comparator 275. The first end of one of the gates 282 is coupled to one of the outputs of the comparator 276. The output end of one of the opposite gates 281 is coupled to the second end of the gate 282. The output end of one of the gates 282 is coupled to the second end of the gate 281. One input of the inverter 283 is coupled to the output of the NAND gate 281 and controls the switch 272. One of the inputs of the inverter 285 is coupled to an output of the inverter 283 and controls the switch 271. An output of one of the inverters 285 generates an oscillation signal PLS. Therefore, the oscillating circuit receives the charging current I _C and the discharging current I _D to generate the oscillation signal PLS.

Please refer to the fourth figure, which is a circuit diagram of a frequency modulation circuit according to a preferred embodiment of the present invention. As shown, the frequency modulation circuit 210 includes a first amplifier 211, a second amplifier 221, a third amplifier 230, and a fourth amplifier 235. The positive input terminal of one of the first amplifiers 211 receives the level shift signal V _F , and the negative input terminal of the first amplifier 211 receives a threshold value V _T1 via a resistor 212. An output of one of the first amplifiers 211 is coupled to a negative input terminal of the first amplifier 211 via a resistor 213. A positive input terminal of the second amplifier 221 is coupled to the VA terminal, and a negative input terminal of the second amplifier 221 is coupled to the output terminal thereof to form a buffer circuit. One end of the current source 220 is coupled to the supply voltage V _CC , and the other end of the current source 220 is coupled to the output of the second amplifier 221 via a resistor 224 . The positive input terminal of one of the third amplifiers 230 is coupled to the output of the first amplifier 211 via a resistor 214. One end of a resistor 215 is coupled to the positive input terminal of the third amplifier 230, and the other end of the resistor 215 is coupled to the ground terminal. The negative input terminal of the third amplifier 230 is coupled to the other end of the current source 220 and coupled to the output terminal via a resistor 225.

One of the positive inputs of the fourth amplifier 235 is coupled to the output of the third amplifier 230. A negative input terminal of the fourth amplifier 235 is coupled to the output end thereof, and an output terminal of the fourth amplifier 235 is coupled to the RM terminal and generates a frequency modulation signal V _M . The modulation current I _{M is} supplied to the output of the fourth amplifier 235 and charges the RM terminal. When the level shift signal V _{F is} higher than the threshold value V _T1 , the frequency modulation signal V _M increases according to the increase of the level shift signal V _F . The frequency modulation circuit 210 detects the input voltage V _IN via the VA terminal. When the voltage at the VA terminal decreases and is lower than a threshold value provided by the current source 220, the frequency modulation signal V _M will increase according to the decrease of the input voltage V _IN .

Referring to FIG. 5, a circuit diagram of a frequency generating circuit in accordance with a preferred embodiment of the present invention. As shown, the frequency generating circuit 240 includes a first voltage current converter, a second voltage current converter, a current source 250, and transistors 244 and 245 forming a first current mirror, and transistors 246 and 247. One of the second current mirrors, the transistors 254 and 255 form a third current mirror, the transistors 254 and 256 form a fourth current mirror, and the transistors 261 and 262 form a fifth current mirror, the transistor 261 and 263 forms a sixth current mirror and transistors 264 and 265 form a seventh current mirror. The frequency generating circuit 240 generates a charging current I _C and a discharging current I _D according to the resistor 51 coupled to the RF terminal (as shown in the first figure). The charging current I _C and the discharging current I _D decrease in accordance with an increase in the frequency modulation signal V _M .

The first voltage current converter includes an operational amplifier 241, a transistor 243, and a resistor 242. One of the operational amplifiers 241 receives a frequency modulation signal V _M , and an output of the operational amplifier 241 is coupled to one of the gates of the transistor 243 . One of the negative input terminals of the operational amplifier 241 is coupled to one of the sources of the transistor 243. The resistor 242 is connected between the source of the transistor 243 and the ground. One of the transistors 243 is electrically coupled to the first current mirror. The sources of the transistors 244 and 245 of the first current mirror are coupled to the supply voltage V _CC . The gates of transistors 244 and 245 and the drains of transistors 244 and 243 are interconnected. One of the transistors 245 is coupled to the second current mirror. The sources of the transistors 246 and 247 of the second current mirror are coupled to the ground. The gates of transistors 246 and 247 and the drains of transistors 246 and 245 are interconnected. One of the transistors 247 is electrically coupled to the fifth current mirror.

The second voltage current converter includes an operational amplifier 251, a transistor 253, and a resistor 252. One of the operational amplifiers 251 has a positive input coupled to the current source 250. The current source 250 is further coupled to the supply voltage V _CC . The positive input terminal of the operational amplifier 251 is further connected to the resistor 51 coupled to the RF terminal (as shown in the first figure). One output of the operational amplifier 251 is coupled to one of the gates of the transistor 253, and one of the negative input terminals of the operational amplifier 251 is coupled to a source of the transistor 253. The resistor 252 is connected between the source of the transistor 253 and the ground. One of the transistors 253 is electrically coupled to the third current mirror. The sources of the transistors 254 and 255 of the third current mirror are coupled to the supply voltage V _CC . The gates of transistors 254 and 255 are connected to the drains of transistors 254 and 253. One of the transistors 255 is coupled to the fifth current mirror.

One source of the transistor 256 of the fourth current mirror is coupled to the supply voltage V _CC . One of the gates of the transistor 256 is coupled to the gate of the transistor 254. One of the gates of the transistor 256 generates a modulation current I _M . The sources of the transistors 261 and 262 of the fifth current mirror are coupled to the ground. The gates of the transistors 261 and 262 and the drains of the transistors 261, 247 and 255 are connected to each other. One of the transistors 262 is electrically coupled to the seventh current mirror. One source of the sixth crystal of the sixth current mirror is coupled to the ground. One of the gates of the transistor 263 is coupled to the gate of the transistor 261. One of the gates of the transistor 263 generates a discharge current I _D . The sources of the transistors 264 and 265 of the seventh current mirror are coupled to the supply voltage V _CC . The gates of transistors 264 and 265 and the drains of transistors 264 and 262 are interconnected. One of the gates of the transistor 265 generates a charging current I _C .

Please refer to a sixth diagram, which is a circuit diagram of a pulse width modulation circuit according to a preferred embodiment of the present invention. As shown, the oscillation signal PLS is coupled to a T-type flip-flop 310 and a D-type flip-flop 315 to trigger the T-type flip-flop 310 and the D-type flip-flop 315. One of the input terminals D of the D-type flip-flop 315 receives the supply voltage V _CC . One output terminal Q of the T-type flip-flop 310 and one output terminal Q of the D-type flip-flop 315 are connected to two input terminals of a gate 350 to generate a pulse width modulation signal S _W . The T-type flip-flop 310 provides a 50% maximum duty cycle (Duty Cycle) to the pulse width modulation signal S _W . The output terminal Q of the T-type flip-flop 310 is further connected to an input terminal of an inverter 331. The inverter 331, a transistor 332, a current source 335 and a capacitor 340 form a ramp generator for generating a ramp signal according to the enable of the output of the T-type flip-flop 310.

One end of the current source 335 is coupled to the supply voltage V _CC , and the other end of the current source 335 is coupled to one of the first ends of the capacitor 340 . The second end of one of the capacitors 340 is coupled to the ground. One of the transistors 332 is coupled to the first end of the capacitor 340. One source of the transistor 332 is coupled to the ground, and one of the gates of the transistor 332 is coupled to an output of the inverter 331. Current source 335 charges capacitor 340 when the output of T-type flip-flop 310 is enabled. When the output of the T-type flip-flop 310 is disabled, the capacitor 340 is discharged through the transistor 332 and the ground. Therefore, the capacitor 340 generates a ramp signal.

The ramp signal is coupled to a positive input terminal of a comparator 320. One of the negative inputs of the comparator 320 receives the level offset signal V _F , and the comparator 320 compares the ramp signal with the level offset signal V _F to generate a The pulse width modulation reset signal, the pulse width modulation reset signal is coupled to one of the D-type flip-flops 315 via a reverse gate 325 to reset the input terminal R to reset the D-type flip-flop 315 and reach Modulate the pulse width of the pulse width modulation signal S _W . A blanking circuit (BLK) 400 is coupled to the pulse width modulation signal S _W and generates a blanking signal S _{B according} to the enable of the pulse width modulation signal S _W . The blanking signal S _{B is} connected to the anti-gate 325 to disable the reset of the D-type flip-flop 315 to ensure a minimum on-time of the pulse width modulation signal S _W .

Please refer to the seventh figure, which is a circuit diagram of a blanking circuit in accordance with a preferred embodiment of the present invention. As shown, the blanking circuit 400 includes a charging current 430, an inverter 410, a transistor 420, a capacitor 450, and a gate 460. In a preferred embodiment of the invention, the transistor 420 can be an N-type transistor. A gate terminal of the N-type transistor 420 receives the pulse width modulation signal S _W via the inverter 410. The first input of one of the gates 460 receives the pulse width modulation signal S _W . One source of the N-type transistor 420 is coupled to the ground. The second input end of the gate 460 is coupled to one of the drain of the N-type transistor 420 and one end of the capacitor 450. The drain of the N-type transistor 420 is coupled to the supply voltage V _CC via a charging current 430. The other end of the capacitor 450 is coupled to the ground. The output of one of the gates 460 produces a blanking signal S _B . Therefore, the blanking circuit 400 receives the pulse width modulation signal S _W and generates the blanking signal S _B according to the pulse width modulation signal S _W . The capacitance of capacitor 450 and the current of charging current 430 determine the blanking time.

Please refer to the eighth drawing, which is a circuit diagram of an output circuit of a preferred embodiment of the present invention. As shown, resistor 53 (shown in Figure 1) is coupled to a current source 510 to generate a voltage at the RT terminal. The current source 510 is coupled to the supply voltage V _CC and coupled to the resistor 53 via the RT terminal. The voltage at the RT terminal is coupled to a positive input of an operational amplifier 520. The operational amplifier 520, a resistor 525 and a transistor 550 form a voltage current converter to generate a current and are coupled to the transistors 551, 552 and 553. The positive input terminal of the operational amplifier 520 receives the voltage of the RT terminal, and the output terminal of one of the operational amplifiers 520 is coupled to one of the gates of the transistor 550. One of the negative input terminals of the operational amplifier 520 is coupled to one of the sources of the transistor 550. A resistor 525 is coupled between the source of the transistor 550 and the ground. One of the gates of the transistor 550 generates a current and is coupled to the transistors 551, 552, and 553.

The transistors 551, 552 and 553 form two current mirrors to generate currents I _T1 and I _T2 , and currents I _T1 and I _T2 are coupled to delay time circuits 700 and 701, respectively. The sources of the transistors 551, 552 and 553 are coupled to the supply voltage V _CC . The gates of the transistors 551, 552 and 553 are connected to the drains of the transistors 551, 550. One of the gates of the transistor 553 generates a current I _T1 and is coupled to one of the inputs of the delay time circuit 700. One of the gates of transistor 552 generates current I _T2 and is coupled to one of the inputs of delay time circuit 701. Delay time circuits 700 and 701 generate delay times for switching signals S _H and S _L . The pulse width modulation signal S _{W is} connected to one of the input terminals of the delay time circuit 700 and a gate 650. One of the delay time circuits 700 is coupled to the other input of the gate 650. An output of one of the gates 650 is coupled to a buffer 670 to generate a switching signal S _H . The switching signal S _H is generated based on the pulse width modulation signal S _W and is generated after the delay time generated by the delay time circuit 700.

In addition, the pulse width modulation signal S _W is connected to the input terminal of one of the delay time circuit 701 and a gate 660 via an inverter 610. The output of the delay time circuit 701 is connected to the other input of the gate 660. An output of one of the gates 660 is coupled to a buffer 680 to generate a switching signal S _L . The switching signal S _L is generated after the delay time generated by the delay time circuit 701 according to the disable of the pulse width modulation signal S _W .

Please refer to the ninth drawing, which is a circuit diagram of delay time circuits 700 and 701 in accordance with a preferred embodiment of the present invention. As shown, the delay time circuit includes a charging current I _T , an inverter 715 , a transistor 720 , a capacitor 750 , and a gate 790 . The charging current I _T refers to the currents I _T1 and I _T2 shown in the eighth figure. In a preferred embodiment of the invention, the transistor 720 can be an N-type transistor. One of the gates of the N-type transistor 720 receives an input signal IP via the inverter 715. For the input of the delay time circuit 700 shown in the eighth figure, the input signal IP is the pulse width modulation signal S _W . For the input end of the delay time circuit 701 shown in the eighth figure, the input signal IP is also the pulse width modulation signal S _W , but the pulse width modulation signal S _W must be inverted by the inverter 610. The first input of one of the gates 790 receives the input signal IP. One source of the N-type transistor 720 is coupled to the ground. The second input end of the gate 790 is coupled to one of the drain of the N-type transistor 720 and one end of the capacitor 750. The drain of the N-type transistor 720 is coupled to the charging current I _T . The other end of the capacitor 750 is coupled to the ground. An output signal OP is generated at one of the outputs of the gate 790. Therefore, the delay time circuit receives the input signal IP and generates an output signal OP (delay time) according to the enable of the input signal IP. The capacitance of the capacitor 750 and the current of the charging current I _T determine the delay time.

Please refer to the tenth figure, which is a conversion function graph showing the change of the gain corresponding to the switching frequency. The voltage V _SW in the figure is the voltage across the transistor 20 (see the first figure), which is the input voltage of the resonant circuit. n is one of the turn ratios of the transformer 30 (see the first figure). The frequency f _P is the maximum switching frequency of the switching signals S _H and S _L . The minimum pulse width of the switching signal S _H must provide sufficient energy and circulating current to achieve flexible switching of the transistors 10 and 20. The frequency f _R is one of the resonant frequencies of the resonant circuit. The minimum switching frequency of the switching signals S _H and S _L should be higher than and close to the resonant frequency f _R to achieve flexible switching and maximum power conversion. The tenth graph shows that as the input voltage decreases and/or the load increases, the switching frequency decreases from the frequency f _P to the frequency f _R , thus expanding the operating range and improving efficiency.

Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the requirements of patent applications for patent law in China. It is undoubtedly to file an invention patent application according to law, and the Prayer Council will grant patents as soon as possible.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10. . . Transistor

100. . . Control circuit

110. . . Transistor

112. . . resistance

115. . . resistance

116. . . resistance

20. . . Transistor

200. . . Oscillator

210. . . Frequency modulation circuit

220. . . Battery

211. . . First amplifier

250. . . Battery

251. . . Operational Amplifier

254. . . Transistor

255. . . Transistor

256. . . Transistor

261. . . Transistor

262. . . Transistor

263. . . Transistor

264. . . Transistor

265. . . Transistor

270. . . capacitance

271. . . switch

275. . . Comparators

276. . . Comparators

281. . . Reverse gate

282. . . Reverse gate

283. . . inverter

285. . . inverter

30. . . transformer

300. . . Pulse width modulation circuit

310. . . T-type flip-flop

315. . . D-type flip-flop

320. . . Comparators

331. . . inverter

332. . . Transistor

335. . . Battery

680. . . buffer

700. . . Delay time circuit

701. . . Delay time circuit

71. . . Rectifier

715. . . inverter

72. . . Rectifier

720. . . Transistor

73. . . inductance

75. . . capacitance

750. . . capacitance

790. . . Gate

80. . . Zener diode

81. . . resistance

85. . . Optocoupler

I _C . . . recharging current

I _D . . . Discharge current

I _M . . . Modulated current

I _T . . . recharging current

221. . . Second amplifier

230. . . Third amplifier

235. . . Fourth amplifier

240. . . Frequency generation circuit

241. . . Operational Amplifier

242. . . resistance

243. . . Transistor

244. . . Transistor

245. . . Transistor

246. . . Transistor

247. . . Transistor

340. . . capacitance

35. . . Parasitic inductance

400. . . Blanking circuit

410. . . inverter

420. . . Transistor

430. . . recharging current

450. . . capacitance

460. . . Gate

50. . . capacitance

500. . . Output circuit

51. . . resistance

510. . . Battery

52. . . resistance

520. . . Operational Amplifier

525. . . resistance

53. . . resistance

550. . . Transistor

551. . . Transistor

552. . . Transistor

553. . . Transistor

61. . . resistance

610. . . inverter

62. . . resistance

650. . . Gate

660. . . Gate

670. . . buffer

I _T1 . . . Current

I _T2 . . . Current

IP. . . Input signal

OP. . . Output signal

S _B . . . Blanking signal

S _H . . . Switching signal

S _L . . . Switching signal

S _W . . . Frequency modulation signal

V _CC . . . Supply voltage

V _F . . . Level shift signal

V _FB . . . Feedback signal

V _H . . . Upper threshold

V _IN . . . Input voltage

V _L . . . Lower threshold

V _M . . . Frequency modulation signal

V _O . . . The output voltage

I _M ‧‧‧ modulated current

I _T ‧‧‧Charging current

V _SW ‧‧‧ voltage

PLS‧‧‧ oscillation signal

The first figure is a circuit diagram of a power converter according to a preferred embodiment of the present invention;

2 is a circuit diagram of a control circuit of a preferred embodiment of the present invention;

Figure 3 is a circuit diagram of an oscillator of a preferred embodiment of the present invention;

Figure 4 is a circuit diagram of a frequency modulation circuit in accordance with a preferred embodiment of the present invention;

Figure 5 is a circuit diagram of a frequency generating circuit in accordance with a preferred embodiment of the present invention;

Figure 6 is a circuit diagram of a pulse width modulation circuit of a preferred embodiment of the present invention;

Figure 7 is a circuit diagram of a blanking circuit in accordance with a preferred embodiment of the present invention;

Figure 8 is a circuit diagram of an output circuit of a preferred embodiment of the present invention;

Figure 9 is a circuit diagram of a delay time circuit in accordance with a preferred embodiment of the present invention;

The tenth figure shows a conversion function graph showing the change of the gain corresponding to the switching frequency.

10. . . Transistor

100. . . Control circuit

20. . . Transistor

30. . . transformer

35. . . Parasitic inductance

50. . . capacitance

51. . . resistance

52. . . resistance

53. . . resistance

61. . . resistance

62. . . resistance

71. . . Rectifier

72. . . Rectifier

73. . . inductance

75. . . capacitance

80. . . Zener diode

81. . . resistance

85. . . Optocoupler

V _IN . . . Input voltage

V _FB . . . Feedback signal

V _O . . . The output voltage

S _H . . . Switching signal

S _L . . . Switching signal

Claims (10)

A flexible switching power converter includes: a resonant circuit; a plurality of transistors that switch the resonant circuit; and a control circuit that generates a plurality of switching signals to control the transistors and modulate the pulses of the switching signals a width of the wave to adjust an output voltage of the power converter, the control circuit detecting an input voltage of the power converter and a feedback signal, and changing the change according to the input voltage and the change of the feedback signal Switching the frequency of the signal to allow the power converter to operate over a wide range, the change of the feedback signal being related to a change in the output load of one of the power converters, the frequency of the switching signals being reduced according to the input voltage The increase in the feedback signal is reduced. The flexible switching power converter of claim 1, wherein the resonant circuit further comprises a capacitor and an inductive device coupled to the sensing device. The flexible switching power converter of claim 1, wherein the control circuit further generates a complex delay time between the switching signals to achieve flexible switching of the transistors. The flexible switching power converter of claim 3, further comprising a delay time resistor coupled to the control circuit to determine the delay times of the switching signals. The flexible switching power converter of claim 1, wherein the frequency of the switching signals is reduced according to an increase in the output load of the power converter. The flexible switching power converter of claim 1, further comprising a frequency setting resistor coupled to the control circuit to determine a maximum switching frequency of one of the switching signals. The flexible switching power converter as described in claim 1 of the patent application further includes A frequency modulation resistor coupled to the control circuit to determine a minimum switching frequency of one of the switching signals. The flexible switching power converter of claim 1, wherein the control circuit comprises: an oscillator, detecting the input voltage and the feedback signal to generate an oscillation signal; and a pulse width modulation a pulse width modulation signal according to the oscillation signal, wherein the pulse width modulation circuit modulates a pulse width of the pulse width modulation signal according to the feedback signal; and an output circuit according to the pulse The wave width modulation signal generates the switching signals, and the complex delay time is located between the switching signals to flexibly switch the transistors. The flexible switching power converter of claim 8, wherein the control circuit further comprises: a feedback input circuit coupled to one of the power converters for outputting and receiving the feedback signal to generate a level An offset signal, the oscillator receives the level shift signal to detect the feedback signal to generate the oscillation signal, and the pulse width modulation circuit receives the level offset signal, and according to the feedback signal, Modulate the pulse width of the pulse width modulation signal. The flexible switching power converter of claim 8, wherein the oscillator comprises: a frequency modulation circuit, generating a frequency modulation signal according to the feedback signal and the input voltage; and a frequency generating circuit Generating a charging current and a discharging current according to a frequency setting resistor and the frequency modulation signal, wherein the frequency setting resistor is coupled to the control circuit to determine a maximum switching frequency of one of the switching signals; and an oscillating circuit receiving the charging The current and the discharge current are used to generate the oscillation signal.