TWI420624B - Semiconductor chip package structure - Google Patents
Semiconductor chip package structure Download PDFInfo
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- TWI420624B TWI420624B TW097125237A TW97125237A TWI420624B TW I420624 B TWI420624 B TW I420624B TW 097125237 A TW097125237 A TW 097125237A TW 97125237 A TW97125237 A TW 97125237A TW I420624 B TWI420624 B TW I420624B
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- heat sink
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- package structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本發明是有關於一種晶片封裝結構，且特別是有關於一種四方扁平晶片封裝結構(Quad Flat Package, QFP)。The present invention relates to a chip package structure, and more particularly to a quad flat package (QFP).
半導體工業是近年來發展速度最快之高科技工業之一，隨著電子技術的日新片異，高科技電子產業的相繼問世，使得更人性化、功能更佳的電子產品不斷地推陳出新，並朝向輕、薄、短、小的趨勢設計。The semiconductor industry is one of the fastest growing high-tech industries in recent years. With the new and different electronic technologies, the high-tech electronics industry has emerged, making the more humanized and functional electronic products constantly innovating and facing. Light, thin, short, and small trend design.
目前在半導體製程當中，導線架是經常使用的構裝承載器之一，而應用導線架作為承載器之導線架型封裝結構通常可區分為引腳插入型(Pin Through Hole, PTH)以及表面黏著型(Surface Mount Technology, SMT)等兩大類，其中較常見的例如有雙邊引腳型封裝結構(Dual In-Line Package, DIP)、在晶片上搭載導線架(Lead On Chip Package, LOC)之封裝結構，以及四方扁平晶片封裝結構等。Currently, in the semiconductor manufacturing process, the lead frame is one of the commonly used package carriers, and the lead frame type package using the lead frame as the carrier can be generally divided into a Pin Through Hole (PTH) and a surface adhesion. Two types, such as Surface Mount Technology (SMT), the most common ones are the Dual In-Line Package (DIP) and the Lead On Chip Package (LOC) package. Structure, and quad flat wafer package structure.
圖1繪示為習知之一種四方扁平晶片封裝結構的示意圖。請參考圖1所示，傳統的四方扁平晶片封裝結構100主要包含一導線架110、一晶片120、一散熱片130以及一封裝膠體140。導線架110包含一晶片座(die pad)112以及環繞於晶片座112外圍的多個引腳(lead)114。晶片120配置於晶片座112之上表面，且透過打線接合技術與導線架 110之引腳114電性連接。散熱片130貼附於晶片座112之下表面，且其是由導熱佳的金屬所製成，例如銅、鋁等金屬片。晶片120運作時所產生的熱能即可經由晶片座112及散熱片130而散逸到大氣環境中。封裝膠體(molding compound)140包覆住導線架110、晶片120以及散熱片130，以保護上述元件免於受損及受潮。FIG. 1 is a schematic diagram of a conventional quad flat wafer package structure. Referring to FIG. 1 , the conventional quad flat package structure 100 mainly includes a lead frame 110 , a wafer 120 , a heat sink 130 , and an encapsulant 140 . The leadframe 110 includes a die pad 112 and a plurality of leads 114 surrounding the periphery of the die paddle 112. The wafer 120 is disposed on the upper surface of the wafer holder 112, and is connected to the lead frame by a wire bonding technique Pin 110 of 110 is electrically connected. The heat sink 130 is attached to the lower surface of the wafer holder 112, and is made of a metal having good heat conductivity, such as a metal piece such as copper or aluminum. The thermal energy generated by the operation of the wafer 120 can be dissipated into the atmosphere via the wafer holder 112 and the heat sink 130. A molding compound 140 encloses the lead frame 110, the wafer 120, and the heat sink 130 to protect the components from damage and moisture.
然而，在將散熱片130貼附於晶片座112之下表面的製程中，常會因散熱片130表面之粗糙度太大，而發生散熱片130與晶片座112之間無法緊密接合的問題。更進一步而言，此接合不佳的情形常會造成晶片座112與散熱片130之間存在有多個空腔，而空氣便會存留在這些空腔中。由於空氣的熱膨脹係數較大，因此，常會從晶片座112與散熱片130之間產生斷裂的情形，進而造成可靠度降低等問題。此外，由於空氣的熱傳導係數較低，因此，晶片120運作時所產生的熱能亦無法順利地從晶片座112傳導到散熱片130中，進而影響到整晶片封裝結構100的散熱效果。However, in the process of attaching the heat sink 130 to the lower surface of the wafer holder 112, the roughness of the surface of the heat sink 130 is often too large, and the problem that the heat sink 130 and the wafer holder 112 cannot be tightly joined occurs. Furthermore, this poorly coupled condition often results in the presence of multiple cavities between the wafer holder 112 and the heat sink 130, and air will remain in these cavities. Since the coefficient of thermal expansion of air is large, breakage often occurs between the wafer holder 112 and the heat sink 130, which causes problems such as reduced reliability. In addition, since the heat transfer coefficient of the air is low, the heat generated during the operation of the wafer 120 cannot be smoothly conducted from the wafer holder 112 to the heat sink 130, thereby affecting the heat dissipation effect of the entire chip package structure 100.
本發明的目的就是在提供一種晶片封裝結構，其藉由一形成於散熱片表面之一多孔性結構，使封裝膠體可填充於此多孔性結構之流體空間中，以改善習知技術中易從晶片座與散熱片之間產生斷裂的問題，進而提高晶片封裝結構的可靠度及其散熱效果。SUMMARY OF THE INVENTION An object of the present invention is to provide a chip package structure in which a package structure can be filled in a fluid space of a porous structure by a porous structure formed on a surface of a heat sink to improve the ease of the prior art. The problem of breakage between the wafer holder and the heat sink is increased, thereby improving the reliability of the package structure and the heat dissipation effect.
本發明提出一種晶片封裝結構，包括一導線架、一晶片、一散熱片以及一封裝膠體。導線架具有一晶片座以及多個環繞晶片座之引腳，其中，此晶片座具有一上表面以及與其相對之一下表面。而晶片是配置於晶片座之上表面，且與導線架之這些引腳電性連接。散熱片之一表面具有一多孔性結構，使散熱片藉由此多孔性結構而配置於晶片座之下表面。封裝膠體包覆導線架、晶片與散熱片，並填充於上述多孔性結構中，且暴露出部分的散熱片。The invention provides a chip package structure comprising a lead frame, a wafer, a heat sink and an encapsulant. The leadframe has a wafer holder and a plurality of pins surrounding the wafer holder, wherein the wafer holder has an upper surface and a lower surface opposite thereto. The wafer is disposed on the upper surface of the wafer holder and electrically connected to the pins of the lead frame. One surface of the heat sink has a porous structure, so that the heat sink is disposed on the lower surface of the wafer holder by the porous structure. The encapsulant encapsulates the leadframe, the wafer and the heat sink, and is filled in the above porous structure, and a part of the heat sink is exposed.
在本發明之一實施例中，散熱片是由一金屬材料製成。In one embodiment of the invention, the heat sink is made of a metallic material.
在本發明之一實施例中，多孔性結構為一燒結鋼絨。In one embodiment of the invention, the porous structure is a sintered steel wool.
在本發明之一實施例中，多孔性結構包括多個形成於散熱片之表面的凸出部及一形成於這些凸出部之間的流體空間，且部分的凸出部貼附於晶片座之下表面。In an embodiment of the invention, the porous structure includes a plurality of protrusions formed on a surface of the heat sink and a fluid space formed between the protrusions, and a portion of the protrusions are attached to the wafer holder Under the surface.
在本發明之一實施例中，此晶片封裝結構更包括多條打線導線，而晶片是透過這些打線導線與上述引腳電性連接。In an embodiment of the invention, the chip package structure further includes a plurality of wire bonding wires, and the chip is electrically connected to the pins through the wire bonding wires.
在本發明之一實施例中，晶片封裝結構更包括一黏著層，配置於晶片與晶片座之間。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the wafer and the wafer holder.
本發明之晶片封裝結構主要是在配置於晶片座下方的散熱片上形成一多孔性結構。如此，在形成封裝膠體時，膠體會在多孔性結構的流體空間中流動，使其填充於多孔性結構的整個流體空間內。此多孔性結構與填充於其流體空間內的封裝膠體會緊密地貼合於晶片座的下表面，而不 致發生習知技術中因散熱片的表面粗糙度過大而使得晶片座與散熱片之間發生斷裂的情形，進而提升整個晶片封裝結構的可靠度。此外，由於晶片座與散熱片之間不會有空氣存在的原故，因此，亦有助於提升此晶片封裝結構的散熱效果。The chip package structure of the present invention mainly forms a porous structure on a heat sink disposed under the wafer holder. Thus, when the encapsulant is formed, the colloid will flow in the fluid space of the porous structure to fill the entire fluid space of the porous structure. The porous structure and the encapsulant filled in the fluid space thereof closely adhere to the lower surface of the wafer holder without In the prior art, the surface roughness of the heat sink is too large to cause breakage between the wafer holder and the heat sink, thereby improving the reliability of the entire chip package structure. In addition, since there is no air between the wafer holder and the heat sink, it also helps to improve the heat dissipation effect of the chip package structure.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2繪示為根據本發明之第一實施例的一種晶片封裝結構的剖面示意圖。請參考圖2所示，本發明之晶片封裝結構200主要包含一導線架210、一晶片220、一散熱片230以及一封裝膠體240。以下將搭配圖示說明此晶片封裝結構200所包含之各元件以及元件之間的連接關係。2 is a cross-sectional view showing a chip package structure in accordance with a first embodiment of the present invention. Referring to FIG. 2 , the chip package structure 200 of the present invention mainly includes a lead frame 210 , a wafer 220 , a heat sink 230 , and an encapsulant 240 . Hereinafter, the components included in the chip package structure 200 and the connection relationship between the components will be described with reference to the drawings.
導線架210具有一晶片座212以及多個環繞於晶片座212外圍之引腳214。其中，晶片座212是用以承載晶片220，而引腳214則是作為與晶片220電性連接之接點使用。如圖2所示，晶片座212具有一上表面212a以及與其相對之一下表面212b。晶片220是配置於晶片座212的上表面212a，且與導線架210的引腳214電性連接。在此實施例中，晶片220是透過一黏著層250而固定於晶片座212之上表面212a，而晶片220是透過多條以打線接合技術形成的打線導線260與引腳214電性連接。然而，晶片220亦可透過其他方式與引腳214電性連接，本發明對於晶片 220與導線架210之間電性連接的方式不作任何限制。The leadframe 210 has a wafer holder 212 and a plurality of pins 214 that surround the periphery of the wafer holder 212. The wafer holder 212 is used to carry the wafer 220, and the pin 214 is used as a contact for electrically connecting to the wafer 220. As shown in FIG. 2, the wafer holder 212 has an upper surface 212a and a lower surface 212b opposite thereto. The wafer 220 is disposed on the upper surface 212 a of the wafer holder 212 and electrically connected to the leads 214 of the lead frame 210 . In this embodiment, the wafer 220 is fixed to the upper surface 212a of the wafer holder 212 through an adhesive layer 250. The wafer 220 is electrically connected to the leads 214 through a plurality of wire bonding wires 260 formed by wire bonding techniques. However, the wafer 220 can also be electrically connected to the pin 214 by other means. The manner in which the electrical connection between the 220 and the lead frame 210 is electrically connected is not limited.
散熱片230是由一具有高導熱係數的金屬材料所製成，且其表面230a具有一多孔性結構232，使散熱片230藉由此多孔性結構232而配置於晶片座212之下表面212b。此多孔性結構232之特性在於：其結構中具有一流體空間S，使流體可流入此流體空間S的各個地方。在此實施例中，多孔性結構232是由一常應用於熱管之內表面的燒結鋼絨所組成，而此燒結鋼絨結構中同樣具有一流體空間，使流體可於此流體空間中流動。The heat sink 230 is made of a metal material having a high thermal conductivity, and the surface 230a has a porous structure 232, so that the heat sink 230 is disposed on the lower surface 212b of the wafer holder 212 by the porous structure 232. . The porous structure 232 is characterized in that it has a fluid space S in its structure so that fluid can flow into various places of the fluid space S. In this embodiment, the porous structure 232 is comprised of a sintered steel wool commonly applied to the inner surface of a heat pipe, and the sintered steel pile structure also has a fluid space in which fluid can flow in the fluid space.
封裝膠體240包覆導線架210、晶片220與散熱片230，以保護上述元件免於受損及受潮。在形成封裝膠體240的過程中，由於膠體亦屬於流體的一種，因此，膠體會在多孔性結構232的流體空間S中流動，並填充於多孔性結構232的流體空間S中，使多孔性結構232與晶片座212之間不會有空氣存在。如此，當膠體固化後，多孔性結構232與填充於其流體空間S內的封裝膠體240會緊密地貼合於晶片座212的下表面212b，而不致發生習知技術中因散熱片的表面粗糙度過大而使得空氣存留在晶片座與散熱片之間，進而造成晶片封裝結構從晶片座與散熱片之間產生斷裂的情形。The encapsulant 240 encloses the leadframe 210, the wafer 220 and the heat sink 230 to protect the components from damage and moisture. In the process of forming the encapsulant 240, since the colloid is also a kind of fluid, the colloid flows in the fluid space S of the porous structure 232 and is filled in the fluid space S of the porous structure 232, so that the porous structure There is no air present between 232 and wafer holder 212. Thus, when the colloid is solidified, the porous structure 232 and the encapsulant 240 filled in the fluid space S thereof closely adhere to the lower surface 212b of the wafer holder 212 without causing surface roughness due to the heat sink in the prior art. Excessively large, air is trapped between the wafer holder and the heat sink, thereby causing the wafer package structure to break from between the wafer holder and the heat sink.
此外，封裝膠體240亦會暴露出部分的散熱片230，例如：散熱片230的底部，使晶片220運作時所產生的熱能可透過晶片座212、散熱片230及封裝膠體240而散逸到大氣環境中。In addition, the encapsulant 240 also exposes a portion of the heat sink 230, such as the bottom of the heat sink 230, so that the heat generated by the operation of the wafer 220 can be dissipated to the atmosphere through the wafer holder 212, the heat sink 230, and the encapsulant 240. in.
圖3繪示為根據本發明之第二實施例的一種晶片封裝結構的剖面示意圖。請參考圖3所示，此晶片封裝結構200'之元件與元件之間的連接關係大致上與圖2中所示之晶片封裝結構200相同，而二者不同之處主要在於：此晶片封裝結構200'之散熱片230'其表面230a'上的多孔性結構232'與圖2中所示之多孔性結構232不同。如圖3所示，此多孔性結構232'是由多個形成於散熱片230'之表面230a'的凸出部232'及一形成於這些凸出部232'之間的流體空間S'所構成。同樣地，在形成封裝膠體240'的過程中，膠體會填充在多孔性結構232'的流體空間S'中，使多孔性結構232'與晶片座212之間不會有空氣存在。3 is a cross-sectional view showing a chip package structure in accordance with a second embodiment of the present invention. Referring to FIG. 3, the connection relationship between the components and components of the chip package structure 200' is substantially the same as the chip package structure 200 shown in FIG. 2, and the difference between the two is mainly: the chip package structure The 200' fins 230' have a porous structure 232' on the surface 230a' that is different from the porous structure 232 shown in FIG. As shown in FIG. 3, the porous structure 232' is formed by a plurality of protrusions 232' formed on the surface 230a' of the heat sink 230' and a fluid space S' formed between the protrusions 232'. Composition. Similarly, during the formation of the encapsulant 240', the colloid will fill the fluid space S' of the porous structure 232' such that no air is present between the porous structure 232' and the wafer holder 212.
圖4A繪示為圖3中所示之散熱片的上視示意圖。請參考圖4A所示，在本發明之一實施例中，此散熱片230'上的多孔性結構232'是由多個橫截面為圓形的凸出部232a'及一形成於這些凸出部232a'之間的流體空間S'所構成。然而，請參考圖4B所示，亦可將這些凸出部232b'製作為具有矩形之橫截面或是其他合適之形狀，本發明對於凸出部的形狀不作任何限制。4A is a top plan view of the heat sink shown in FIG. 3. Referring to FIG. 4A, in an embodiment of the present invention, the porous structure 232' on the heat sink 230' is formed by a plurality of protrusions 232a' having a circular cross section and a protrusion formed thereon. The fluid space S' between the portions 232a' is formed. However, as shown in FIG. 4B, the protrusions 232b' may also be formed to have a rectangular cross section or other suitable shape. The present invention does not impose any limitation on the shape of the protrusions.
此外，散熱片230'之凸出部232a'可利用沖壓(punch)方式製作而成。舉例而言，可先於模具上作出對應於這些凸出部232a'的凹部，再以沖壓方式於散熱片230'上形成這些凸出部232a'。Further, the protruding portion 232a' of the heat sink 230' can be fabricated by a punching method. For example, recesses corresponding to the projections 232a' may be formed on the mold, and the projections 232a' may be formed on the heat sink 230' by stamping.
綜上所述，本發明之晶片封裝結構主要是在配置於晶片座下方的散熱片上形成一多孔性結構。如此，在形成封 裝膠體時，膠體會在多孔性結構的流體空間中流動，使其填充於多孔性結構的整個流體空間內。由於此多孔性結構與填充於其流體空間內的封裝膠體會緊密地貼合於晶片座的下表面，因此，不致發生習知技術中因散熱片的表面粗糙度過大而使得空氣存留在晶片座與散熱片之間的情形，以避免由晶片座與散熱片之間發生斷裂，進而提升整個晶片封裝結構的可靠度。此外，由於晶片座與散熱片之間不會有空氣存在的原故，因此，亦有助於提升此晶片封裝結構的散熱效果。In summary, the chip package structure of the present invention mainly forms a porous structure on the heat sink disposed under the wafer holder. So, forming a seal When the colloid is loaded, the colloid will flow in the fluid space of the porous structure, filling it into the entire fluid space of the porous structure. Since the porous structure and the encapsulant filled in the fluid space thereof closely adhere to the lower surface of the wafer holder, the prior art does not cause the air to remain in the wafer holder due to the excessive surface roughness of the heat sink. The situation with the heat sink avoids breakage between the wafer holder and the heat sink, thereby improving the reliability of the entire chip package structure. In addition, since there is no air between the wafer holder and the heat sink, it also helps to improve the heat dissipation effect of the chip package structure.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
100‧‧‧四方扁平晶片封裝結構100‧‧‧Quad Flat Chip Package Structure
200、200'‧‧‧晶片封裝結構200, 200'‧‧‧ chip package structure
110、210‧‧‧導線架110, 210‧‧‧ lead frame
112、212‧‧‧晶片座112, 212‧‧‧ wafer holder
114、214‧‧‧引腳114, 214‧‧‧ pin
120、220‧‧‧晶片120, 220‧‧‧ wafer
130、230、230'‧‧‧散熱片130, 230, 230'‧‧ ‧ heat sink
140、240、240'‧‧‧封裝膠體140, 240, 240'‧‧‧Package colloid
212a‧‧‧上表面212a‧‧‧ upper surface
212b‧‧‧下表面212b‧‧‧ lower surface
230a、230a'‧‧‧表面230a, 230a'‧‧‧ surface
232‧‧‧多孔性結構232‧‧‧Porous structure
232'、232a'、232b'‧‧‧凸出部232', 232a', 232b'‧‧‧ protruding parts
250‧‧‧黏著層250‧‧‧Adhesive layer
260‧‧‧打線導線260‧‧‧Wire conductor
S、S'‧‧‧流體空間S, S'‧‧‧ fluid space
圖1繪示為習知之一種四方扁平晶片封裝結構的示意圖。FIG. 1 is a schematic diagram of a conventional quad flat wafer package structure.
圖2繪示為根據本發明之第一實施例的一種晶片封裝結構的剖面示意圖。2 is a cross-sectional view showing a chip package structure in accordance with a first embodiment of the present invention.
圖3繪示為根據本發明之第二實施例的一種晶片封裝結構的剖面示意圖。3 is a cross-sectional view showing a chip package structure in accordance with a second embodiment of the present invention.
圖4A繪示為圖3中所示之散熱片的上視示意圖。4A is a top plan view of the heat sink shown in FIG. 3.
圖4B繪示為另一種散熱片的上視示意圖。FIG. 4B is a top view of another heat sink.
200‧‧‧晶片封裝結構200‧‧‧ Chip package structure
210‧‧‧導線架210‧‧‧ lead frame
212‧‧‧晶片座212‧‧‧ wafer holder
214‧‧‧引腳214‧‧‧ pin
220‧‧‧晶片220‧‧‧ wafer
230‧‧‧散熱片230‧‧‧ Heat sink
240‧‧‧封裝膠體240‧‧‧Package colloid
212a‧‧‧上表面212a‧‧‧ upper surface
212b‧‧‧下表面212b‧‧‧ lower surface
230a‧‧‧表面230a‧‧‧ surface
250‧‧‧黏著層250‧‧‧Adhesive layer
260‧‧‧打線導線260‧‧‧Wire conductor
S‧‧‧流體空間S‧‧‧ Fluid Space
Claims (5)
Priority Applications (1)
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|---|---|---|---|
| TW097125237A TWI420624B (en) | 2008-07-04 | 2008-07-04 | Semiconductor chip package structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097125237A TWI420624B (en) | 2008-07-04 | 2008-07-04 | Semiconductor chip package structure |
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| Publication Number | Publication Date |
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| TW201003863A TW201003863A (en) | 2010-01-16 |
| TWI420624B true TWI420624B (en) | 2013-12-21 |
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Citations (1)
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|---|---|---|---|---|
| TW200412659A (en) * | 2003-01-10 | 2004-07-16 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipating structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW200412659A (en) * | 2003-01-10 | 2004-07-16 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipating structure |
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