TWI420191B - Pixel circuitry for display apparatus - Google Patents

Description

Pixel circuit of display device

The present invention relates to a pixel circuit of a display device, and more particularly to a voltage range for increasing a pixel signal passing through a scan switch to a pixel electrode, and increasing a capacitance of a storage element for storing a pixel signal at a low operating frequency. Pixel circuit.

The display panel of a liquid crystal display is composed of a pixel array having a plurality of pixel circuits. 1A is a circuit diagram of a conventional pixel circuit. Referring to FIG. 1A, the pixel circuit 100A includes a switching element 111A and a storage capacitor 112A. The switching element 111A is implemented by an NMOS transistor, the gate is coupled to the scan line SC to receive the scan signal, the first source/drain is coupled to the data line DA to receive the pixel signal, and the second source/drain is coupled Pixel electrode Pix. The storage capacitor 112A is also implemented by an NMOS transistor. The gate is coupled to the pixel electrode Pix, and the first and second source/drain electrodes are coupled to a voltage (eg, a voltage of a common electrode). When the scan signal is enabled to turn on the switching element 111A, the pixel signal on the data line DA is transmitted to the pixel electrode Pix and stored in the storage capacitor 112A to control the steering of the liquid crystal.

As is known, the NMOS transistor is fabricated on a P-type substrate coupled to a negative supply voltage VSSA. If the voltage range of the pixel signal is between the positive power supply voltage VDDA and the negative power supply voltage VSSA, not all pixel signals within this voltage range may pass through the switching element 111A to be transmitted to the pixel electrode Pix due to the influence of the main body effect. In other words, only the voltage range is The pixel signal in the voltage VSSA to the voltage VDDA-ΔV can be transmitted to the pixel voltage Pix, and the pixel signal in the high voltage range of the voltage VDDA-ΔV to the voltage VDDA cannot be transmitted. From this, it can be seen that the voltage range across the switching element 111A is limited.

In addition, storage capacitor 112A is also referred to as an NMOS capacitor, and this capacitance changes as the gate is at a low operating frequency. Figure 1C is a graph of the capacitance of a MOS capacitor at a low operating frequency. Referring to FIG. 1C, the curve 101 is a capacitance Cgb of the NMOS capacitor. When the gate voltage Vg is less than zero, an accumulation layer is formed between the gate and the substrate as a capacitor. When the gate voltage Vg is greater than zero but less than the threshold voltage Vtn, the depletion layer is formed on the substrate under the gate oxide layer, and the thickness of the depletion layer increases as the gate voltage increases to reduce the NMOS capacitance. Capacitance Cgb.

At the same time, the capacitance Cgb of the NMOS capacitor is composed of a gate capacitance series depletion layer capacitor, wherein the gate capacitance is formed between two parallel planes of the gate and the depletion layer. In other words, at a low operating frequency, when the gate voltage Vg is greater than zero and less than the threshold voltage Vtn, the capacitance Cgb of the NMOS capacitor cannot be as expected. When the gate voltage Vg is greater than the threshold voltage Vtn, the channel layer is formed on the substrate under the gate oxide layer, and the capacitance of the NMOS capacitor is formed by the gate capacitance formed between the parallel planes of the gate and the channel layer.

FIG. 1B is a circuit diagram of another conventional pixel circuit. Referring to FIG. 1B, the switching element 111B and the storage capacitor 112B are implemented by a PMOS transistor, wherein the PMOS transistor is coupled to the N-type substrate and coupled to the positive power supply voltage VDDA. Due to the effect of the main effect, only the voltage range is between the voltage The pixel signal in VSSA + ΔV to the voltage VDDA can be transmitted to the pixel voltage Pix, and the pixel signal in the low voltage range of the voltage VSSA to the voltage VSSA + ΔV cannot be transmitted. It can be seen from this that the voltage range across the switching element 111 is limited. Referring to FIG. 1C , the curve 102 is a capacitance Cgb of the storage capacitor 112 implemented in the PMOS transistor, and the storage capacitor 112 is referred to as a PMOS capacitor. Similarly, at a low operating frequency, when the gate voltage Vg is less than zero and greater than the threshold voltage Vtp, the capacitance Cgb of the PMOS capacitor cannot be as expected. The above voltage limitation and insufficient capacitance are the problems that the circuit design of the pixel circuit is extremely difficult to solve.

The present invention provides a pixel circuit that uses a plurality of switches in parallel to transmit a pixel signal having a large voltage range in accordance with a scan signal to avoid the influence of a main effect. In addition, the present invention also provides a pixel circuit that increases the equivalent capacitance of a storage element coupled to a pixel electrode to store a pixel signal.

The present invention provides a pixel circuit of a display device including a first storage element and a switching element. The first storage element has a first end and a second end for storing a pixel signal, wherein the first end of the first storage element receives the pixel signal, and the second end of the first storage element is coupled to the first voltage. The switching element is composed of a plurality of switches including a first switch and a second switch. The first switch has an input end and an output end, and is turned on according to the first signal, wherein the input end of the first switch is coupled to the data line, and the output end of the first switch is coupled to the first storage element. The second switch has an input end and an output end, and is turned on according to the second signal, wherein the input end of the second switch is coupled to the data line, and the second switch is The output end is coupled to the first storage element.

In an embodiment of the invention, the first switch and the second switch are respectively an NMOS transistor and a PMOS transistor.

In an embodiment of the invention, the pixel circuit further includes a multiplexer that generates the first signal and the second signal according to the scan signal. Moreover, the first switch and the second switch are synchronously turned on according to the first signal and the second signal.

The invention also provides a pixel circuit of a display device comprising a first switch, a first storage element and a second storage element. The first switch has an input end and an output end, wherein the input end of the first switch receives the pixel signal, and the first switch is turned on according to the scan signal. The first storage element has a first end and a second end for storing the pixel signal, wherein the first end of the first storage element is coupled to the output end of the first switch, and the second end of the first storage element is coupled to the first voltage . The second storage element has a first end and a second end for storing the pixel signal, wherein the first end of the second storage element is coupled to the output end of the first switch, and the second end of the second storage element is coupled to the second end Voltage.

In an embodiment of the invention, the first storage element and the second storage element are respectively an NMOS capacitor and a PMOS capacitor.

The present invention provides a pixel circuit including first and second switches in parallel to ensure that a pixel signal having a voltage range between a positive power supply voltage and a negative power supply voltage is substantially transparent to the first storage element through the switching element. Avoid the effects of the main effect. In addition, the present invention provides another pixel circuit including a first storage element and a second storage element, one end of the first and second storage elements being coupled to the output end of the first switch for increasing the equivalent capacitance to store the pixel signal.

The above described features and advantages of the present invention will be more apparent from the following description.

It is assumed here that the positive power supply voltage VDDA and the negative power supply voltage VSSA are applied to a display device such as a liquid crystal display. The source driver of the display device can drive the tilt of the liquid crystal and display the gray scale of the image by using a voltage range between the positive power supply voltage VDDA and the negative power supply voltage VSSA. Increasing the voltage range that drives the liquid crystal makes the gray level perceived by the human eye easier to recognize. However, the switching elements of the pixel circuit are realized by MOS transistors, and the voltage range for driving the liquid crystals is often limited due to the main effect. In addition, the storage capacitance of the pixel circuit can be realized by using a MOS capacitor. When the voltage of the pixel signal is between zero and the threshold voltage of the MOS capacitor, the capacitance of the stored pixel signal is insufficient. The embodiments of the present invention described below provide a circuit design of a pixel circuit to solve the above problems.

2A is a circuit diagram of a pixel circuit in accordance with an embodiment of the present invention. Referring to FIG. 2A, the pixel circuit 200 includes a switch SW1 and storage elements 121 and 122. The input end of the switch SW1 is coupled to the data line DA1 to receive the pixel signal Vp, and the output end thereof is coupled to the storage elements 221 and 222. The switch SW1 is turned on according to the scan signal for transmitting the pixel signal Vp on the data line DA1 to the storage elements 221 and 222 to store the pixel signal Vp. In this embodiment, the storage elements 221 and 222 can be NMOS capacitors and PMOS capacitors, respectively. The first end and the second end of the storage element 221 are respectively coupled to the output end of the switch SW1 and the negative power supply voltage VSSA. Storage element 222 The first end and the second end are respectively coupled to the output end of the switch SW1 and the positive power supply voltage VDDA.

Referring to FIG. 1C, a single storage element can be implemented by using an NMOS capacitor or a PMOS capacitor, and its capacitance varies with the gate voltage (that is, the voltage of the pixel signal Vp transmitted to the storage voltage), and when the pixel signal When the voltage of Vp is between zero and the threshold voltage Vtn/Vtp, the capacitance of the stored pixel signal Vp is insufficient. In this embodiment, the equivalent capacitance of the storage elements 221 and 222 can be implemented by using different types of MOS capacitors, which can be increased when the voltage of the pixel signal Vp is between zero and the threshold voltage Vtn/Vtp. The capacitance for storing the pixel signal Vp. 2B is a graph of the equivalent capacitance of the storage element at a low operating frequency in accordance with the embodiment of FIG. 2A. Referring to FIGS. 2A and 2B, the equivalent capacitance Ceq of the storage elements 221 and 222 approximates the average capacitance of the capacitance obtained by using the NMOS capacitor and the PMOS capacitor, respectively. As shown in FIG. 2B, when the voltage of the pixel signal Vp is between zero and the threshold voltage Vtn/Vtp, the equivalent capacitance Ceq of the storage elements 221 and 222 is an effective increase.

3 is a circuit diagram of a pixel circuit in accordance with another embodiment of the present invention. Referring to FIG. 3, the pixel circuit includes a switching element 310, a storage element 321, and a multiplexer 330, wherein the switching element 310 is composed of a plurality of switches. In this embodiment, the switching element 310 includes switches T1 and T2, wherein the switches T1 and T2 can be implemented by using an NMOS transistor and a PMOS transistor, respectively. The switches T1 and T2 are connected in parallel, and are respectively turned on according to the first signal S11 and the second signal transmitted from the scan signal S1. When scanning signals When enabled, the multiplexer 330 generates a first signal having a high logic and a second signal having a low logic to synchronously turn on the switches T1 and T2. Next, the switching element 310 transmits the pixel signal Vp on the data line DA1 to the storage element 321 to store the pixel signal Vp. Conversely, when the scan signal S1 is disabled, the multiplexer 330 generates a first signal S11 having a low logic and a second signal S12 having a high logic to make the switches T1 and T2 non-conductive. The storage element 321 is an NMOS capacitor or other type of capacitor for storing the pixel signal Vp transmitted from the switching element 310, and other types such as a polysilicon layer-insulation layer-polysilicon layer structure, a metal layer-insulation layer-metal layer structure .

As can be seen from the above, the voltage range formed between the voltage VDDA and the voltage VSSA cannot transmit signals of all voltage ranges through a single switch, and includes a single switch realized by an NMOS transistor or a PMOS transistor. In the present embodiment, the switches T1 and T2 constitute a transfer gate and are synchronously turned on to transmit the pixel signal Vp having a voltage range between the voltage VDDA and the voltage VSSA without distortion. In other words, the pixel signal Vp having a low voltage can be transmitted through the switch T1 to be transmitted to the storage element 321 without distortion, and the pixel signal Vp having a high voltage can be transmitted through the switch T2 without being distorted.

4 is a circuit diagram of a pixel circuit in accordance with still another embodiment of the present invention. Referring to FIG. 4, the embodiment of FIG. 4 is different from the embodiment of FIG. 3 in that the pixel circuit further includes a storage element 422, and the storage element 422 can be implemented by using a PMOS capacitor. Referring to FIG. 2A and FIG. 2B, when the voltage of the pixel signal Vp is between zero and the threshold voltage Vtn/Vtp, the connection manner of the storage elements 421 and 422 can increase the equivalent capacitance thereof for storing the pixel letter. No. Vp.

In summary, the pixel circuit of the embodiment of the present invention implements two switches by using different types of MOS transistors, and parallels the two switches to ensure pixel signals with voltage ranges between VDDA and VSSA. In general, the switching element can be fully transmitted to the first storage element to avoid the effects of the main effect. Increasing the voltage range of the driving pixel circuit can improve the display quality because the large voltage range can drive the pixel circuit to display more grayscale of the image. In addition, the pixel circuit utilizes different types of MOS capacitors to implement two storage elements for increasing the capacitance of the stored pixel signals.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100A, 100B, 200, 300, 400‧‧‧ pixel circuits

101, 102‧‧‧ Curve

111A, 111B, 310, 410‧‧‧ Switching components

112A, 112B‧‧‧ storage capacitor

221, 222, 321, 421, 422 ‧ ‧ storage components

330, 430‧‧‧ multiplexer

Cgb, Ceq, C2, C1‧‧‧ capacitance

DA, DA1‧‧‧ data line

SC‧‧‧ scan line

S1, S11, S12‧‧ signals

SW1, T1, T2‧‧‧ switch

Pix‧‧‧electrode

VDDA, VSSA, Vtp, Vtn, Vg‧‧‧ voltage

Vp‧‧ ‧ pixel signal

1A is a circuit diagram of a conventional pixel circuit.

FIG. 1B is a circuit diagram of another conventional pixel circuit.

Figure 1C is a graph of the capacitance of a MOS capacitor at a low operating frequency.

2A is a circuit diagram of a pixel circuit in accordance with an embodiment of the present invention.

2B is a graph of the equivalent capacitance of the storage element at a low operating frequency in accordance with the embodiment of FIG. 2A.

3 is a circuit diagram of a pixel circuit in accordance with another embodiment of the present invention.

4 is a circuit diagram of a pixel circuit in accordance with still another embodiment of the present invention.

200‧‧‧pixel circuit

221, 222‧‧‧ storage elements

DA1‧‧‧ data line

S1‧‧‧ signal

SW1‧‧‧ switch

VDDA, VSSA‧‧‧ voltage

Vp‧‧ ‧ pixel signal

Claims (9)

A pixel circuit of a display device includes: a first storage element having a first end and a second end for storing a pixel signal, wherein the first end of the first storage element receives the pixel signal, the first The second end of the storage element is coupled to a first voltage; the second storage element has a first end and a second end for storing the pixel signal, wherein the first end of the second storage element receives the a pixel signal, the second end of the second storage element is coupled to a second voltage; and a switching element is composed of a plurality of switches, including: a first switch having an input end and an output end, according to a first The signal is turned on, wherein the input end of the first switch is coupled to a data line, the output end of the first switch is coupled to the first storage element, and the second switch has an input end and an output end, according to The second signal is turned on, wherein the input end of the second switch is coupled to the data line, and the output end of the second switch is coupled to the first storage element, wherein the first end of the first storage element and the second First of storage components Coupled to the output terminal of the first switch and the second switch. The pixel circuit of claim 1, wherein the first switch and the second switch are synchronously turned on according to the first signal and the second signal. The pixel circuit of claim 1, wherein the first switch and the second switch are an NMOS transistor and a PMOS transistor, respectively. For example, the pixel circuit described in claim 1 further includes: A multiplexer generates the first signal and the second signal according to a scan signal. A pixel circuit of a display device includes: a first switch having an input end and an output end, wherein an input end of the first switch receives a pixel signal, and the first switch is turned on according to a scan signal; a storage element having a first end and a second end for storing the pixel signal, wherein the first end of the first storage element is coupled to the output end of the first switch, and the second end of the first storage element The second storage element has a first end and a second end for storing the pixel signal, wherein the first end of the second storage element is coupled to the first switch The second end of the second storage element is coupled to a second voltage. The pixel circuit of claim 5, wherein the first storage element and the second storage element are composed of a plurality of MOS capacitors. The pixel circuit of claim 6, wherein the first storage element and the second storage element are an NMOS capacitor and a PMOS capacitor, respectively. The pixel circuit of claim 5, further comprising: a second switch having an input end and an output end, wherein the input end of the second switch is coupled to the input end of the first switch, the The output of the second switch is coupled to the output of the first switch. The pixel circuit of claim 8, wherein the first switch and the second switch are synchronously turned on according to the scan signal.