TWI407329B - Transmitting hardware structure for high speed differential signals - Google Patents

Abstract

A transmitting structure for high speed differential signals includes a signal controlling chip, a first pad for a first connector, a plurality of first transmitting lines, a second pad for a second connector and a plurality of second transmitting lines. The first pad is connected to the signal controlling chip via the first transmitting lines. The second pad is connected to the first pad via the second transmitting lines. Each second transmitting line is connected to a switch. The transmitting structure for high speed differential signals forms two types of pads for fixing two kinds of connector on the motherboard. Different kinds of connectors are selectively mounted on corresponding pad by controlling the states of the switches. The transmitting structure satisfies different clients, and also saves the cost of design for motherboard.

Description

High-speed differential signal transmission hardware architecture

The present invention relates to a high-speed differential signal transmission hardware architecture, and more particularly to a transmission hardware architecture that can flexibly support connectors of different specifications.

On the current general PC motherboard, in addition to the central processing unit, the control chipset, there are a plurality of connectors for installing the interface card. With the development of the electronics industry, the functions of the control chip are further improved. The same control chip can support connectors of different specifications. For example, a PCI-Express control chip can support one PCI-Express x8 connector or two at the same time. PCI-Express x4 connector. Different motherboard product specifications will choose to install different connectors. If some manufacturers require only one PCI-Express x8 connector on the motherboard, some manufacturers require two PCI-Express x4 on the motherboard. The connector, therefore, allows the control chip to support two types of connectors, but only one type of production can be selected during production, that is, a motherboard supporting one PCI-Express x8 connector, or two PCI-Express x4 connectors. Motherboard, the two cannot be shared. Therefore, according to the requirements of different manufacturers, it is necessary to redesign the layout of the motherboard, which increases the cost of the motherboard design. Therefore, how to provide a motherboard wiring structure, using the same motherboard wiring, can flexibly support connectors of different specifications, and maintain signal integrity during line operation, which is an urgent problem to be solved in the industry.

Therefore, it is necessary to improve the conventional motherboard wiring structure to eliminate the above-mentioned defects.

In view of the above, it is necessary to provide a high-speed differential signal transmission hardware architecture that can selectively connect connectors of different specifications.

A high speed differential signal transmission hardware architecture includes a signal control chip, a first connector pad, a plurality of first transmission lines, a second connector pad, and a plurality of second transmission lines. The first connector pad is connected to the signal control chip through the first transmission lines, and the second connector pad is connected to the first connector pad through the second transmission lines, and each second transmission line is connected A switch.

The high-speed differential signal transmission hardware architecture has two pads for mounting two connectors on one motherboard, and only needs to control the state of the switch to selectively install different connectors to meet the needs of different customers. It plays the role of controlling the chip and saves the design cost of the motherboard.

Referring to FIG. 1, a high speed differential signal transmission hardware architecture 20 includes a signal control chip 22, a first connector pad 24, a second connector pad 26, a plurality of first transmission lines 28, and a plurality of second transmission lines 29. The first connector pad 24 is connected to the signal control chip 22 through the first transmission line 28, and the second connector pad 26 is connected to the first connector pad 24 through the second transmission line 29. A resistor R is connected in series to a second transmission line 29.

When a first connector is mounted on the first connector pad 24, the second connector pad 26 is vacant, and the resistor R on the second transmission line 29 is removed to break the second transmission line 29. open. The transmission line between the first connector pad 24 and the resistor R becomes a stub, and the open circuit effect of the stub generates signal reflection, in order to prevent the signal from being generated on the second transmission line 29. The reflection affects the integrity of the signal, and the length of the transmission line between the resistor R and the first connector pad 24 is controlled to satisfy the following formula: Lstub<(Tj*v)/2

Where Lstub represents the length of the transmission line between the first connector pad 24 and the resistor R, Tj is the allowable jitter of the high speed differential signal, and v is the speed at which the signal is transmitted in the transmission line.

When a second connector is mounted on the second connector pad 26, the first connector pad 24 is vacant, and the resistors R are mounted on the second transmission lines 29 to turn on each of the second transmission lines 29. The communication between the control chip 22 and the second connector is guaranteed.

In order to reduce the signal transmission loss, the resistance of the resistors R is preferably zero ohms. The resistors R can also be replaced by other devices such as jumpers. The resistors R or jumpers are used as switches in the present invention. When the second connector is connected, the switch is closed, and the switch is connected when the first connector is connected. disconnect.

In addition, in order to obtain better transmission signal quality, the first transmission line 28 may also be connected in series with a current isolation capacitor or an AC coupling capacitor to filter out interference components in the transmission signal.

The high-speed differential signal transmission hardware structure can be used for connecting a high-speed differential signal control chip such as a PCI-Express, SATA/SAS, and a corresponding connector. For example, the signal control chip 22 is a north bridge chip, and the first connector is a PCI- Express x8 connector, this second connector is a PCI-Express x4 connector.

In this way, it is only necessary to provide a motherboard wiring architecture, using the same host Board wiring, flexible support for different specifications of the connector, and maintain signal integrity while the line is working, saving the cost of the motherboard design.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

20‧‧‧High-speed differential signal transmission hardware architecture

22‧‧‧Signal Control Wafer

24‧‧‧First connector pad

26‧‧‧Second connector pad

28‧‧‧First transmission line

29‧‧‧Second transmission line

R‧‧‧resistance

1 is a schematic diagram of a preferred embodiment of a high speed differential signal transmission hardware architecture of the present invention.

20‧‧‧High-speed differential signal transmission hardware architecture

22‧‧‧Signal Control Wafer

24‧‧‧First connector pad

26‧‧‧Second connector pad

28‧‧‧First transmission line

29‧‧‧Second transmission line

R‧‧‧resistance

Claims (7)

A high-speed differential signal transmission hardware structure includes a signal control chip, a first connector pad, and a plurality of first transmission lines. The first connector pad is connected to the signal control chip through the first transmission lines. The improvement is that the high-speed differential signal transmission hardware structure further includes a second connector pad and a plurality of second transmission lines, and the second connector pad is connected to the first connector pad through the second transmission lines, and each A switch is connected to a second transmission line. The high-speed differential signal transmission hardware architecture of claim 1, wherein the first connector pad is for mounting a first connector, and the second connector pad is for mounting a second connector. The first connector and the second connector are selectively mounted on the corresponding connector pads. When the second connector is mounted, the switches are closed, and the switches are disconnected when the first connector is mounted. The high-speed differential signal transmission hardware architecture of claim 1, wherein the length of the transmission line between the switches and the first connector pad satisfies the formula Lstub<(Tj*v)/2, wherein Lstub represents The length of the transmission line between a connector pad and the switch, Ti is the allowable jitter of the high-speed differential signal, and v is the speed at which the signal is transmitted in the transmission line. For example, the high-speed differential signal transmission hardware architecture described in claim 1 wherein each switch is a zero ohm resistor. For example, the high-speed differential signal transmission hardware architecture described in claim 1 wherein each switch is a jumper. The high-speed differential signal transmission hardware architecture of claim 1, wherein a capacitor is connected in series on each of the first transmission lines. The high-speed differential signal transmission hardware architecture of claim 1, wherein the connector control chip is a PCI-Express high-speed differential signal control chip, and the first and second connectors are PCI-Express connectors.