TWI400782B - Packaging substrate with heat-dissipation capability and the manufacturing method thereof - Google Patents
Packaging substrate with heat-dissipation capability and the manufacturing method thereof Download PDFInfo
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- TWI400782B TWI400782B TW97144245A TW97144245A TWI400782B TW I400782 B TWI400782 B TW I400782B TW 97144245 A TW97144245 A TW 97144245A TW 97144245 A TW97144245 A TW 97144245A TW I400782 B TWI400782 B TW I400782B
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- 239000000758 substrate Substances 0.000 title claims description 114
- 230000017525 heat dissipation Effects 0.000 title claims description 86
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000004806 packaging method and process Methods 0.000 title description 2
- 239000010410 layer Substances 0.000 claims description 393
- 239000002184 metal Substances 0.000 claims description 79
- 229910052751 metal Inorganic materials 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 23
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 230000000149 penetrating effect Effects 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011889 copper foil Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 21
- 230000000694 effects Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 239000003973 paint Substances 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 239000004743 Polypropylene Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本發明係關於一種封裝基板及其製法,尤指一種散熱封裝基板及其製法。The invention relates to a package substrate and a preparation method thereof, in particular to a heat dissipation package substrate and a preparation method thereof.
隨著電子產業的蓬勃發展,電子產品亦逐漸邁入具有多功能、高性能之發展趨勢。為滿足半導體封裝件高積集度(integration)及微型化(miniaturization)的封裝需求,以供更多主被動元件及線路載接,半導體封裝基板亦逐漸由雙層演變成多層(multi-layer),俾在有限的空間下運用層間連接技術(interlayer connection)以擴大半導體封裝基板上可供利用的線路佈局面積,藉此配合高線路密度之積體電路(integrated circuit)需要,降低封裝基板的厚度,以滿足電子產品輕薄短小之需求。With the rapid development of the electronics industry, electronic products have gradually entered a development trend of multi-functionality and high performance. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, for more active and passive components and lines to be carried, the semiconductor package substrate is gradually evolved from double layer to multi-layer.俾Using an interlayer connection in a limited space to expand the layout area available on the semiconductor package substrate, thereby reducing the thickness of the package substrate in accordance with the need for a high circuit density integrated circuit. To meet the needs of light and short electronic products.
如圖1A-1C,其為一習知空腔區朝上(cavity-up)打線式(wire bonding)封裝基板之製備流程圖。首先,如圖1A所示,必須提供二個核心板10,11以及一例如材料為聚丙烯(PP,poly propylene)之介電層12。將其中一核心板10以及一介電層12壓合後,挖出一開口100,120,接著與另一核心板11壓合,以形成一具有可容置晶片之開口100,120的基板本體(如圖1B),並於其上下表面分別形成一防焊層14,15,其係分別具有一開口140及複數開孔150顯露部分線路層以作為電性接觸墊16,以完成該封裝基板1。如圖1D所示,係該封裝基板1之應用,將一半導體晶片17置入此封裝基板1之開口100,120中,並以打線連接(wire bonding)之導線18使半導體晶片17電性連接至最外層之電性接觸墊16。最後以封裝材料19覆蓋該導線18以及半導體晶片17,如此則完成一空腔區朝上打線式封裝基板。1A-1C, which is a flow chart of a conventional cavity-up wire bonding package substrate. First, as shown in FIG. 1A, two core boards 10, 11 and a dielectric layer 12 of, for example, polypropylene (PP) must be provided. After pressing one of the core plates 10 and the dielectric layer 12, an opening 100, 120 is dug out, and then pressed against the other core plate 11 to form a substrate body having openings 100, 120 for accommodating the wafer (see FIG. 1B). And forming a solder resist layer 14, 15 respectively on the upper and lower surfaces thereof, respectively having an opening 140 and a plurality of openings 150 exposing a portion of the wiring layer as the electrical contact pads 16 to complete the package substrate 1. As shown in FIG. 1D, for the application of the package substrate 1, a semiconductor wafer 17 is placed in the openings 100, 120 of the package substrate 1, and the semiconductor wafer 17 is electrically connected to the wire 18 by wire bonding. The outer layer of electrical contact pads 16. Finally, the wire 18 and the semiconductor wafer 17 are covered by the encapsulating material 19, thus completing a cavity area facing up the package substrate.
惟於前述結構中,半導體晶片17藉由該導線18以電性連接核心板10外表面之電性接觸墊16。由於具有二個核心板10,11,因此造成封裝基板整體結構的厚度以及體積無法降低。此外,半導體晶片17係容置於封裝基板1之開口100,120內部,並以封裝材料19覆蓋導線18以及半導體晶片17,加上兩層核心板10,11的厚度較大,導致位於內部之半導體晶片17不易散熱。再者,由於電性接觸墊16僅製作於核心板10之外表面,因此線路密度可增加的程度有限,無法達到大幅提升線路密度的效果。In the foregoing structure, the semiconductor wafer 17 is electrically connected to the electrical contact pads 16 on the outer surface of the core board 10 by the wires 18. Since there are two core plates 10, 11, the thickness and volume of the entire structure of the package substrate cannot be reduced. In addition, the semiconductor wafer 17 is housed inside the openings 100, 120 of the package substrate 1, and covers the wires 18 and the semiconductor wafer 17 with the encapsulation material 19, and the thickness of the two core plates 10, 11 is large, resulting in the semiconductor wafer located inside. 17 is not easy to heat. Moreover, since the electrical contact pads 16 are only formed on the outer surface of the core board 10, the degree of increase in the line density is limited, and the effect of greatly increasing the line density cannot be achieved.
另外,由於貫穿基板整體之導電通孔13的設置,需要較大的製作表面積,因此造成封裝基板整體更無法達到微小化的目標。In addition, since the installation of the conductive vias 13 through the entire substrate requires a large surface area to be produced, the entire package substrate is less likely to be miniaturized.
因此,如何提出一種封裝基板及其製法,以克服習知空腔區朝上打線式封裝結構中,整體之封裝尺寸較高、不易散熱等問題,並有效地提升線路密度使電性效果達到提升,實已成為目前業界亟待解決之課題。Therefore, how to propose a package substrate and a manufacturing method thereof to overcome the problems of the conventional package area facing up the wire-type package structure, the overall package size is high, and it is not easy to dissipate heat, and the line density is effectively improved to improve the electrical effect. It has become an urgent issue in the industry.
本發明之主要目的係在提供一種散熱封裝基板及其製法,俾能使封裝基板具有較佳之散熱效果,且有效地增加封裝基板之線路密度,並有效地縮小封裝基板整體之封裝尺寸,進而提高電性效能。The main object of the present invention is to provide a heat dissipating package substrate and a method for manufacturing the same, which can provide a better heat dissipation effect of the package substrate, effectively increase the line density of the package substrate, and effectively reduce the package size of the package substrate as a whole, thereby improving the package size. Electrical performance.
為達成上述目的,本發明提供一種散熱封裝基板,包括:一核心板,係具有相對之第一表面及第二表面;一第一線路層,係設於該第一表面上,並具有一晶片置放墊;一第二線路層,係設於該第二表面上;一第一介電層,係設於該第一線路層上,並具有一開口,以顯露該晶片置放墊;一第三線路層,係設於該第一介電層上,並具有複數圍繞該開口周緣之第二打線墊;一第二介電層,係設於該第二線路層上;以及一第四線路層,係設於該第二介電層上。In order to achieve the above object, the present invention provides a heat dissipation package substrate, comprising: a core plate having opposite first and second surfaces; a first circuit layer disposed on the first surface and having a wafer a first circuit layer is disposed on the first circuit layer and has an opening to expose the wafer placement pad; a third circuit layer is disposed on the first dielectric layer and has a plurality of second bonding pads surrounding the periphery of the opening; a second dielectric layer is disposed on the second circuit layer; and a fourth The circuit layer is disposed on the second dielectric layer.
上述之散熱封裝基板中,可更包括圍繞該晶片置放墊周緣之複數第一打線墊,且該開口並顯露該些第一打線墊。The heat dissipation package substrate may further include a plurality of first wire pads surrounding the periphery of the wafer, and the openings and the first wire pads are exposed.
上述之散熱封裝基板中,其核心板更具有一貫穿核心板之散熱通孔連接至該晶片置放墊,該第二介電層更具有一貫穿該第二介電層之散熱盲孔,且散熱盲孔係對應連接至該散熱通孔。In the above heat dissipation package substrate, the core board further has a heat dissipation through hole penetrating through the core board to the wafer placement pad, and the second dielectric layer further has a heat dissipation blind hole penetrating the second dielectric layer, and The heat dissipation blind hole is correspondingly connected to the heat dissipation through hole.
上述之散熱封裝基板中,該核心板係為絕緣板;復包括導電通孔,係貫穿該核心板本體,並電性連接該第一及第二線路層。In the above heat-dissipating package substrate, the core plate is an insulating plate; and the conductive through-holes are formed through the core plate body and electrically connected to the first and second circuit layers.
上述之散熱封裝基板中,復包括金屬保護層,係設於該第一打線墊、第二打線墊、以及該晶片置放墊上。The heat dissipation package substrate further includes a metal protection layer disposed on the first wire bonding pad, the second wire bonding pad, and the wafer placing pad.
本發明復提供一種散熱封裝基板之製法,係包括:(a)提供一核心板,該核心板具有相對之一第一及第二表面,且於該第一及第二表面之上分別設有一第一及第二金屬層,並形成有貫穿該核心板及第一及第二金屬層之複數通孔;(b)於該第一及第二金屬層及通孔之內壁上全面形成一導電晶種層;(c)於該第一及第二金屬層上之導電晶種層上分別形成一第一及第二阻層,並於該第一及第二阻層形成複數圖案化開口區;(d)藉由該導電晶種層,於各該圖案化開口區及該通孔內分別電鍍形成一第三及第四金屬層以及一導電通孔;(e)移除該第一及第二阻層;(f)於該第三金屬層之第一打線區以及晶片置放區上形成一第三阻層;(g)進行蝕刻,以移除為第一、第二阻層所覆蓋之導電晶種層、該第一及第二金屬,以形成第一及第二線路層;(h)去除該第三阻層;(i)於該第一以及第二線路層上分別形成一第一及第二介電層,於該第一及第二介電層上分別形成一第三及第四線路層,其中,該第三線路層具有一對應該晶片置放區及第一打線區而不具有任何線路之空白區,及圍繞該空白區之第二打線區,且該第二打線區具有複數第二打線墊;(j)分別於該第三線路層及該第四線路層上形成一第一及第二防焊層,並於該第一防焊層形成一開口以顯露該空白區及該第二打線區;(1)於該空白區形成一開口以暴露出該第一線路層之第一打線區以及晶片置放區;以及(m)進行蝕刻,以移除於該第一打線區以及該晶片置放區為第三阻層所覆蓋之導電晶種層及第一金屬層,以形成複數第一打線墊以及一晶片置放墊。The invention provides a method for manufacturing a heat dissipation package substrate, comprising: (a) providing a core plate having a first one and a second surface opposite to each other, and respectively providing a first surface on the first surface and the second surface The first and second metal layers are formed with a plurality of through holes penetrating the core plate and the first and second metal layers; (b) forming a full surface on the inner walls of the first and second metal layers and the through holes a conductive seed layer; (c) forming a first and a second resist layer on the conductive seed layer on the first and second metal layers, and forming a plurality of patterned openings in the first and second resist layers (d) by the conductive seed layer, respectively forming a third and fourth metal layer and a conductive via in each of the patterned opening regions and the via hole; (e) removing the first And a second resist layer; (f) forming a third resist layer on the first bonding region of the third metal layer and the wafer placement region; (g) etching to remove the first and second resist layers a conductive seed layer covered, the first and second metals to form first and second circuit layers; (h) removing the third resist layer; (i) in the first Forming a first and a second dielectric layer on the second circuit layer, and forming a third and fourth circuit layer on the first and second dielectric layers, wherein the third circuit layer has a pair of a wafer placement area and a first line area without a blank area of any line, and a second line area surrounding the blank area, and the second line area has a plurality of second line pads; (j) respectively for the third Forming a first and second solder resist layer on the circuit layer and the fourth circuit layer, and forming an opening in the first solder resist layer to expose the blank area and the second hitting area; (1) in the blank area Forming an opening to expose the first bonding region of the first wiring layer and the wafer placement region; and (m) performing etching to remove the first bonding region and the wafer placement region as a third resist layer The conductive seed layer and the first metal layer are covered to form a plurality of first wire pads and a wafer placement pad.
依上述之製法,該步驟(1)之前可更包括一步驟(k):於該第三線路層之第二打線區上形成一第四阻層,以及於步驟(m)之後可更包括一步驟(n):去除該第四阻層以顯露複數第二打線墊。According to the above method, the step (1) may further include a step (k): forming a fourth resist layer on the second wiring region of the third circuit layer, and further including a step after the step (m) Step (n): removing the fourth resist layer to expose a plurality of second wire pads.
依上述之製法,該步驟(a)可更包括:於核心板中形成一貫穿核心板之散熱通孔,且散熱通孔係對應連接至該晶片置放墊;並且步驟(i)可更包括:於第二介電層中形成一貫穿第二介電層之散熱盲孔,且散熱盲孔係對應連接至散熱通孔。According to the above method, the step (a) may further include: forming a heat dissipation through hole in the core plate through the core plate, and the heat dissipation through hole is correspondingly connected to the wafer placement pad; and the step (i) may further include A heat dissipation blind hole penetrating through the second dielectric layer is formed in the second dielectric layer, and the heat dissipation blind hole is correspondingly connected to the heat dissipation through hole.
依上述之製法,該第一及第二金屬層可為銅箔層。According to the above method, the first and second metal layers may be a copper foil layer.
依上述之製法,該步驟(n)後可更包括一步驟(o):形成一金屬保護層於第一打線墊、第二打線墊、以及晶片置放墊上。According to the above method, the step (n) may further comprise a step (o) of forming a metal protective layer on the first bonding pad, the second bonding pad, and the wafer placing pad.
本發明更提出一種散熱封裝基板,係包括:一核心板,係具有相對之第一表面及第二表面;一第一線路層,係設於該第一表面上;一第二線路層,係設於該第二表面上,且該第二線路層具有一晶片置放墊;一第一介電層,係設於第一線路層上,其中,該核心板及該第一介電層各具有一尺寸相同且相連接之開口,以顯露該晶片置放墊;一第三線路層,係設於該第一介電層上,並具有複數圍繞該開口之第二打線墊;一第二介電層,係設於該第二線路層上;以及一第四線路層,係設於該第二介電層上。The present invention further provides a heat dissipation package substrate, comprising: a core plate having opposite first and second surfaces; a first circuit layer disposed on the first surface; and a second circuit layer On the second surface, the second circuit layer has a wafer placement pad; a first dielectric layer is disposed on the first circuit layer, wherein the core plate and the first dielectric layer are respectively Having the same size and connected openings to expose the wafer placement pad; a third circuit layer disposed on the first dielectric layer and having a plurality of second wire pads surrounding the opening; a dielectric layer is disposed on the second circuit layer; and a fourth circuit layer is disposed on the second dielectric layer.
上述之散熱封裝基板中,可更包括圍繞該晶片置放墊周緣之複數第一打線墊,且該開口並顯露該些第一打線墊。The heat dissipation package substrate may further include a plurality of first wire pads surrounding the periphery of the wafer, and the openings and the first wire pads are exposed.
上述之散熱封裝基板中,第二介電層更具有一貫穿該第二介電層之散熱盲孔,且該散熱盲孔係對應連接至該晶片置放墊。In the above heat dissipation package substrate, the second dielectric layer further has a heat dissipation blind hole penetrating the second dielectric layer, and the heat dissipation blind hole is correspondingly connected to the wafer placement pad.
上述之散熱封裝基板中,更包括金屬保護層,係設於該第一打線墊、該第二打線墊、以及該晶片置放墊上。The heat dissipation package substrate further includes a metal protection layer disposed on the first wire bonding pad, the second wire bonding pad, and the wafer placing pad.
上述之散熱封裝基板中,更包括導電盲孔,係分別貫穿該第一介電層及該第二介電層,並電性連接該第一與第三線路層,及該第二與第四線路層。The heat dissipation package substrate further includes a conductive via hole penetrating through the first dielectric layer and the second dielectric layer, and electrically connecting the first and third circuit layers, and the second and fourth layers Line layer.
上述之散熱封裝基板中,該核心板係為一絕緣板;更包括一導電通孔,係貫穿該核心板,並電性連接該第一及第二線路層。In the above heat-dissipating package substrate, the core plate is an insulating plate, and further comprises a conductive through hole extending through the core plate and electrically connecting the first and second circuit layers.
本發明再提供一種散熱封裝基板之製法,係包括:(a)提供一核心板,該核心板具有相對之一第一及第二表面,且於該第一及第二表面之上分別設有一第一及第二金屬層,並形成有貫穿該核心板及第一及第二金屬層之複數通孔;(b)於該第一及第二金屬層及通孔之內壁上全面形成一導電晶種層;(c)於該第一及第二金屬層上之導電晶種層上分別形成一第一及第二阻層,並於該第一及第二阻層形成複數圖案化開口區;(d)藉由該導電晶種層,於各該圖案化開口區及該通孔內分別電鍍形成一第三及第四金屬層以及一導電通孔,其中,該第四金屬層具有一晶片置放區以及圍繞該置放區之第一打線區;(e)移除該第一及第二阻層;(f)於該第四金屬層之第一打線區以及晶片置放區上形成一第三阻層;(g)進行蝕刻,以移除為第一、第二阻層所覆蓋之該導電晶種層、該第一及第二金屬,以形成第一及第二線路層;(h)去除該第三阻層;(i)於該第一以及第二線路層上分別形成一第一及第二介電層,於該第一及第二介電層上分別形成一第三及第四線路層,其中,該第三線路層具有一對應該晶片置放區及第一打線區而不具有任何線路之空白區,及圍繞該空白區之第二打線區,且該第二打線區具有複數第二打線墊;(j)分別於該第三線路層及該第四線路層上形成一第一及第二防焊層,並於該第一防焊層形成一開口以顯露該空白區及該第二打線區;(l)於該空白區形成一貫穿該第一介電層及該核心板之開口以暴露出該第二線路層之第一打線區以及晶片置放區;以及(m)進行蝕刻,以移除於該第一打線區以及該晶片置放區之該第二金屬層以及導電晶種層,以形成複數第一打線墊以及一晶片置放墊。The invention further provides a method for manufacturing a heat dissipation package substrate, comprising: (a) providing a core plate having a first one and a second surface opposite to each other, and respectively providing a first surface on the first surface and the second surface The first and second metal layers are formed with a plurality of through holes penetrating the core plate and the first and second metal layers; (b) forming a full surface on the inner walls of the first and second metal layers and the through holes a conductive seed layer; (c) forming a first and a second resist layer on the conductive seed layer on the first and second metal layers, and forming a plurality of patterned openings in the first and second resist layers And (d) forming a third and fourth metal layer and a conductive via hole respectively in each of the patterned opening region and the via hole by the conductive seed layer, wherein the fourth metal layer has a wafer placement area and a first bonding area surrounding the placement area; (e) removing the first and second resist layers; (f) a first bonding area of the fourth metal layer and a wafer placement area Forming a third resist layer thereon; (g) performing etching to remove the conductive seed layer covered by the first and second resist layers, the first a second metal to form the first and second circuit layers; (h) removing the third resist layer; (i) forming a first and a second dielectric layer on the first and second circuit layers, respectively Forming a third and fourth circuit layers on the first and second dielectric layers, wherein the third circuit layer has a pair of blank areas corresponding to the wafer placement area and the first wiring area without any lines. And a second wire bonding area surrounding the blank area, wherein the second wire bonding zone has a plurality of second wire bonding pads; (j) forming a first and second soldering prevention on the third circuit layer and the fourth circuit layer respectively And forming an opening in the first solder resist layer to expose the blank region and the second bonding region; (1) forming an opening through the first dielectric layer and the core plate to expose the blank region a first bonding region of the second wiring layer and a wafer placement region; and (m) etching to remove the second metal layer and the conductive seed layer in the first bonding region and the wafer placement region, To form a plurality of first wire pads and a wafer placement pad.
依上述之製法,該步驟(l)之前可更包括一步驟(k):於該第三線路層之第二打線區上形成一第四阻層,以及於步驟(m)之後可更包括一步驟(n):去除該第四阻層以顯露複數第二打線墊。According to the above method, the step (1) may further include a step (k): forming a fourth resist layer on the second wiring region of the third circuit layer, and further including a step after the step (m) Step (n): removing the fourth resist layer to expose a plurality of second wire pads.
依上述之製法,其中,該步驟(a)可更包括:於該第二介電層中形成一貫穿該第二介電層之散熱盲孔,且該散熱盲孔係對應連接至該晶片置放墊。According to the above method, the step (a) may further include: forming a heat dissipation blind via the second dielectric layer in the second dielectric layer, and the heat dissipation blind via is correspondingly connected to the wafer Place the mat.
依上述之製法,該第一及第二金屬層可為銅箔層。According to the above method, the first and second metal layers may be a copper foil layer.
依上述之製法,其中,該步驟(n)後可更包括一步驟(o):形成一金屬保護層於該第一打線墊、該第二打線墊、以及該晶片置放墊上。According to the above method, the step (n) may further comprise a step (o) of forming a metal protective layer on the first bonding pad, the second bonding pad, and the wafer placing pad.
本發明之散熱封裝基板及其製法,係可使電子元件同時打線連接至多層線路層,相較於習知僅可打線至單層線路層之封裝基板,本發明之散熱封裝基板可使電子元件打線之密度大幅地提升。此外,散熱通孔以及散熱盲孔的設置,亦有效地將基板內部的熱傳導出去,因此能達到高效率的散熱效果。再者,相較於習知雙核心板之封裝基板,本發明之散熱封裝基板由於僅具有單一核心板,因此可大幅降低封裝基板之尺寸,進而達到封裝基板結構整體微小化之需求。而打線墊上所形成之金屬保護層更提供打線墊一保護功能,使封裝基板整體之信賴性得以提高。此外,本發明之介電層的導電盲孔以及核心板的導電通孔的設置,取代了習知技術中表面積大之貫穿封裝基板整體之導電通孔。因此,本發明之散熱封裝基板可更容易達成微型化之目標。The heat-dissipating package substrate of the present invention and the method for manufacturing the same can be used for simultaneously connecting the electronic components to the multi-layer circuit layer. Compared with the package substrate which can only be wired to the single-layer circuit layer, the heat-dissipating package substrate of the present invention can make the electronic components The density of the wire is greatly increased. In addition, the arrangement of the heat dissipation through holes and the heat dissipation blind holes also effectively conducts heat inside the substrate, thereby achieving a highly efficient heat dissipation effect. Furthermore, compared with the package substrate of the conventional dual core board, the heat dissipation package substrate of the present invention has only a single core board, so that the size of the package substrate can be greatly reduced, thereby achieving the requirement of miniaturization of the package substrate structure. The metal protection layer formed on the wire pad further provides a wire pad protection function, so that the overall reliability of the package substrate is improved. In addition, the conductive via holes of the dielectric layer of the present invention and the conductive vias of the core plate are arranged to replace the conductive vias of the entire package substrate which have a large surface area in the prior art. Therefore, the heat dissipation package substrate of the present invention can more easily achieve the goal of miniaturization.
以下係藉由特定的具體實例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.
請參閱圖2A至2L,其係顯示本發明一較佳實施例之散熱封裝基板及其製法之剖面示意圖。該散熱封裝基板可使晶片同時打線至內部與外部線路層(第一線路層以及第三線路層),使達到有效提升線路密度之效果。2A to 2L are schematic cross-sectional views showing a heat dissipation package substrate and a method of fabricating the same according to a preferred embodiment of the present invention. The heat-dissipating package substrate enables the wafer to be simultaneously wired to the inner and outer circuit layers (the first circuit layer and the third circuit layer), so as to effectively increase the line density.
如圖2A,首先(a)提供一核心板20,該核心板20具有相對之一第一及第二表面20a,20b,且於該第一及第二表面20a,20b之上分別設有一第一及第二金屬層21a,21b,並形成有貫穿該核心板20及第一及第二金屬層21a,21b之複數通孔20c。接著,(b)於該第一及第二金屬層21a,21b及通孔20c之內壁上全面形成一導電晶種層22。在本實施例中,其第一及第二金屬層21a,21b為銅箔層。As shown in FIG. 2A, (a) firstly, a core board 20 is provided. The core board 20 has a first and second surface 20a, 20b opposite to each other, and a first surface is provided on the first and second surfaces 20a, 20b. The first and second metal layers 21a, 21b are formed with a plurality of through holes 20c penetrating the core plate 20 and the first and second metal layers 21a, 21b. Next, (b) a conductive seed layer 22 is formed on the inner walls of the first and second metal layers 21a, 21b and the through holes 20c. In this embodiment, the first and second metal layers 21a, 21b are copper foil layers.
接著,如圖2B,(c)於第一及第二金屬層21a,21b上之導電晶種層22上分別形成一第一及第二阻層23,23’,並於第一及第二阻層23,23’形成複數圖案化開口區230,230’。Next, as shown in FIG. 2B, (c) forming first and second resist layers 23, 23' on the conductive seed layer 22 on the first and second metal layers 21a, 21b, respectively, and in the first and second The resist layers 23, 23' form a plurality of patterned opening regions 230, 230'.
如圖2C,(d)藉由導電晶種層22,於各圖案化開口區230,230’及通孔20c內分別電鍍形成一第三及第四金屬層25a’,25b’以及一導電通孔25c,並接著(e)移除第一及第二阻層23,23’。As shown in FIG. 2C, (d) a third and fourth metal layers 25a', 25b' and a conductive via 25c are respectively formed in each of the patterned opening regions 230, 230' and the via holes 20c by the conductive seed layer 22. And then (e) removing the first and second resist layers 23, 23'.
接下來,如圖2D,(f)於第三金屬層25a’之第一打線區B以及晶片置放區A上形成一第三阻層24。Next, as shown in Fig. 2D, (f) a third resist layer 24 is formed on the first wiring region B of the third metal layer 25a' and the wafer placement region A.
如圖2E,(g)進行蝕刻,以移除為第一、第二阻層23,23’所覆蓋之導電晶種層22、第一及第二金屬層21a,21b,以形成第一及第二線路層25a,25b。2E, (g) etching to remove the conductive seed layer 22, the first and second metal layers 21a, 21b covered by the first and second resist layers 23, 23' to form the first and The second circuit layers 25a, 25b.
如圖2F,(h)去除第三阻層24。As shown in FIG. 2F, (h) the third resist layer 24 is removed.
接著,如圖2G,(i)於第一以及第二線路層25a,25b上分別形成一第一及第二介電層26,28,於第一及第二介電層26,28上分別形成一第三及第四線路層27,29。其中,第三線路層27具有一對應晶片置放區A及第一打線區B而不具有任何線路之空白區D,及圍繞空白區D之第二打線區E,且第二打線區E具有複數第二打線墊271。此外,第一及第二介電層26,28更分別包括一貫穿其本身之導電盲孔272,291,並分別電性連接該第一與第三線路層25a,27,及該第二與第四線路層25b,29。Next, as shown in FIG. 2G, (i) forming first and second dielectric layers 26, 28 on the first and second circuit layers 25a, 25b, respectively, on the first and second dielectric layers 26, 28, respectively. A third and fourth circuit layers 27, 29 are formed. The third line layer 27 has a blank area D corresponding to the wafer placement area A and the first line area B without any lines, and a second line area E surrounding the blank area D, and the second line area E has A plurality of second wire mats 271. In addition, the first and second dielectric layers 26, 28 further include conductive vias 272, 291 extending through themselves, and electrically connecting the first and third circuit layers 25a, 27, and the second and fourth portions, respectively. Circuit layers 25b, 29.
如圖2H,(j)分別於第三線路層27及第四線路層29上形成一第一及第二防焊層40,42,並於第一防焊層40形成一開口400以顯露該空白區D及第二打線區E。在此,第一及第二防焊層40,42之材質為綠漆,且本步驟中此綠漆亦同時填入導電盲孔272,291中。或者導電盲孔272,291可鍍滿為實心而不需填入防焊層(圖未示)。2H, (j) forming a first and second solder resist layers 40, 42 on the third circuit layer 27 and the fourth circuit layer 29, respectively, and forming an opening 400 in the first solder resist layer 40 to reveal the Blank area D and second hitting area E. Here, the first and second solder resist layers 40, 42 are made of green paint, and in this step, the green paint is also filled into the conductive blind holes 272, 291. Alternatively, the conductive blind vias 272, 291 can be plated to be solid without the need to fill a solder mask (not shown).
如圖2I,(k)於第三線路層27之第二打線區E上形成一第四阻層24’。As shown in Fig. 2I, (k) a fourth resist layer 24' is formed on the second wiring region E of the third wiring layer 27.
如圖2J,(1)於空白區D形成一開口260以暴露出第一線路層25a之第一打線區B以及晶片置放區A。As shown in FIG. 2J, (1) an opening 260 is formed in the blank region D to expose the first bonding region B of the first wiring layer 25a and the wafer placement region A.
如圖2K,(m)進行蝕刻,以移除於第一打線區B以及晶片置放區A為第三阻層24所覆蓋之導電晶種層22及第一金屬層21a,以形成複數第一打線墊251以及一晶片置放墊252。As shown in FIG. 2K, (m) is performed to remove the conductive seed layer 22 and the first metal layer 21a covered by the third resist layer 24 in the first bonding region B and the wafer placement region A to form a plurality of A wire pad 251 and a wafer placement pad 252 are provided.
如圖2L,(n)去除第四阻層24’以顯露複數第二打線墊271。如此,則得到本實施例之散熱封裝基板2。As shown in Fig. 2L, (n) the fourth resist layer 24' is removed to expose the plurality of second bonding pads 271. Thus, the heat dissipation package substrate 2 of the present embodiment is obtained.
除此之外,如圖2M,可更於步驟(n)之後增加一步驟(o):形成一金屬保護層611,612,613於該第一打線墊251、該第二打線墊271、以及該晶片置放墊252上。如此,打線墊可受到金屬保護層的保護,而可減少第一及第二打線墊251、271因氧化而毀損的情形發生。In addition, as shown in FIG. 2M, a step (o) may be further added after the step (n): forming a metal protection layer 611, 612, 613 on the first wire pad 251, the second wire pad 271, and the wafer. Pad 252. Thus, the wire mat can be protected by the metal protective layer, and the first and second wire mats 251, 271 can be reduced due to oxidation.
圖2N係本實施例之散熱封裝基板2應用於半導體晶片封裝之例子,其中一半導體晶片81係嵌入至散熱封裝基板2內,且導線82係將半導體晶片81打線連接至第一打線墊251以及第二打線墊271;另以一封裝材料83包覆開口260、導線82、以及半導體晶片81,俾以保護半導體晶片81及導線82。2N is an example of a heat dissipating package substrate 2 of the present embodiment applied to a semiconductor chip package, wherein a semiconductor wafer 81 is embedded in the heat dissipation package substrate 2, and the wire 82 is used to wire the semiconductor wafer 81 to the first wire pad 251 and The second wire pad 271 is further covered with an opening material 260, a wire 82, and a semiconductor wafer 81 to protect the semiconductor wafer 81 and the wire 82.
另外,於本實施例中,其步驟(a)可更包括:於核心板20中形成一貫穿核心板20且對應連接至晶片置放墊252之散熱通孔25c’;且步驟(i)可更包括:於第二介電層28中形成一貫穿第二介電層28且對應連接至散熱通孔25c’之散熱盲孔292,如此所製得之散熱封裝基板2係圖2M’所示。散熱通孔25c’以及散熱盲孔292的設置更可有效地將基板內部電子元件的熱傳導出去,因此能大幅提高散熱效果。In addition, in this embodiment, the step (a) may further include: forming a heat dissipation through hole 25c' penetrating through the core plate 20 and correspondingly connected to the wafer placement pad 252 in the core board 20; and the step (i) may The method further includes: forming a heat dissipation blind hole 292 penetrating through the second dielectric layer 28 and correspondingly connected to the heat dissipation through hole 25c' in the second dielectric layer 28, and the heat dissipation package substrate 2 thus obtained is shown in FIG. 2M' . The arrangement of the heat dissipation through holes 25c' and the heat dissipation blind holes 292 can more effectively conduct heat of the electronic components inside the substrate, thereby greatly improving the heat dissipation effect.
本發明復提供一種散熱封裝基版2,如圖2L所示,係包括:一核心板20,係具有相對之第一表面20a及第二表面20b;一第一線路層25a,係設於該第一表面20a上,並具有一晶片置放墊252;一第二線路層25b,係設於該第二表面20b上;一第一介電層26,係設於該第一線路層25a上,並具有一開口260,以顯露該晶片置放墊252;一第三線路層27,係設於該第一介電層26上,並具有複數圍繞該開口260周緣之第二打線墊271;一第二介電層28,係設於該第二線路層25b上;以及一第四線路層29,係設於該第二介電層28上。The present invention further provides a heat-dissipating package substrate 2, as shown in FIG. 2L, comprising: a core board 20 having opposite first and second surfaces 20a, 20b; a first circuit layer 25a is disposed The first surface 20a has a wafer placement pad 252; a second circuit layer 25b is disposed on the second surface 20b; a first dielectric layer 26 is disposed on the first circuit layer 25a. And has an opening 260 to expose the wafer placement pad 252; a third circuit layer 27 is attached to the first dielectric layer 26, and has a plurality of second wire pads 271 around the periphery of the opening 260; A second dielectric layer 28 is disposed on the second wiring layer 25b; and a fourth wiring layer 29 is disposed on the second dielectric layer 28.
本發明之散熱封裝基版2,如圖2L所示,可更包括圍繞該晶片置放墊252周緣之複數第一打線墊251,且該開口260並顯露該些第一打線墊251。The heat-dissipating package substrate 2 of the present invention, as shown in FIG. 2L, may further include a plurality of first wire bonding pads 251 surrounding the periphery of the wafer placing pad 252, and the opening 260 exposes the first wire bonding pads 251.
如圖2M所示,本發明之散熱封裝基版2可更包括金屬保護層611,612,613,係設於該第一打線墊251、該第二打線墊271、以及該晶片置放墊252上。As shown in FIG. 2M, the heat dissipation package substrate 2 of the present invention may further include a metal protection layer 611, 612, 613 disposed on the first wire pad 251, the second wire pad 271, and the wafer placement pad 252.
此外,如圖2M’所示,本發明之散熱封裝基版2其核心板20可更具有一貫穿該核心板20之散熱通孔25c’對應連接至該晶片置放墊252,且該第二介電層28可更具有一貫穿該第二介電層28之散熱盲孔292,且該散熱盲孔292係對應連接至該散熱通孔25c’。In addition, as shown in FIG. 2M′, the core package 20 of the heat dissipation package base 2 of the present invention may further have a heat dissipation through hole 25c′ extending through the core plate 20 correspondingly connected to the wafer placement pad 252, and the second The dielectric layer 28 has a heat dissipation blind hole 292 extending through the second dielectric layer 28, and the heat dissipation blind hole 292 is correspondingly connected to the heat dissipation through hole 25c'.
如圖2M’所示,本發明之散熱封裝基版2可更包括一導電通孔25c,係貫穿該核心板20,並電性連接該第一及第二線路層25a,25b。並且,本發明之散熱封裝基版2可更包括導電盲孔272,291,係分別貫穿該第一介電層26及該第二介電層28,並電性連接該第一與第三線路層25a,27,及該第二與第四線路層25b,29。As shown in FIG. 2M', the heat dissipation package substrate 2 of the present invention further includes a conductive via 25c extending through the core board 20 and electrically connecting the first and second circuit layers 25a, 25b. Moreover, the heat-dissipating package substrate 2 of the present invention may further include conductive vias 272, 291 extending through the first dielectric layer 26 and the second dielectric layer 28, respectively, and electrically connecting the first and third circuit layers 25a. , 27, and the second and fourth circuit layers 25b, 29.
另外,本發明之散熱封裝基版2之核心板20可為一絕緣板。In addition, the core board 20 of the heat dissipation package base 2 of the present invention may be an insulation board.
本實施例之散熱封裝基板2具有複數第一打線墊251以及複數第二打線墊271,因此,可使電子元件(圖未示)同時打線連接至第一線路層25a以及第三線路層27。亦即,可有效率地增加電子元件(圖未示)打線之密度。此外,相較於習知雙核心板之封裝基板,本實施例之散熱封裝基板2由於僅具有單一核心板20,因此可大幅降低封裝基板之尺寸,進而達到封裝基板結構整體微小化之需求。The heat dissipation package substrate 2 of the present embodiment has a plurality of first wire pads 251 and a plurality of second wire pads 271. Therefore, electronic components (not shown) can be wire-bonded to the first circuit layer 25a and the third circuit layer 27 at the same time. That is, the density of the wires of the electronic component (not shown) can be efficiently increased. In addition, since the heat dissipation package substrate 2 of the present embodiment has only a single core board 20 compared to the package substrate of the conventional dual core board, the size of the package substrate can be greatly reduced, thereby achieving the miniaturization of the package substrate structure.
圖3A至3L係本發明另一較佳實施例之散熱封裝基板之製作流程圖。3A to 3L are flowcharts showing the fabrication of a heat dissipation package substrate according to another preferred embodiment of the present invention.
如圖3A,首先(a)提供一核心板30,該核心板30具有相對之一第一及第二表面30a,30b,且於第一及第二表面30a,30b之上分別設有一第一及第二金屬層31a,31b,並形成有貫穿該核心板30及第一及第二金屬層31a,31b之複數通孔30c;(b)於第一及第二金屬層31a,31b及通孔30c之內壁上全面形成一導電晶種層32。在本實施例中,其第一及第二金屬層31a,31b係為銅箔層。As shown in FIG. 3A, (a) firstly, a core board 30 is provided. The core board 30 has a first and second surfaces 30a, 30b opposite to each other, and a first surface is respectively disposed on the first and second surfaces 30a, 30b. And the second metal layers 31a, 31b are formed with a plurality of through holes 30c penetrating the core plate 30 and the first and second metal layers 31a, 31b; (b) the first and second metal layers 31a, 31b and A conductive seed layer 32 is formed on the inner wall of the hole 30c. In the present embodiment, the first and second metal layers 31a, 31b are copper foil layers.
如圖3B,(c)於第一及第二金屬層31a,31b上之導電晶種層32上分別形成一第一及第二阻層33,33’,並於第一及第二阻層33,33’形成複數圖案化開口區330,330’。As shown in FIG. 3B, (c) forming first and second resist layers 33, 33' on the conductive seed layer 32 on the first and second metal layers 31a, 31b, respectively, and the first and second resist layers. 33, 33' form a plurality of patterned open areas 330, 330'.
如圖3C,(d)藉由導電晶種層32,於各圖案化開口區330,330’及通孔30c內分別電鍍形成一第三及第四金屬層35a’,35b’以及一導電通孔35c,其中,第四金屬層35b’具有一晶片置放區A以及圍繞該置放區A之第一打線區B。As shown in FIG. 3C, (d) a third and fourth metal layers 35a', 35b' and a conductive via 35c are respectively formed in each of the patterned opening regions 330, 330' and the via holes 30c by the conductive seed layer 32. The fourth metal layer 35b' has a wafer placement area A and a first bonding area B surrounding the placement area A.
如圖3D,(e)移除該第一及第二阻層33,33’。As shown in Fig. 3D, (e) the first and second resist layers 33, 33' are removed.
如圖3E,(f)於第四金屬層35b’之第一打線區B以及晶片置放區A上形成一第三阻層34。As shown in Fig. 3E, (f) a third resist layer 34 is formed on the first bonding region B of the fourth metal layer 35b' and the wafer placement region A.
如圖3E,(g)進行蝕刻,以移除為第一、第二阻層33,33’所覆蓋之該導電晶種層32、該第一及第二金屬31a,31b,以形成第一及第二線路層35a,35b。並接著,如圖3F,(h)去除該第三阻層34。3E, (g) etching to remove the conductive seed layer 32, the first and second metals 31a, 31b covered by the first and second resist layers 33, 33' to form a first And second circuit layers 35a, 35b. And then, as shown in FIG. 3F, (h), the third resist layer 34 is removed.
如圖3G,(i)於第一以及第二線路層35a,35b上分別形成一第一及第二介電層36,38,於該第一及第二介電層36,38上分別形成一第三及第四線路層37,39,其中,第三線路層37具有一對應晶片置放區A及第一打線區B而不具有任何線路之空白區D,及圍繞該空白區D之第二打線區E,且第二打線區E具有複數第二打線墊371;於第二介電層38中形成一貫穿第二介電層38且對應連接至該晶片置放區A之散熱盲孔392。此外,第一及第二介電層36,38更分別包括一貫穿其本身之導電盲孔372,391,並電性連接該第一與第三線路層35a,37,及該第二與第四線路層35b,39。As shown in FIG. 3G, (i) forming first and second dielectric layers 36, 38 on the first and second circuit layers 35a, 35b, respectively, forming the first and second dielectric layers 36, 38, respectively. a third and fourth circuit layer 37, 39, wherein the third circuit layer 37 has a blank area D corresponding to the wafer placement area A and the first wiring area B without any lines, and surrounding the blank area D a second bonding area E, and the second bonding area E has a plurality of second bonding pads 371; forming a heat dissipation blind through the second dielectric layer 38 and correspondingly connected to the wafer placement area A in the second dielectric layer 38 Hole 392. In addition, the first and second dielectric layers 36, 38 further include a conductive via 372, 391 extending through itself, and electrically connecting the first and third circuit layers 35a, 37, and the second and fourth lines. Layers 35b, 39.
如圖3H,(j)分別於該第三線路層37及該第四線路層39上形成一第一及第二防焊層50,52,並於該第一防焊層50形成一開口500以顯露該空白區D及該第二打線區E。在此,第一及第二防焊層50,52之材質為綠漆,且此綠漆亦同時填入導電盲孔372,391中。或者導電盲孔372,391可鍍滿為實心而不需填入防焊層(圖未示)。As shown in FIG. 3H, (j) forming a first and second solder resist layers 50, 52 on the third circuit layer 37 and the fourth circuit layer 39, respectively, and forming an opening 500 in the first solder resist layer 50. The blank area D and the second line area E are exposed. Here, the first and second solder resist layers 50, 52 are made of green paint, and the green paint is also filled into the conductive blind holes 372, 391 at the same time. Alternatively, the conductive blind vias 372, 391 can be plated to be solid without the need to fill a solder mask (not shown).
如圖3I,(k)於該第三線路層37之第二打線區E上形成一第四阻層34’。As shown in FIG. 3I, (k) a fourth resist layer 34' is formed on the second wiring region E of the third wiring layer 37.
如圖3J,(1)於該空白區D形成一貫穿該第一介電層36及該核心板30之開口360及300以暴露出該第二線路層35b之第一打線區B以及晶片置放區A。As shown in FIG. 3J, (1) forming a first wiring region B and a wafer through the openings 360 and 300 of the first dielectric layer 36 and the core plate 30 to expose the second wiring layer 35b. Put area A.
如圖3K,(m)進行蝕刻,以移除於該第一打線區B以及該晶片置放區A之該第二金屬層31b以及導電晶種層32,以形成複數第一打線墊351以及一晶片置放墊352。3K, (m) etching to remove the second metal layer 31b and the conductive seed layer 32 in the first bonding region B and the wafer placement region A to form a plurality of first bonding pads 351 and A wafer is placed on the pad 352.
如圖3L,(n)去除該第四阻層34’以顯露複數第二打線墊371。如此,則得到本實施例之散熱封裝基板3。As shown in Fig. 3L, (n) the fourth resist layer 34' is removed to expose a plurality of second bonding pads 371. Thus, the heat dissipation package substrate 3 of the present embodiment is obtained.
除此之外,如圖3M,可更於步驟(n)之後增加一步驟(o):形成一金屬保護層711,712,713於第一打線墊351、第二打線墊371、以及晶片置放墊352上。如此,打線墊可受到金屬保護層的保護,而可減少第一及第二打線墊351、371因氧化而毀損的情形發生。In addition, as shown in FIG. 3M, a step (o) may be further added after the step (n): forming a metal protective layer 711, 712, 713 on the first bonding pad 351, the second bonding pad 371, and the wafer placing pad 352. . Thus, the wire mat can be protected by the metal protective layer, and the first and second wire mats 351, 371 can be reduced from being damaged by oxidation.
圖3N係本實施例之散熱封裝基板3應用於半導體晶片封裝之例子,其中一半導體晶片81係嵌入至基板內,且導線82係將半導體晶片81打線連接至第一打線墊351以及第二打線墊371;另以一封裝材料83包覆開口360,300、導線82、以及半導體晶片81,俾以保護該半導體晶片81及導線82。3N is an example of a heat dissipation package substrate 3 of the present embodiment applied to a semiconductor chip package in which a semiconductor wafer 81 is embedded in a substrate, and the wire 82 is used to wire the semiconductor wafer 81 to the first wire pad 351 and the second wire. The pad 371 is further covered with an opening material 360, 300, a wire 82, and a semiconductor wafer 81 to protect the semiconductor wafer 81 and the wire 82.
另外,於本實施例中,其步驟(i)中形成之散熱盲孔可為一個以上,如圖3M’中之所示之第二介電層38係具有2個散熱盲孔392,以更增加散熱效率。In addition, in this embodiment, the heat dissipation blind holes formed in the step (i) may be more than one, and the second dielectric layer 38 shown in FIG. 3M′ has two heat dissipation blind holes 392 to further Increase heat dissipation efficiency.
除此之外,本實施例中第二介電層38亦可為不具有散熱盲孔,如圖3M”所示。由於介電層本身厚度不大,因此可具有基本的散熱效果,而省去製作散熱盲孔之步驟,則可減少一些製作時間。In addition, in this embodiment, the second dielectric layer 38 may also have no heat dissipation blind holes, as shown in FIG. 3M". Since the dielectric layer itself is not thick, it can have a basic heat dissipation effect, and saves The step of making a thermal blind via can reduce some production time.
本發明復提供一種散熱封裝基板3,如圖3L所示,係包括:一核心板30,係具有相對之第一表面30a及第二表面30b;一第一線路層35a,係設於該第一表面30a上;一第二線路層35b,係設於該第二表面30b上,且該第二線路層35b具有一晶片置放墊352;一第一介電層36,係設於該第一線路層35a上,其中,該核心板30及該第一介電層36各具有一尺寸相同且相連接之開口300,360,以顯露該晶片置放墊352;一第三線路層37,係設於該第一介電層36上,並具有複數圍繞該開口360之第二打線墊371;一第二介電層38,係設於該第二線路層35b上;以及一第四線路層39,係設於該第二介電層38上。The present invention further provides a heat dissipating package substrate 3, as shown in FIG. 3L, comprising: a core plate 30 having a first surface 30a and a second surface 30b opposite thereto; and a first circuit layer 35a disposed on the first a second circuit layer 35b is disposed on the second surface 30b, and the second circuit layer 35b has a wafer placement pad 352; a first dielectric layer 36 is disposed on the surface a circuit layer 35a, wherein the core board 30 and the first dielectric layer 36 each have a same size and connected openings 300, 360 to expose the wafer placement pad 352; a third circuit layer 37, On the first dielectric layer 36, and having a plurality of second bonding pads 371 surrounding the opening 360; a second dielectric layer 38 is disposed on the second wiring layer 35b; and a fourth wiring layer 39 And is disposed on the second dielectric layer 38.
如圖3L所示,本發明之散熱封裝基版3,可更包括圍繞該晶片置放墊352周緣之複數第一打線墊351,且該些開口300,360並顯露該些第一打線墊351。As shown in FIG. 3L, the heat-dissipating package substrate 3 of the present invention may further include a plurality of first wire bonding pads 351 surrounding the periphery of the wafer placing pad 352, and the openings 300, 360 expose the first wire bonding pads 351.
本發明之散熱封裝基版3,如圖3L所示,其中該第二介電層38可更具有一貫穿該第二介電層38之散熱盲孔292,且該散熱盲孔292係對應連接至該晶片置放墊352。The heat dissipation package substrate 3 of the present invention, as shown in FIG. 3L, wherein the second dielectric layer 38 further has a heat dissipation blind hole 292 penetrating the second dielectric layer 38, and the heat dissipation blind hole 292 is connected. The pad 352 is placed on the wafer.
本發明之散熱封裝基版3,如圖3M所示,可更包括金屬保護層711,712,713,係設於該第一打線墊351、該第二打線墊371、以及該晶片置放墊352上。The heat-dissipating package substrate 3 of the present invention, as shown in FIG. 3M, may further include metal protective layers 711, 712, 713 disposed on the first bonding pad 351, the second bonding pad 371, and the wafer placing pad 352.
本發明之散熱封裝基版3,如圖3M所示,可更包括一導電通孔35c,係貫穿該核心板30,並電性連接該第一及第二線路層35a,35b。並且,本發明之散熱封裝基版3,可更包括導電盲孔372,391,係分別貫穿該第一介電層36及該第二介電層38,並電性連接該第一與第三線路層35a,37,及該第二與第四線路層35b,39。The heat-dissipating package substrate 3 of the present invention, as shown in FIG. 3M, may further include a conductive via 35c extending through the core board 30 and electrically connecting the first and second circuit layers 35a, 35b. The heat-dissipating package substrate 3 of the present invention may further include conductive vias 372, 391 extending through the first dielectric layer 36 and the second dielectric layer 38, respectively, and electrically connecting the first and third circuit layers. 35a, 37, and the second and fourth circuit layers 35b, 39.
另外,本發明之散熱封裝基板3之核心板30可為一絕緣板。In addition, the core board 30 of the heat dissipation package substrate 3 of the present invention may be an insulation board.
綜上所述,本發明之散熱封裝基板及其製法,係可使電子元件同時打線連接至多層線路層,相較於習知僅可打線至單層線路層之封裝基板,本發明之散熱封裝基板可使電子元件打線之密度大幅地提升。此外,散熱通孔以及散熱盲孔的設置,亦有效地將基板內部的熱傳導出去,因此能達到高效率的散熱效果。再者,相較於習知雙核心板之封裝基板,本發明之散熱封裝基板由於僅具有單一核心板,因此可大幅降低封裝基板之尺寸,進而達到封裝基板結構整體微小化之需求。而打線墊上所形成之金屬保護層更提供打線墊一保護功能,使封裝基板整體之信賴性得以提高。In summary, the heat-dissipating package substrate of the present invention and the method for manufacturing the same can be used for simultaneously connecting the electronic components to the multi-layer circuit layer, and the heat-dissipating package of the present invention is compared with the package substrate which can only be wired to the single-layer circuit layer. The substrate can greatly increase the density of the electronic components. In addition, the arrangement of the heat dissipation through holes and the heat dissipation blind holes also effectively conducts heat inside the substrate, thereby achieving a highly efficient heat dissipation effect. Furthermore, compared with the package substrate of the conventional dual core board, the heat dissipation package substrate of the present invention has only a single core board, so that the size of the package substrate can be greatly reduced, thereby achieving the requirement of miniaturization of the package substrate structure. The metal protection layer formed on the wire pad further provides a wire pad protection function, so that the overall reliability of the package substrate is improved.
此外,本發明之介電層的導電盲孔以及核心板的導電通孔的設置,取代了習知技術中表面積大之貫穿封裝基板整體之導電通孔。因此,本發明之散熱封裝基板可更容易達成微型化之目標。In addition, the conductive via holes of the dielectric layer of the present invention and the conductive vias of the core plate are arranged to replace the conductive vias of the entire package substrate which have a large surface area in the prior art. Therefore, the heat dissipation package substrate of the present invention can more easily achieve the goal of miniaturization.
上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.
1...封裝基板1. . . Package substrate
100,120,140...開口100,120,140. . . Opening
10,11...核心板10,11. . . Core board
12...介電層12. . . Dielectric layer
13...導電通孔13. . . Conductive through hole
14,15...防焊層14,15. . . Solder mask
150...開孔150. . . Opening
16...電性接觸墊16. . . Electrical contact pad
17,81...半導體晶片17,81. . . Semiconductor wafer
18,82...導線18,82. . . wire
19,83...封裝材料19,83. . . Packaging material
2,3...散熱封裝基板2,3. . . Heat dissipation package substrate
20,30...核心板20,30. . . Core board
20a,30a...第一表面20a, 30a. . . First surface
20b,30b...第二表面20b, 30b. . . Second surface
20c,30c...通孔20c, 30c. . . Through hole
21a,31a...第二金屬層21a, 31a. . . Second metal layer
21b,31b...第一金屬層21b, 31b. . . First metal layer
22,32...導電晶種層22,32. . . Conductive seed layer
23,33...第一阻層23,33. . . First resistive layer
23',33'...第二阻層23', 33'. . . Second resistive layer
230,230’,330,330’...圖案化開口區230,230',330,330’. . . Patterned open area
24,34...第三阻層24,34. . . Third resistive layer
24',34'...第四阻層24', 34'. . . Fourth resistive layer
25a,35a...第一線路層25a, 35a. . . First circuit layer
25b,35b...第二線路層25b, 35b. . . Second circuit layer
25a',35a'...第三金屬層25a', 35a'. . . Third metal layer
25b',35b'...第四金屬層25b', 35b'. . . Fourth metal layer
25c,35c...導電通孔25c, 35c. . . Conductive through hole
25c'...散熱通孔25c'. . . Thermal through hole
251,351...第一打線墊251,351. . . First line mat
252,352...晶片置放墊252,352. . . Wafer placement pad
26,36...第一介電層26,36. . . First dielectric layer
28,38...第二介電層28,38. . . Second dielectric layer
27,37...第三線路層27,37. . . Third circuit layer
271,371...第二打線墊271,371. . . Second line mat
29,39...第四線路層29,39. . . Fourth circuit layer
272,291,372,391...導電盲孔272,291,372,391. . . Conductive blind hole
292,392...散熱盲孔292,392. . . Thermal blind hole
40,50...第一防焊層40,50. . . First solder mask
260,400,360,300,500...開口260,400,360,300,500. . . Opening
42,52...第二防焊層42,52. . . Second solder mask
611,612,613...金屬保護層611,612,613. . . Metal protective layer
711,712,713...金屬保護層711,712,713. . . Metal protective layer
A...晶片置放區A. . . Wafer placement area
B...第一打線區B. . . First hit area
D...空白區D. . . Blank area
E...第二打線區E. . . Second line zone
圖1A-1D係習知一空腔區朝上打線式封裝基板之製作流程圖以及其應用。1A-1D are flow diagrams showing the fabrication of a cavity-up line-up package substrate and its application.
圖2A-2N係本發明一較佳實施例之散熱封裝基板及其製法之剖面示意圖。2A-2N are cross-sectional views showing a heat dissipation package substrate and a method of fabricating the same according to a preferred embodiment of the present invention.
圖3A-3M”係本發明一較佳實施例之散熱封裝基板及其製法之剖面示意圖。3A-3M are schematic cross-sectional views showing a heat dissipation package substrate and a method of manufacturing the same according to a preferred embodiment of the present invention.
2...散熱封裝基板2. . . Heat dissipation package substrate
20...核心板20. . . Core board
20a...第一表面20a. . . First surface
20b...第二表面20b. . . Second surface
25a...第一線路層25a. . . First circuit layer
25b...第二線路層25b. . . Second circuit layer
25c...導電通孔25c. . . Conductive through hole
251...第一打線墊251. . . First line mat
252...晶片置放墊252. . . Wafer placement pad
26...第一介電層26. . . First dielectric layer
260...開口260. . . Opening
27...第三線路層27. . . Third circuit layer
271...第二打線墊271. . . Second line mat
28...第二介電層28. . . Second dielectric layer
29...第四線路層29. . . Fourth circuit layer
272,291...導電盲孔272,291. . . Conductive blind hole
40...第一防焊層40. . . First solder mask
42...第二防焊層42. . . Second solder mask
Claims (24)
Priority Applications (1)
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TW97144245A TWI400782B (en) | 2008-11-14 | 2008-11-14 | Packaging substrate with heat-dissipation capability and the manufacturing method thereof |
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TW97144245A TWI400782B (en) | 2008-11-14 | 2008-11-14 | Packaging substrate with heat-dissipation capability and the manufacturing method thereof |
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TW201019432A TW201019432A (en) | 2010-05-16 |
TWI400782B true TWI400782B (en) | 2013-07-01 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW457836B (en) * | 1999-06-09 | 2001-10-01 | Phoenix Prec Technology Corp | High heat dissipation type integrated circuit substrate structure and fabrication process |
TWI237372B (en) * | 2004-06-29 | 2005-08-01 | Advanced Semiconductor Eng | Leadframe for multi-chip package and method for manufacturing the same |
TWI240387B (en) * | 2004-10-28 | 2005-09-21 | Phoenix Prec Technology Corp | Method for fabricating thermally enhanced semiconductor package substrate |
TWI247572B (en) * | 2001-03-22 | 2006-01-11 | Phoenix Prec Technology Corp | Chip-packaging substrate process for heat sink sheet with supporting effect |
TWI264806B (en) * | 2001-07-10 | 2006-10-21 | Phoenix Prec Technology Corp | Structure of connecting substrate of IC packaged substrate |
TWI271874B (en) * | 2005-08-25 | 2007-01-21 | Phoenix Prec Technology Corp | Circuit board structure of semiconductor package and method for fabricating the same |
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2008
- 2008-11-14 TW TW97144245A patent/TWI400782B/en active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW457836B (en) * | 1999-06-09 | 2001-10-01 | Phoenix Prec Technology Corp | High heat dissipation type integrated circuit substrate structure and fabrication process |
TWI247572B (en) * | 2001-03-22 | 2006-01-11 | Phoenix Prec Technology Corp | Chip-packaging substrate process for heat sink sheet with supporting effect |
TWI264806B (en) * | 2001-07-10 | 2006-10-21 | Phoenix Prec Technology Corp | Structure of connecting substrate of IC packaged substrate |
TWI237372B (en) * | 2004-06-29 | 2005-08-01 | Advanced Semiconductor Eng | Leadframe for multi-chip package and method for manufacturing the same |
TWI240387B (en) * | 2004-10-28 | 2005-09-21 | Phoenix Prec Technology Corp | Method for fabricating thermally enhanced semiconductor package substrate |
TWI271874B (en) * | 2005-08-25 | 2007-01-21 | Phoenix Prec Technology Corp | Circuit board structure of semiconductor package and method for fabricating the same |
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