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TWI398933B - 積體電路元件之封裝結構及其製造方法 - Google Patents

積體電路元件之封裝結構及其製造方法 Download PDF

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TWI398933B
TWI398933B TW097107608A TW97107608A TWI398933B TW I398933 B TWI398933 B TW I398933B TW 097107608 A TW097107608 A TW 097107608A TW 97107608 A TW97107608 A TW 97107608A TW I398933 B TWI398933 B TW I398933B
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integrated circuit
circuit component
package structure
copper foil
bonding
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TW097107608A
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TW200939409A (en
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Shih Hsiung Chan
Shen Bo Lin
Pin Chuan Chen
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Advanced Optoelectronic Tech
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Priority to TW097107608A priority Critical patent/TWI398933B/zh
Priority to US12/396,898 priority patent/US7863717B2/en
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Microelectronics & Electronic Packaging (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

積體電路元件之封裝結構及其製造方法
本發明係關於一種積體電路元件之封裝結構及其製造方法，尤係關於一種積體電路元件之薄型化封裝結構及其製造方法。
隨著消費性電子產品的需求趨勢，再加上節能與環保等發展方向，輕、薄、短、小的產品已蔚為趨勢，也因此促使積體電路的封裝結構往薄型化發展。習知積體電路封裝多採用陶瓷基板，雖然陶瓷基板有良好的耐熱程度，但熱傳導與散熱性質則相對的差。此外，為了使陶瓷基板維持其適當的應力與堅硬度，因此無法降低基板厚度，一般的陶瓷基板厚度約限於1~3mm，此情形於封裝結構薄型化的發展上係為一大阻礙。
有鑑於此，仍有必要開發新的封裝結構與製程，以達到封裝結構薄型化之目標，並改善散熱不佳之問題，降低生產成本，以符合市場需求。
本發明提供一種積體電路元件之封裝結構及其製造方法，並 利用一銅箔基板取代陶瓷基板以達到封裝結構更加薄型化之目的，且藉由銅箔基板的性質改善傳統陶瓷基板散熱不佳的問題。
本發明提供一種積體電路元件之封裝結構，其包含一銅箔基板、一積體電路元件、複數個金屬導線及一封膠材料。上述之銅箔基板包含一IC接合區、複數個導電區及一種絕緣介電材料。其中，積體電路元件係固定於IC接合區之表面，並藉由金屬導線連接積體電路元件與複數個導電區的電性，而絕緣介電材料則介於IC接合區與導電區之間及兩相鄰導電區之間。此外，封膠材料係覆蓋於IC接合區、複數個導電區及積體電路元件上。
本發明所提供之銅箔基板其厚度約可降至20~50μm。
100‧‧‧銅箔基板
110‧‧‧銅箔板
112‧‧‧IC接合區
114‧‧‧導電區
116‧‧‧溝槽
120‧‧‧絕緣介電材料
200‧‧‧IC封裝結構
210‧‧‧銅箔基板
212‧‧‧IC接合區
214‧‧‧導電區
217‧‧‧固件凹槽
218‧‧‧打線凹槽
220‧‧‧絕緣介電材料
230‧‧‧積體電路元件
240‧‧‧金屬導線
250‧‧‧黏結材料
260‧‧‧封膠材料
270‧‧‧凸塊
280‧‧‧絕緣材料層
290‧‧‧金屬層
第一A~C圖係為根據本發明之第一實施例所建構之銅箔基板的製程示意圖；第二A圖係為於本發明之第二實施例中所建構的一種積體電路元件之封裝結構的剖面示意圖；第二B圖係為第二A圖之IC封裝結構的上視圖；第二C圖係為根據本發明之第一較佳範例所建構的一種IC封裝結構200a的剖面示意圖；第二D圖係為根據本發明之第二較佳範例所建構的一種IC封裝結構200b的剖面示意圖； 第二E圖係為根據本發明之第三較佳範例所建構的一種IC封裝結構200c的剖面示意圖；第二F圖係為根據本發明之第四較佳範例所建構的一種IC封裝結構200d的剖面示意圖；以及第三A~D圖係為於本發明中採用電鑄製程形成固件凹槽與打線凹槽之製程示意圖。
本發明在此所探討的方向為一種積體電路元件之封裝結構及其製造方法。為了能徹底地瞭解本發明，將在下列的描述中提出詳盡的步驟及其組成。顯然地，本發明的施行並未限定於IC封裝結構之技藝者所熟習的特殊細節。另一方面，眾所周知的組成或步驟並未描述於細節中，以避免造成本發明不必要之限制。本發明的較佳實施例會詳細描述如下，然而除了這些詳細描述之外，本發明還可以廣泛地施行在其他的實施例中，且本發明的範圍不受限定，其以之後的專利範圍為準。
第一A圖~第一C圖係為根據本發明之第一實施例所建構之銅箔基板的製程示意圖。如第一A圖所示，提供一厚度為20~50μm之銅箔板110。接著，如第一B圖所示，再利用鑽孔製程、蝕刻製程或是金屬沖壓等製程於銅箔板110上形成複數個溝槽116，藉由溝槽116斷絕兩導電區114之間及導電區114與IC接合區112之間的電性導通。最後，如第一C圖所示，於溝槽116中填入絕緣介電材料120，即完成銅箔基板100之製 作。此外，上述之絕緣介電材料120係包含下列群組之一者或其組合：氧化矽(SiO)、氮化矽(SiN)、氮氧化矽(SiON)、氧化鉭(TaO)、氧化鋁(AlO)、氧化鈦(TiO)、氮化鋁(AlN)、氮化鈦(TiN)、環氧樹脂(epoxy)、矽樹脂(silicone)或高分子絕緣材料等，且藉由絕緣介電材料120的填入可增加兩導電區114之間及導電區114與IC接合區112之間的絕緣性與銅箔基板100之支撐剛性。
第二A圖係為於本發明之第二實施例中所建構的一種積體電路元件之封裝結構的剖面示意圖。首先提供一銅箔基板210，其中銅箔基板210包含一IC接合區212、複數個導電區214及一種絕緣介電材料220，絕緣介電材料220介於IC接合區212與導電區214之間及兩相鄰導電區214之間。接著，利用黏結技術將積體電路元件230固定於銅箔基板210之IC接合區212表面，亦即積體電路元件230藉由黏結材料250而固定於IC接合區212之表面。再經由金屬導線240連接積體電路元件230與銅箔基板210之導電區214的電性，如此銅箔基板210即成為積體電路元件230及金屬導線240之封裝載體。最後再利用模壓製程使封膠材料260覆蓋於積體電路元件230、金屬導線240及導電區214上，從而達到防濕氣與保護的效果。其中，上述之黏結技術係包含下列之一者：共晶黏結法、玻璃膠黏結法、高分子膠黏結法及銲接黏結法，黏結材料250係包含下列群組之一者或其組合：金矽合金、金錫合金、金鍺合金、鉛錫合金、鉛銀銦合金、玻璃、金、錫、共晶合金、高 導熱性金屬玻璃膠、銀玻璃膠、環氧樹酯或聚亞醯胺等高分子膠，封膠材料260係為環氧樹脂(epoxy)或是矽氧烷(silicone)。
第二B圖係為第二A圖之IC封裝結構上視圖。經由移除第二A圖中局部的封膠材料260，則積體電路元件230、金屬導線240及銅箔基板210之連結關係清晰可見，複數個金屬導線240分別自積體電路元件230表面向導電區214延伸並連接。
第一較佳範例：
請參考第二C圖，其係為根據本發明之第一較佳範例所建構的一種IC封裝結構200a的剖面示意圖。上述之封裝結構200a係利用覆晶(flip chip)製程將積體電路元件230藉由凸塊(bump)270固定於銅箔基板210之導電區214表面，與第二B圖不同之處在於積體電路元件230之主動面翻轉朝向銅箔基板210，並利用錫球與積體電路元件230上之焊墊相接合而成為凸塊270，經過迴焊後則凸塊270與銅箔基板210會因錫膏融熔後又固化而倒通電性，最後再利用模壓製程使封膠材料260覆蓋積體電路元件230及銅箔基板210，達到防濕氣與保護的效果。本範例之優點係為電流路徑較短與散熱效果佳，此外亦能扣除金屬導線240之線弧高度(loop height)所佔據的空間，使得封裝結構更加微小化。
第二較佳範例：
請參考第二D圖，其係為根據本發明之第二較佳範例所建構 的一種IC封裝結構200b的剖面示意圖。相較於第一實施例，本範例更能進一步減少封裝結構之厚度。首先於銅箔基板210之IC接合區212形成一固件凹槽217，並藉由黏結材料250將積體電路元件230黏著於固件凹槽217之表面，再由金屬導線240連接積體電路元件230與複數個導電區214的電性，最後將封膠材料260覆蓋積體電路元件230、金屬導線240及銅箔基板210之導電區214。其中，上述之形成一固件凹槽217的方法係為光微影蝕刻、電鑄製程或鑽孔製程。本範例之優點在於：當積體電路元件230被放置於固件凹槽217中，對於利用金屬導線240連接積體電路元件230與銅箔基板210間的電性而言，此固件凹槽217能有效降低金屬導線240的線弧高度，進而使整體封裝結構達成更加薄型化的目的。
第三較佳範例：
請參考第二E圖，其係為根據本發明之第三較佳範例所建構的一種IC封裝結構200c的剖面示意圖。相較於第二較佳範例，本範例更包含於每一個導電區214形成一打線凹槽218。上述之形成一打線凹槽218的方法係為光微影蝕刻、電鑄製程或鑽孔製程。本範例所提供之打線凹槽218降低了導電區214中金屬導線240的焊點熔接位置，相對的亦降低了金屬導線240的線弧高度，也因此使得積體電路元件230之封裝結構更加薄型化。
第四較佳範例：
請參考第二F圖，其係為根據本發明之第四較佳範例所建構的一種IC封裝結構200d的剖面示意圖。相較於第三較佳範例，本範例之形成固件凹槽217與打線凹槽218的方法，係為於銅箔基板210上形成一圖案化之絕緣材料層280，即利用光微影蝕刻於絕緣材料層280上形成固件凹槽217與打線凹槽218。如此不僅可減少封裝結構的厚度，亦可避免連接導電區214之金屬導線240與IC接合區212有不當接觸而短路。
第三A圖~第三D圖係為於本發明中採用電鑄製程形成固件凹槽217與打線凹槽218之製程示意圖。首先提供一銅箔基板210，並於銅箔基板210上形成一圖案化之絕緣材料層280，如第三B圖所示。接著，如第三C圖所示，利用電鑄製程於IC接合區212及複數個導電區214露出之表面成長一金屬層290。最後，如第三D圖所示，去除絕緣材料層280，形成固件凹槽217與複數個打線凹槽218。上述之絕緣材料層280係為光阻材料，去除絕緣材料層280之步驟係為去光阻步驟。
顯然地，依照上面實施例中的描述，本發明可能有許多的修正與差異。因此需要在其附加的權利要求項之範圍內加以理解，除了上述詳細的描述外，本發明還可以廣泛地在其他的實施例中施行。上述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成的等效改變或修飾，均應包含在下述申請專利範圍內。
200‧‧‧IC封裝結構
210‧‧‧銅箔基板
212‧‧‧IC接合區
214‧‧‧導電區
220‧‧‧絕緣介電材料
230‧‧‧積體電路元件
240‧‧‧金屬導線
250‧‧‧黏結材料
260‧‧‧封膠材料

Claims (22)

  1. 一種積體電路(integrated circuit；IC)元件之封裝結構，包含：一銅箔基板，包含一IC接合區、複數個導電區及一種絕緣介電材料，其中該絕緣介電材料介於該IC接合區與該導電區之間及兩相鄰該導電區之間；一積體電路元件，位於該IC接合區上方，且該積體電路元件之電性與複數個該導電區相連接；以及一封膠材料，係覆蓋於該IC接合區、複數個該導電區及該積體電路元件。
  2. 如申請專利範圍第1項所述之積體電路元件之封裝結構，該積體電路元件與該IC接合區之間更包含一黏結材料。
  3. 如申請專利範圍第2項所述之積體電路元件之封裝結構，該黏結材料係包含下列群組之一者或其組合：金矽合金、金錫合金、金鍺合金、鉛錫合金、鉛銀銦合金、玻璃、金、錫、共晶合金、高導熱性金屬玻璃膠、銀玻璃膠、環氧樹酯(epoxy)或聚亞醯胺等高分子膠。
  4. 如申請專利範圍第1項所述之積體電路元件之封裝結構，其中該銅箔基板之厚度為20~50μm。
  5. 如申請專利範圍第1項所述之積體電路元件之封裝結構，其中該絕緣介電材料係包含下列群組之一者或其組合：氧化矽(SiO)、氮化矽(SiN)、氮氧化矽(SiON)、氧化鉭(TaO)、氧 化鋁(AlO)、氧化鈦(TiO)、氮化鋁(AlN)、氮化鈦(TiN)、環氧樹脂(epoxy)、矽樹脂(silicone)或高分子絕緣材料。
  6. 如申請專利範圍第1項所述之積體電路元件之封裝結構，該封裝結構更包含複數個金屬導線以連接該積體電路元件與該導電區之電性。
  7. 如申請專利範圍第1項所述之積體電路元件之封裝結構，該封裝結構更包含複數個凸塊以連接該積體電路元件與該導電區之電性。
  8. 如申請專利範圍第1項所述之積體電路元件之封裝結構，其中該IC接合區更包含一固件凹槽，該積體電路元件係固定於該固件凹槽內。
  9. 如申請專利範圍第6項所述之積體電路元件之封裝結構，其中每一個該導電區更包含一可供該金屬導線熔接之一打線凹槽。
  10. 如申請專利範圍第1項所述之積體電路元件之封裝結構，該封裝結構更包含一疊置於該銅箔基板上被圖案化之絕緣材料層，其中該絕緣材料層包括一供該積體電路元件固定之固件凹槽。
  11. 如申請專利範圍第6項所述之積體電路元件之封裝結構，該封裝結構更包含一疊置於該銅箔基板上被圖案化之絕緣材料層，其中該絕緣材料層包括一供該積體電路元件固定之固件凹槽及至少一可供該金屬導線熔接之打線凹槽。
  12. 一種積體電路元件封裝結構的製造方法，其步驟包含：提供一銅箔基板，其包括一IC接合區、複數個導電區及一種 絕緣介電材料，其中該絕緣介電材料介於該IC接合區與該導電區之間及兩相鄰該導電區之間；將一積體電路元件固接於該IC接合區上，並將該積體電路元件的電性連接至複數個該導電區；以及將一膠材包覆該積體電路元件、該IC接合區及複數個該導電區。
  13. 如申請專利範圍第12項所述之積體電路元件封裝結構的製造方法，其中該銅箔基板係由下列步驟製成：提供一銅箔板；於該銅箔板上形成複數個溝槽以分隔該IC接合區及複數個該導電區；以及在該溝槽中填入一絕緣介電材料。
  14. 如申請專利範圍第13項所述之積體電路元件封裝結構的製造方法，其中該溝槽係利用鑽孔製程、蝕刻製程或是金屬沖壓製程所形成。
  15. 如申請專利範圍第13項所述之積體電路元件封裝結構的製造方法更包含於該IC接合區形成一固件凹槽之步驟。
  16. 如申請專利範圍第15項所述之積體電路元件封裝結構的製造方法，其中該積體電路元件係固定於該固件凹槽內。
  17. 如申請專利範圍第12項所述之積體電路元件封裝結構的製造方法，其中該積體電路元件與複數個該導電區間的電性連接係藉由金屬導線來達成。
  18. 如申請專利範圍第17項所述之積體電路元件封裝結構的製造方法更包含於每一個該導電區形成一打線凹槽之步驟，其中 該打線凹槽係可供至少一金屬導線熔接之處。
  19. 如申請專利範圍第17項所述之積體電路元件封裝結構的製造方法更包含於該銅箔基板上疊置被圖案化之絕緣材料層，其中該絕緣材料層包括一供該積體電路元件固定之固件凹槽及可供至少一金屬導線熔接之複數個打線凹槽。
  20. 如申請專利範圍第12項所述之積體電路元件封裝結構的製造方法更包含以打線接合或是覆晶(flip chip)接合方式連接該積體電路元件與該銅箔基板上之該導電區的電性。
  21. 如申請專利範圍第15項或第18項所述之積體電路元件封裝結構的製造方法，其中該固件凹槽或該打線凹槽係藉由光微影蝕刻、電鑄製程或是鑽孔製程所形成。
  22. 如申請專利範圍第12項所述之積體電路元件封裝結構的製造方法，其中，將該積體電路元件固接於該IC接合區表面的方法係包含下列之一者：共晶黏結法、玻璃膠黏結法、高分子膠黏結法、銲接黏結法。
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