TWI397233B - Monitoring circuit of the rear regulator circuit - Google Patents

Description

Monitoring circuit of the post-stage voltage regulation loop

A monitoring circuit for a post-stage voltage regulation loop, in particular, a control and protection circuit, and is used for controlling a post-stage voltage regulation loop in a power supply.

The power supply has multiple outputs with different voltage levels as a conventional technique, and a common power supply configuration is to divide the secondary side of the transformer into at least one main output loop and a post-stage stable connected to the main output loop. Post regulation. The main output circuit is formed by the secondary side of the transformer through the winding induction method to form a main output power with a higher proportion of the output power, and the post-stage voltage stabilization circuit is further stepped by the main output power to form a lower voltage and power. Auxiliary output power. Taking the power supply of a general desktop computer as an example, the power and current account for a large proportion of the overall output power of the main output power of 12V, 5V, so the two windings are used to supply the main output power 12V, 5V, and then pass through the latter stage. The post regulation produces 3.3V.

Based on the above-mentioned prior art, a conventional circuit having a post-stage voltage regulation can be seen in FIG. 1, wherein the power supply has a transformer, and the current passing through the primary side 10 of the transformer is controlled by a PWM controller (PWM controller). And a set of switches, and the secondary side of the transformer has a plurality of main output circuits 11, 12 respectively generating inductive power through different windings, wherein the power is synchronously rectified by a plurality of switches (Q1 and Q2, Q3 and Q4), and After the inductor and capacitor stabilize the power waveform, two main output powers (12V and 5V) are formed. Furthermore, a set of switching elements 131, 132, an inductor 133, a capacitor and a resistor constitute a set of post-stage voltage stabilizing circuits 13 connected to the main output circuit 12, and the voltage is regulated by the operation of the switching elements 131, 132. It constitutes an auxiliary output power of 3.3V. The switching elements 131 and 132 are controlled by a post-stage control circuit (not shown), and the way to determine the on-period of the switching elements 131 and 132 is to integrate the current flowing through the inductor 133. The amplifier is amplified to drive signals to control the on-period of the switching elements 131, 132.

Since the control mechanism of the current stage voltage regulator loop monitors the inductor current in the post-stage voltage regulator loop, the inductor current is integrated to obtain a corresponding voltage to modulate the turn-on period of the set of switching elements. The protection mechanism of the post-stage voltage regulation loop is to set an upper limit value of the current. When the inductor current reaches the upper limit value, the driving pulse wave trailing edge of the pulse width modulation circuit is forcibly reduced to avoid the current being too high. However, when the auxiliary output power terminal is short-circuited, the current rises at a very high speed. Even if the trailing edge of the drive pulse is reduced, the inductor current in the subsequent voltage-stabilizing circuit will suddenly rise (about 2 to 3 clocks). The overcurrent waveform 91 in FIG. 2 is generated. Since the flow rate of the overcurrent waveform 91 is too large, the main output loop connected to the post-stage voltage stabilization loop generates a reverse current waveform 92 to burn the rectifying element. Therefore, not only the rear-stage voltage regulator loop cannot operate, but also the main output loop connected to the latter-stage voltage regulator loop.

Due to the prior art described in the preceding paragraph, the rear-stage voltage stabilizing circuit not only destroys itself when it is short-circuited, but also causes a reverse current to damage the connected main output circuit. The purpose of this case is to provide a control and protection circuit. In addition to controlling the operation of the post-stage voltage regulation loop, the current of the post-stage voltage stabilization circuit itself is further suppressed, and the main output circuit is not stabilized by the latter stage. Continue to work due to the effect of the short circuit of the voltage loop.

The present invention is a monitoring circuit of a post-stage voltage regulation loop for monitoring an auxiliary output power generated by a power supply, wherein the power supply has a transformer having at least one secondary side coil and the secondary side coil a connected main output loop, the post-stage voltage stabilization loop is connected to the main output loop and obtains a main output power of the main output loop, and the post-stage voltage stabilizing loop includes a set of switch units to convert the main output power into one The auxiliary output power, and a monitoring circuit controls the operation timing of the switching unit. The monitoring circuit includes a pulse wave generating unit, a power monitoring unit and a logic unit. The pulse wave generating unit outputs a first pulse wave to the logic unit, and the power monitoring unit sets an abnormal level, and since then The level voltage loop obtains a detected power and compares the abnormal level, and outputs a status signal to indicate whether the detected power crosses the abnormal level, and the status signal is sent to the logic unit. Finally, the logic unit determines whether to output a driving pulse wave according to the waveform of the first pulse wave according to the status signal, or stop outputting the driving pulse wave to limit the working timing of the switching unit. With the action of the above circuit, the specific effect is to suppress the operation of the switching unit before the inductor current of the post-stage voltage stabilizing circuit causes the main output circuit to generate a reverse current, so even if the rear-stage voltage stabilizing circuit is short-circuited or damaged, the main The output loop also does not generate a reverse current, which has the beneficial effect of having an independent protection mechanism in the post-stage voltage regulator loop.

In this case, a monitoring circuit for a post-stage voltage regulator loop is applied to a power supply with a post-stage voltage regulator loop. Referring to FIG. 3, the primary side 10 of the power supply of the power supply transmits power to the two main output circuits 11, 12 on the secondary side of the transformer, and is modulated by the main output circuits 11, 12 through the switch units 111, 121, respectively. 12V and 5V main output power, and a post-stage voltage stabilization circuit 13 is connected to one of the main output circuits 12, the post-stage voltage stabilization circuit 13 can obtain the 5V main output power of the main output circuit 12, and thereafter The stage voltage stabilizing circuit 13 adjusts the main output power to an auxiliary output power of 3.3 V by using a group of switching units composed of the two switching elements 131 and 132. In addition to the switching elements 131 and 132, the post-stage voltage stabilization circuit 13 may further include an inductor 133, a capacitor, and a resistor. FIG. 3 is a schematic diagram showing details of the post-stage voltage stabilization loop 13 The circuit is of course not limited to the one shown in the figure; in addition, the functions of the inductor 133, the capacitor and the like are well-known techniques well known to those skilled in the art, and therefore will not be described again.

Please refer to FIG. 3 and FIG. 4 at the same time. The feature of the present invention is that the rear-stage voltage stabilization circuit 13 is controlled by a monitoring circuit 2, and the monitoring circuit 2 obtains a feedback signal (3.3V_FB) from the auxiliary output power, and The switching unit obtains a detection power 214, and the monitoring circuit 2 adjusts a duty cycle of the driving pulse wave 24 by the feedback signal, and determines whether to reduce the driving pulse wave by detecting the power 214. The leading edge of 24 achieves the protection. The monitoring circuit 2 is described in detail as follows. The monitoring circuit 2 includes a power monitoring unit 21, a pulse wave generating unit 22, and a logic unit 23, wherein the pulse wave generating unit 22 uses a pulse width control comparator 222 to obtain a sawtooth wave. The signal 223 and the pulse width reference signal 224 are compared to each other to output a first pulse 225 having a high and a low level. In order to have the function of feedback control, a better implementation of the pulse wave generating unit 22 further includes a feedback correction amplifier 221 in addition to the pulse width control comparator 222, and the feedback correction amplifier 221 obtains a reference. The voltage (Vref) and the feedback signal (3.3V_FB) are obtained from the auxiliary output power, and the level of the pulse width level signal 224 is determined according to the voltage difference between the reference voltage and the feedback signal. Therefore, the size of the feedback signal changes the pulse width level signal 224, and the first pulse wave 225 is further changed by the size of the pulse width level signal 224 and the sawtooth wave signal 223. The power monitoring unit 21 sets an abnormal level for determining whether the power between the auxiliary output circuit 13 and the main output circuit 12 is abnormal to determine the timing at which the protection mechanism is executed. The power monitoring unit 21 mainly includes a DC current source 211 and a comparator 212. One of the comparators 212 takes a potential as an abnormal level, and the preferred embodiment in FIG. 4 makes the comparison. An input of the device 212 is grounded with a voltage of 0V as an abnormal level. The DC current source 211 and the comparator 212 have a line connecting the post-stage voltage stabilization circuit 13 to form the detection power 214. As can be seen from FIG. 3 and FIG. 4, the DC current source 211 and the comparator are shown. A line between 212 is connected between the two switching elements 131, 132, and draws the main output power flowing through the switching unit as the detected power 214, the amount of change of the detected power 214 and the auxiliary output power The amount of change is proportional. Thereby, the power monitoring unit 21 can monitor the power flowing into the auxiliary output circuit 13 to detect and avoid the generation of the reverse current as soon as possible. The DC current source 211 is driven by an overcurrent signal (OCP) to provide a buffered power and form a stable DC level in a capacitor 216, thereby increasing the DC level of the detected power 214, thus increasing the Detectivity. The difference between the power 214 and the abnormal level is measured to avoid malfunction. The comparator 212 compares the abnormal level with the detected power 214, and outputs a status signal 215 through an inverter 213. The low and high levels of the status signal 215 indicate whether the detected power 214 is crossed. This abnormal level. The logic unit 23 obtains the first pulse 225 and the status signal 215. As shown in FIG. 4, the logic unit 23 may include an AND gate to receive the first pulse 225 and the status signal 215. According to the status signal 215, it is determined whether a driving pulse wave 24 is output according to the waveform of the first pulse wave 225. More specifically, the driving pulse wave 24 is output when the state signal 215 and the first pulse wave 225 are both at a high level, and if the power monitoring unit 21 determines that the detected power 214 is abnormal, the state is stopped. Signal 215 causes logic unit 23 to turn off drive pulse 24 to limit the operational timing of the switch unit. When the switch unit has two switching elements 131, 132 as shown in FIG. 3, the logic unit 23 can include a branch line to generate a reverse driving pulse wave 25 by using an inverter, so that the switching elements 131, 132 are subjected to the The driving pulse wave 24 and the reverse driving pulse wave 25 are driven to be staggered.

Please refer to the circuit of FIG. 3 and FIG. 4, and then refer to the node waveform of FIG. 5. It can be seen in FIG. 5 that when the auxiliary output power of 3.3V is normal, the state signal 215 (OC_Lock) waveform is normally located at Micro Motion. The bit is such that the first pulse wave 225 is not constricted by the logic unit 23 at all to form the driving pulse wave 24 and the inverting driving pulse wave 25. In the normal state, the power (V _DS ) passing through the switching elements 131 and 132 enters the power monitoring unit 21, and the DC level provided by the DC current source 211 is added to form the capacitor 216 to form a view as seen in FIG. The detected power 214 (V _set ) waveform is detected. As shown in FIG. 5, the detected power 214 should be positive (above the abnormal level) in a normal state, and since the detected power 214 is obtained between the two switching elements 131, 132, it will follow the switch. The conduction periods of the elements 131, 132 fluctuate.

When the auxiliary output power (3.3V) is short-circuited, the inductor current (I _Lpost ) rises very rapidly in each charging cycle, but since the voltage of the feedback signal is too low, the pulse wave generating unit 22 instead increases the first pulse wave. 225 duty cycle, so it is not possible to quickly troubleshoot. When the inductor current (I _Lpost ) _suddenly rises to a certain amount of current, the detected power 214 is lower than the abnormal level (0V), indicating that an abnormality has occurred in the rear end of the regulator circuit 13 . When the detected power 214 is lower than the abnormal level, the output of the comparator 212 is turned, and the state signal 215 is changed to a low level through the inverter 213, so the logic unit 23 limits the driving pulse 24 The leading edge until the detected power 214 is above the abnormal level. As can be seen in FIG. 5, when the inductor current (I _Lpost ) is _{suddenly increased} , the detected power 214 (V _set ) decreases, even lower than the abnormal level (the waveform falls below the origin), and the status signal 215 (OC_Lock) transitions and limits the leading edge of the drive pulse 24 until the detected power 214 ( _Vset ) returns to normal (the waveform returns to above the origin). Before the condition of the short circuit is not eliminated, the inductor current (I _Lpost ) cannot be restored to normal, but the monitoring circuit 2 can control the reverse current condition by the large reduction of the leading edge of the driving pulse wave 24, even if the post-stage voltage regulator is controlled. The loop 13 does not work properly, nor does it cause any damage to the connected main output circuit 12, achieving the positive effect of independent protection.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any modifications and refinements made by those skilled in the art without departing from the spirit and scope of the invention should be In the invention, the scope of the invention is therefore defined by the scope of the appended claims.

In summary, the conventional circuit of the present invention enhances the above-mentioned effects, and should fully comply with the novelty and progressive statutory innovation patent requirements, and submit an application according to law, and invites your office to approve the invention patent application, to encourage creation, to Feeling the virtues.

10‧‧‧Transformer primary side

11, 12‧‧‧ main output circuit

111, 121‧‧‧ Switching components

13‧‧‧After voltage stabilization loop

131, 132‧‧‧Switching elements

133‧‧‧Inductance

2‧‧‧Monitoring circuit

21‧‧‧Power Monitoring Unit

211‧‧‧DC current source

212‧‧‧ Comparator

213‧‧‧ reverser

214‧‧‧Detecting electricity

215‧‧‧Status signal

216‧‧‧ Capacitance

22‧‧‧ Pulse Generation Unit

221‧‧‧Return correction amplifier

222‧‧‧ Pulse Width Control Comparator

223‧‧‧Sawtooth signal

224‧‧‧ Pulse width signal

225‧‧‧First pulse

23‧‧‧Logical unit

24‧‧‧ Drive pulse

25‧‧‧Backward driving pulse wave

91‧‧‧Overcurrent waveform

92‧‧‧Reverse current waveform

FIG. 1 is a schematic diagram of a conventional power supply circuit having a post-stage voltage stabilization loop.

FIG. 2 is a waveform diagram of each node of the conventional circuit of FIG. 1. FIG.

Figure 3 is a schematic diagram of the circuit of the present invention.

FIG. 4 is a schematic structural diagram of the monitoring circuit.

Figure 5 is a waveform diagram of each node of the circuit of the present invention.

10‧‧‧Transformer primary side

11, 12‧‧‧ main output circuit

111, 121‧‧‧ switch unit

13‧‧‧After voltage stabilization loop

131, 132‧‧‧Switching elements

133‧‧‧Inductance

2‧‧‧Monitoring circuit

24‧‧‧ Drive pulse

25‧‧‧Backward driving pulse wave

Claims (10)

An overcurrent protection circuit for an output loop, wherein the overcurrent protection circuit is connected to a post-stage voltage regulation loop, the post-stage voltage stabilization loop is connected to a main output loop of a transformer secondary side coil, the latter stage is stable The voltage loop obtains a main output power modulated by the main output loop, and the post-stage voltage stabilization loop includes a group of switch units to adjust the main output power to an auxiliary output power, and the overcurrent protection circuit controls the switch a working sequence of the unit, wherein the overcurrent protection circuit uses a feedback signal obtained from the auxiliary output power to adjust a duty cycle of a driving pulse wave, and determines whether to reduce the driving pulse by using the detected power obtained from the switching unit The leading edge of the wave. The overcurrent protection circuit of claim 1, wherein the overcurrent protection circuit comprises: a pulse wave generating unit, the pulse wave generating unit outputs a first pulse wave; and a power monitoring unit, the power monitoring device The unit sets an abnormal level, and obtains a detected power from the rear-stage voltage stabilization loop to compare with the abnormal level, and outputs a status signal to indicate whether the detected power crosses the abnormal level; and a logic a unit, the logic unit obtains the first pulse wave and the status signal, and determines whether to output a driving pulse wave according to the waveform of the first pulse wave according to the status signal, or stop outputting the driving pulse wave to limit the switching unit The timing of the work. The overcurrent protection circuit of claim 2, wherein the logic circuit comprises: at least one logic gate for performing a predetermined logic operation on the first pulse wave and the state signal to determine the driving pulse wave Output. The overcurrent protection circuit of claim 2, wherein the amount of change in the detected power is proportional to the amount of change in the auxiliary output power. The overcurrent protection circuit of claim 4, wherein the detected power is extracted from a main output power flowing through the switching unit. The overcurrent protection circuit of claim 2, wherein the power monitoring unit outputs a buffered power to increase a DC level of the detected power to increase a gap between the detected power and the abnormal level. Avoid malfunctions. The overcurrent protection circuit of claim 6, wherein the power monitoring unit comprises a DC current source for providing the buffered power, and a comparator for obtaining the abnormal level, wherein the DC current source and the comparator The detection power is obtained by connecting a circuit of the rear stage voltage stabilization circuit, and the comparator compares the abnormal level and the detected power of the DC level by the buffer power, and determines the output according to the size of the two. The timing of this status signal. The overcurrent protection circuit of claim 2, wherein the pulse wave generating unit uses a pulse width control comparator to obtain a sawtooth wave signal and a pulse width level signal, and compares the two sizes to output one The first pulse of high and low levels. The overcurrent protection circuit of claim 8, wherein the pulse wave generating unit further comprises a feedback correction amplifier that outputs the pulse width level signal, the feedback correction amplifier obtains a reference voltage and an auxiliary output. The power obtains a feedback signal, and determines the level of the pulse width level signal according to the voltage difference between the reference voltage and the feedback signal. An overcurrent protection circuit for an output loop, wherein the overcurrent protection circuit is connected to a post-stage voltage regulation loop, the post-stage voltage stabilization loop is connected to a main output loop of a transformer secondary side coil, the latter stage is stable The pressure circuit obtains a main output power modulated by the main output circuit, And the post-stage voltage regulation loop includes a switch unit that converts the main output power into an auxiliary output power, and the over-current protection circuit controls an operation timing of the switch unit, wherein the over-current protection circuit comprises: a pulse wave generation a unit, the pulse wave generating unit outputs a first pulse wave; a power monitoring unit, the power monitoring unit sets an abnormal level, and obtains a detected power from the rear voltage stabilizing circuit to compare with the abnormal level, And outputting a status signal to indicate whether the detected power crosses the abnormal level; and a logic unit, the logic unit obtains the first pulse wave and the status signal, and determines whether to follow the first pulse according to the status signal The waveform of the wave outputs a driving pulse wave, or stops outputting the driving pulse wave to limit the operation timing of the switching unit.