1377423 < ψ 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種電極結構，特別是關於一種高顯示品質之畫素 電極結構。 【先前技術】 請參閱第1圖，在傳統主動矩陣式的液晶顯示器（LCD)中，其 單閘極電路架構之每個畫素具有一薄膜電晶體（TFT) 1〇，其閘極連 接至水平方向的掃瞄線12，源極連接至垂直方向的資料線14，汲極則 連接至畫素電極，鄰行的薄膜電晶體10有各自連接的資料線14。 隹 以下介紹此傳統電路架構的基本操作方式，在水平方向上的同一 條掃瞒線12上，所有薄膜電晶體1〇的閘極都連接在一起，所以施加 電壓疋連動的’若在某-條掃瞒線上施力口足夠大的正電壓，則此條 掃瞒線上所有的薄膜電晶體12都會被打開，此時該條掃猫線12上的 晝素電極’會直方向的資料線14連接，而經由垂直資料線14送 入對應的視訊信號，以將畫素電極充電至適當的電壓。接著施加足夠 大的負電壓，關閉薄膜電晶體1〇，直到下次再重新寫入信號，其間使 得電荷保存在液晶電容上；此時再啟動—條水平娜線彳2，送入其對 應的視讯、號。如此依序將整個畫面的視訊資料寫入，再重新自第一 1条重新寫入信號。 上述之單閘極電路架構由於資料線14的數量過多，因此其消耗在 ， 源極W上的成本相當高’而為了減少此成本的消耗 ，後來的技術提 出了-種雙閘極電雜構，也就是如第2圖所示，相鄰兩行的薄膜電 •晶體二6共用同-條資料線18，這樣一來，就可以減少資料線18的使 用數罝’進而降低源極晶片的製造成本。另外為了解決面板顯示的串 音(crosstalk)現象，在相鄰的資料線18之間更設有一虛擬線2〇，並 在虛擬線20上提供與資料線18極性相反的訊號，如此便能使面板呈 現更好顯示效果。 - 3 1377423 但是對於上述所提供的技術而言，其從電路佈局來觀察，如第3 圖所示，因為共通電極線22佔有面積過大，使電極層24扣掉形成共 通電極線22之金屬層的透光區域變少，進而讓整個面板的開口率有所 損失。 因此，本發明係在針對上述之困擾，提出一種高顯示品質之畫素 電極結構，以解決習知所產生的問題。 【發明内容】 本發明之主要目的，在於提供一種高顯示品質之畫素電極結構， 其係將共通電極線設置在相鄰之掃瞄線之間，以減少共通電極線之數 量，如此可提升面板之晝素開口率p 本發明之另一目的，在於提供一種高顯示品質之畫素電極結構， 其係將共通電極線與虛擬線做短路連接，以擁有較佳的共同訊號之穩 定性’並於資料線斷線時’可利用雷射修補的方式再與虛擬線連接， 藉此提升良率。 為達上述目的，本發明提供一種高顯示品質之晝素電極結構，包 含一透明基板，此基板上設有一資料線、一共通電極線與一第一、第 二陣列畫素，第一陣列畫素係形成一第一薄膜電晶體、一第一晝素電 極與一第一掃瞄線，且使共通電極線設置於第一掃瞄線側方，第二陣 列畫素係形成一第一薄膜電晶體、一第二畫素電極、一第二掃瞎線， 且亦使共通電極線設置於第二掃瞄線側方，另在共通電極線上設有一 第一、第二通孔，其分別與第一、第二薄膜電晶體延伸端接觸，在資 料線之側邊設有一虛擬線，且又有一第三通孔位於虛擬線與共通電極 線上。 茲為使貴審查委員對本發明之結構特徵及所達成之功效更有進 —步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明 如後： 【實施方式】 1377423 ㈣製作之液晶顯示面板主要係姻先前技術已設有之虛擬 線與和與_電晶體端之共料極連接的共通電極線進行短路設計。 請同時參閱第4圖與第5圖之電路佈局的第—實施例，第5圖為第4 圖中虛線方财的畫素電極結構之放Α示意@，此虛線方框中所有的 X件包含二由f極層50軸的畫素電極、二顆薄膜電晶趙26、28及 其周圍的佈線，薄膜電晶體26、28為N型，而第4關是以此虛線 方框中的畫素電極結構鱗元，彼此_#_(Gate Hne)3()、資料 線(Data丨ine>32、虛擬線34及共通電極線36相互連接而構成的陣列136. The invention relates to an electrode structure, and more particularly to a pixel structure of high display quality. [Prior Art] Referring to FIG. 1, in a conventional active matrix liquid crystal display (LCD), each pixel of a single gate circuit structure has a thin film transistor (TFT), and its gate is connected to The scanning line 12 in the horizontal direction has a source connected to the data line 14 in the vertical direction, a drain electrode connected to the pixel electrode, and a thin film transistor 10 in the adjacent row having the data line 14 connected thereto.隹 The following describes the basic operation of this traditional circuit architecture. On the same broom line 12 in the horizontal direction, all the gates of the thin-film transistors are connected together, so the voltage is applied in conjunction with the 'if- A large positive voltage is applied to the broom line, and all the thin film transistors 12 on the broom line are opened. At this time, the halogen electrode on the cat line 12 will be in the straight direction of the data line 14 Connected, and the corresponding video signal is fed via the vertical data line 14 to charge the pixel electrode to an appropriate voltage. Then apply a large enough negative voltage to turn off the thin film transistor 1 〇 until the next time the signal is rewritten, during which the charge is stored on the liquid crystal capacitor; at this point, start again - the horizontal line 彳 2, into its corresponding Video, number. In this way, the video data of the entire picture is sequentially written, and the signal is rewritten from the first one. The single gate circuit architecture described above has a high cost due to the excessive number of data lines 14, and the cost of the source W is quite high. In order to reduce the cost, the latter technique proposes a double gate electrical hybrid structure. That is, as shown in FIG. 2, the adjacent two rows of thin film transistors 2 share the same data line 18, so that the number of data lines 18 can be reduced, thereby reducing the source wafer. manufacturing cost. In addition, in order to solve the crosstalk phenomenon displayed on the panel, a virtual line 2〇 is further disposed between adjacent data lines 18, and a signal opposite to the polarity of the data line 18 is provided on the virtual line 20, so that The panel presents a better display. - 3 1377423 However, as for the technique provided above, it is observed from the circuit layout. As shown in FIG. 3, since the common electrode line 22 occupies an excessive area, the electrode layer 24 is buckled off to form a metal layer of the common electrode line 22. The light transmissive area is reduced, which in turn causes a loss in the aperture ratio of the entire panel. Accordingly, the present invention has been made in view of the above-mentioned problems, and has proposed a pixel structure of high display quality to solve the problems caused by the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a pixel display structure with high display quality, wherein a common electrode line is disposed between adjacent scan lines to reduce the number of common electrode lines, thereby improving The aperture ratio p of the panel is another object of the present invention to provide a pixel structure with high display quality, which is to short-circuit the common electrode line and the dummy line to have better stability of the common signal. And when the data line is disconnected, it can be connected to the virtual line by means of laser repair, thereby improving the yield. To achieve the above objective, the present invention provides a high display quality pixel electrode structure comprising a transparent substrate, wherein the substrate is provided with a data line, a common electrode line and a first and second array of pixels, and the first array is drawn. Forming a first thin film transistor, a first halogen electrode and a first scan line, and the common electrode line is disposed on a side of the first scan line, and the second array of pixels forms a first film a transistor, a second pixel electrode, and a second brush line, and the common electrode line is disposed on the side of the second scan line, and the first and second through holes are respectively disposed on the common electrode line. In contact with the extended ends of the first and second thin film transistors, a dummy line is disposed on a side of the data line, and a third through hole is located on the virtual line and the common electrode line. In order to make the reviewer's understanding of the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description, as follows: [Embodiment] 1377423 (4) The liquid crystal display panel produced is mainly designed to short-circuit the imaginary electrode line which has been provided in the prior art and the common electrode line connected to the common electrode of the _ transistor end. Please refer to the fourth embodiment of the circuit layout of FIG. 4 and FIG. 5 at the same time. FIG. 5 is a schematic diagram of the pixel structure of the dotted square in the fourth figure, and all the X pieces in the dotted box. A pixel electrode comprising two 50-axis layers of the f-pole layer, two thin film electro-opticals 26, 28 and surrounding wiring thereof, the thin film transistors 26, 28 being N-type, and the fourth level is in the dashed box The pixel structure structure scale, an array formed by mutually connecting _#_(Gate Hne)3(), data line (Data丨ine>32, imaginary line 34, and common electrode line 36)
液晶顯示面板。且，由於畫素電極結構在顯柯板上是以矩陣方式排 列’因此同一行的畫素電極結構會共用同一條資料線32、虛擬線34， 同一列的畫素電極結構會共用同一條掃瞄線3〇與共通電極線36 ^每 一個晝素電極結構中的元件之連接關係與位置關係都相同，茲以一個 晝素電極結構為例，陳述如下。 為了清楚說明實施方式，以下請同時參閱第5圖與第6圖，第6 圖為第5圖之電路佈局(layout)結構中沿A-A’切線之剖視圖，可表達出 第5圖中所包含的元件之上下堆疊關係。第5圖為一畫素電極結構， 其主要包含一透明基板38、一第一陣列晝素與一第二陣列晝素，第 —、第二陣列畫素係分別形成第一、第二薄膜電晶體26、28、第—、 第二畫素電極33、35，以及第一、第二掃瞄線60、62 »第一、第二 陣列晝素係由一第一金屬層40、一絕緣層42、一半導體層44、一第 二金屬層46、一保護層48、一電極層50所形成，而液晶層係設在電 極層上50。保護層48係為一絕緣材質’其與絕緣層42之材質皆為氮 化矽’電極層50的材質為氧化銦錫（IT0)’且此電極層5〇係形成與 第一、第二薄膜電晶體26、28分別連接之第一、第二晝素電極33 ' 35 〇 第一金屬層40係設於透明基板38上，以形成一第一薄膜電晶體 26之閘極56、一第二薄膜電晶體28之閘極58、一第一掃瞄線6〇、 一第二掃瞄線62與在第一掃瞄線60下方與第二掃瞄線62上方之兩 1377423 =間Ϊ一共通電極線64，然在第一金屬層40形成時，同時分別將 i如第Γ婦描線6〇、62與第一、第二薄膜電晶體26、28之閘極 络® π形成為相連之線路，第—金屬層4G形成後其上係形成有一絕 、’絕緣層42係於第-、二薄膜電晶體26、28上作為閘極絕緣 。絕緣層42上係設有半導趙層44，此半導趙層44分為上下二層結 其下層為一非晶矽層(a-Si)52，係直接設於絕緣層42上，其上層 ^- n+摻凡雜非晶石夕(n+a_Si)之歐姆接觸層％，歐姆接觸層％與絕緣層 上係°又有一第二金屬層46，以形成第一、第二薄膜電晶體26、28 66、68與汲極7〇、72、-虛擬線74與在該虛擬線74側邊的 資料線78,資料線78係連接第—、第二薄膜電晶體26、28之源極 66、68，又第一、第二薄膜電晶體26、28係位於資料線78的相異兩 侧第一、第二薄膜電晶體26、28係分別位於第一、第二掃瞄線60、 62的相異兩側，第一、第二薄膜電晶體26、28 U原66、68、沒極 70 72係分別位於第一、第二薄膜電晶體26、28之閘極56、58上 方’且非晶矽層52與歐姆接觸層54皆位於第一、第二薄膜電晶體26、 28 =源極66、68與没極70、72下方，虛擬線74與資料線78互相 平行叹置’並與共通電極線64及第一、第二掃瞄線6〇、62垂直交會》 另從圖中可以發現，第一畫素電極33設於第一掃瞄線60下方且 於共通電極線64及第二掃瞒線62,其中第—晝素電極33與第二 掃聪線62重疊面積小於第一晝素電極33與共通電極線64重疊面積。 而第二晝素電極35設於第二掃瞄線62上方且重疊於共通電極線64 及第一掃瞄線60’其中第二晝素電極35與第一掃瞄線6〇重疊面積小 於第二晝素電極35與共通電極線64重疊面積。 接下來請同時參閱第5圖、第6圖及第7圖，第7圖為第5圖之 電路佈局結構中沿B-B，切線之剖視圖。歐姆接觸層54與第二金屬層 46^係覆蓋-保護層48，此保護層48具有分別位於第-、第二薄膜 電晶體26、28之沒極70、72和半導體層44上方的一第一、第二通 孔80、8彳，與位於虛擬線74和共通電極線64之交界處的一第三通孔 護層48僅有部份覆蓋其線宽，__ 舶穿下方名緣層42，另在保護層48钱刻出第一、第 第：Γ透過半導想層44並繼續往絕緣層42_ :第 為第tmr度係僅能到達半麵44。第-通孔8〇 7 . 中的保護層48沒有連接的部分，第三通孔82為坌 圖之剖視圖令的保護層48與絕緣層42沒有連接的部分。 在保護層48上係設有一電極層5〇，此電極層5〇不但 二、第二通孔80、81與對應的第一、第二薄膜電晶體26、28 ^沒極 丑ii It半輪1 44相接觸，又可藉由第三通孔82與虛擬線74和 ，、通電極線64相接觸。如第6圖所示，由於通孔的緣故 7〇的第二金屬層46*半導體層44暴露在外，因此可與電極層5〇相 接觸；亦如第7圖所示’由於通孔的緣故’作為虛擬線74之第二金屬 層46和作為共通電極線64之第一金屬層40也暴露在外，因此可與 電極層50相接觸，此處的電極層50為獨立電極層區塊，可將虛擬線 74與共通電極線64相連接並令其導通。 ν 另外’與薄膜電晶體之汲極相接觸的電極層5〇和第一金屬層4〇、 第一金屬層46重疊的部分’可形成該薄膜電晶體之儲存電容。如第一 薄膜電晶體26之汲極70有一部分係往共通電極線64延伸，並與此 共通電極線64和電極層50重疊之部分為第一薄膜電晶體26之儲存 電谷，第二薄臈電晶體28之沒極72有一部分係往共通電極線延 伸，並與此共通電極線64和電極層50重疊之部分為第二薄膜電曰 28之儲存電容。 、Μ 還有’此實施例之電極層50並沒有與第一、第二薄膜電晶體26、 28之汲極70、72侧的第一、第二掃瞄線60、62重疊，所以在連接 每個薄膜電晶體之電極層邊緣處’必須於彩色濾光片中對應設置遮光 物，如黑色矩陣（BM)。如此一來，當顯示面板製作成液晶顯示器時， 每一個晝素邊緣才不會出現漏光’而影響液晶分子排列，且鄰接畫素 才不會出現混色的現象。 盘生」用上述電路佈局所奴絲的液晶顯示面板如第4圖所示，可 技術之第3圖同時峻，在轉軸線30與轉資料線32的 別二個畫素的晝素顯示區，在本發明之設計下，共 $極線36不會侵佔到電極層5G之透光區域的面積另外在相同的 體的數#下’第4 _使用到的共通電極線36的數量比第3圖 >、’如八顆電晶體本發_㈣二條共通電極線， 四條，^賴，域餅航提升畫素_口率。 接著請同時參㈣8圖與第9圖之電路佈局的第二實施例，其與 第實施例的差異在於電極層5〇係與第一、第二薄膜電晶體26、28 之没極70、72側的第一、第二掃猫線6〇、62部份重疊所以在連接 每個薄膜電晶體之電極層與第—、第二掃_6〇、62重疊區域的邊緣 處不必於彩色濾光片中對應設置遮光物，此種設計可同時增加了儲 存電容的分佈面積，進而減少面板閃爍率，且增加其開口率。 參閱完本發明之電路佈局，請繼續參閱其等效電路圖，如第1〇圖 所不。本發明之液晶顯示面板的等效電路包含複數條平行之掃描線86 與複數條平行之資料線84，掃描線86包含有一第一掃描線862與一 第二掃描線864，資料線84係與掃描線86互相垂直，且資料線84 中包含一第一資料線842，掃描線86係與複數共通電極線88互相平 行，且共通電極線88包含一第一共通電極線882 » 本發明之液晶顯示面板還包含以矩陣方式排列的複數雙閘極畫素 單元92 ’並以資料線84、掃瞄線86與共通電極線88彼此連接而成， 每一個雙閘極畫素單元92係連接一條資料線84、二條掃瞄線86與一 條共通電極線88。同一行的雙閘極畫素單元92會共用同一條資料線 84,同一列的雙閘極晝素單元92會共用同一條掃瞄線86與共通電極 線88 每一個雙閘極晝素單元92中的元件之連接關係與位置關係都 相同，兹以一個雙閘極畫素單元92為例，並將第一、第二掃瞄線862、 864、第一資料線842、第一共通電極線882與一雙閘極書素單元92 彼此之間的連接與位置關係介紹如下。 1377423 請同時參閱第12圖’每一個雙閘極畫素單元92包含一第一薄膜 電晶體922及其對應連接之一第一液晶電容925、一第一儲存電容 926 ’與一第二薄膜電晶體924及其對應連接之一第二液晶電容927、 一第二儲存電容928，且第一掃瞄線862與第二掃瞄線864之相異兩 側係分別設有一薄膜電晶體及其對應連接之液晶電容、儲存電容，第 一資料線842之相異兩侧亦分別設有一薄膜電晶體及其對應連接之液 晶電容、儲存電容，第一掃瞄線862及第二掃瞄線864係設於第一共 通電極線882的相異兩側》 第一薄膜電晶體922之閘極連接第一掃瞄線862，其源極連接第 • 一資料線842 ,其汲極連接第一液晶電容925與第一儲存電容926之 一端，第一液晶電容925之另一端連接一彩色濾光片（CF)端之共通電 極，以接收一第一共通電極訊號，第一儲存電容926之另一端連接第 一共通電極線882，第一資料線842與第一共通電極線882分別傳輸 一資料訊號與一第二共通電極訊號至第一薄膜電晶體922中，且第一 掃瞒線862控制第-薄膜電晶體922接收該資料訊號，進而控制第一 液晶電容925之充放電，而第—儲存電容926個來維持第—液晶電 容925兩端的電位差，以防第一液晶電容925漏電的情況發生。 同樣地’第二溥膜電晶體924之閘極連接第二掃瞄線864，其源 籲極連接第-資料、線842，其沒極連接第二液晶電容927與第二儲存電 容928之-端，第二液晶電容927之另一端連接彩色滤光片端之共通 電極’以接收第一共通電極訊號，第二儲存電容928之另-端連接第 ^共通電極、線882，第一資料線842與第一共通電極線册2分別傳輸 資料訊號與第二共通電極訊號至第二薄膜電晶體924中，且第二掃: 線=4控制第二薄膜電晶體924接收該資料訊號，進而控制第:液晶 電容927之充放電，而第二儲存電容928係用來維持第二液晶電容 兩端的電位差’以防第二液晶電容927漏電的情況發生。 液晶顯示面板還包含複數虛擬線9〇，每一條虛擬線9〇係& 於相鄰兩行之雙閘極晝素單元92之間，並短路連接共通電極線肪叹 9 1377423 由於在第二共通電極訊號在共通電極線88傳輸的過程中，會因為佈線 的長度過長而造成面板中央處的訊號不穩定，因此將共通電極線88藉 由與該些虛擬線90短路’以穩定第二共通電極訊號。 第10圖可與先前技術之第2圖同時比較，如同電路佈局比較的結 果，在相同的電晶體的數量下，第8圖所使用到的共通電極線的數量 比第2圖少，換句話說，如此便能提升晝素的開口率，且此電路設計 可應用於垂直配向式（VA type)、扭轉向列式（TN type)、平面轉換 式（IPStype)之液晶或是有有機緣膜之晝素設計。 請繼續參閱第10圖’本發明之液晶顯示面板的作動描述如下，首 先每一條共通電極線88與資料線84係分別傳輸一第二共通電極訊號 φ 與一資料訊號至連接的儲存電容98與薄膜電晶體94中，且每一個液 晶電容96係接收一第一共通電極訊號，同時由於每一條共通電極線 88彼此藉由虛擬線90短路連接的緣故，因此在每一條共通電極線88 中的第二共通電極訊號是相當穩定的。接著利用掃瞄線86由上而下依 序控制每一行的薄膜電晶體94接收該資料訊號，進而控制液晶電容 96之充放電，同時連接液晶電容96的儲存電容98則用來維持液晶電 容96兩端的電位差。 最後睛參閱第12圖，本發明之液晶顯示面板的電路設計還有一項 優點，即是當資料線842斷線時，可在虛線方框所在位置處利用雷射 鲁 將其斷線後，在虛線圈所在位置處，再利用雷射將第一資料線842與 共通電極線88連接，即可利用第一虛擬線9〇2來代替以斷線之資料 線842而修補完成’同時提昇產品良率。 紅上所述，本發明不但可提升面板之畫素開口率，又將共通電極 線與虛擬線做短路連接，以擁有較佳的共同訊號之穩定性，是一種相 當實用的發明。 以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發 明實施之範圍’故舉凡依本發明申請專利範圍所述之形狀構造、特 徵及精神所為之均等變化餅飾，均應包括於本發明之㈣專利範圍 1377423 内。 【圖式簡單說明】 第1圖與第2圖為先前技術之顯示面板的電路示意圖。 第3圖為先前技術之顯示面板的電路佈局(layout)結構示意圖。 第4圖為本發明之液晶顯示面板的第一實施例之電路佈局結構示意圖。 第5圖為本發明之液晶顯示面板的第一實施例之電路佈局結構之局部 放大示意圖。 第6圖為第5圖之電路佈局結構中沿A-A，切線之結構剖視圖。 第7圖為第5圖之電路佈局結構中沿B_B，切線之結構剖視圖。LCD panel. Moreover, since the pixel electrode structures are arranged in a matrix on the display board, the pixel electrodes of the same row share the same data line 32 and the dummy line 34, and the pixel electrodes of the same column share the same sweep. The connection relationship and the positional relationship of the components in the structure of each of the pixel electrodes 36 are the same as those of the common electrode line 36. A single pixel electrode structure is taken as an example and is as follows. In order to clarify the embodiment, please refer to FIG. 5 and FIG. 6 at the same time. FIG. 6 is a cross-sectional view along the line A-A' in the circuit layout structure of FIG. 5, which can be expressed in FIG. The included components are stacked on top of each other. Figure 5 is a pixel electrode structure, which mainly comprises a transparent substrate 38, a first array of halogen and a second array of halogen, and the first and second array of pixels respectively form the first and second thin films. The crystals 26, 28, the first and second pixel electrodes 33, 35, and the first and second scan lines 60, 62 are: a first metal layer 40, an insulating layer 42. A semiconductor layer 44, a second metal layer 46, a protective layer 48, and an electrode layer 50 are formed, and the liquid crystal layer is disposed on the electrode layer 50. The protective layer 48 is an insulating material. The material of the insulating layer 42 is tantalum nitride. The electrode layer 50 is made of indium tin oxide (IT0) and the electrode layer 5 is formed into a first and second film. The first and second halogen electrodes 33' 35 〇 are connected to the transparent substrate 38 to form a gate 56 and a second of the first thin film transistor 26, respectively. The gate 58 of the thin film transistor 28, a first scan line 6 〇, and a second scan line 62 are common to the two 1374432=1 under the first scan line 60 and the second scan line 62. The electrode line 64, while the first metal layer 40 is formed, simultaneously forms a line such as the first and second thin film transistors 26, 62 and the first and second thin film transistors 26, 28 respectively. After the formation of the first metal layer 4G, an insulating layer 42 is formed on the first and second thin film transistors 26 and 28 as gate insulating. The insulating layer 42 is provided with a semi-conductive layer 44. The semi-conductive layer 44 is divided into upper and lower layers, and the lower layer is an amorphous layer (a-Si) 52, which is directly disposed on the insulating layer 42. The upper layer of the ohmic contact layer of the upper layer of n-n+doped amorphous austenite (n+a_Si), the ohmic contact layer% and the upper layer of the insulating layer further have a second metal layer 46 to form the first and second thin film transistors 26, 28 66, 68 and the drain 7 〇, 72, - the imaginary line 74 and the data line 78 on the side of the imaginary line 74, the data line 78 is connected to the source of the first and second thin film transistors 26, 28 66, 68, the first and second thin film transistors 26, 28 are located on the opposite sides of the data line 78. The first and second thin film transistors 26, 28 are respectively located on the first and second scan lines 60, On the opposite sides of 62, the first and second thin film transistors 26, 28 U, 66, 68, and the bottom 70 72 are located above the gates 56, 58 of the first and second thin film transistors 26, 28, respectively. The amorphous germanium layer 52 and the ohmic contact layer 54 are both located below the first and second thin film transistors 26, 28 = the source 66, 68 and the gates 70, 72, and the dummy line 74 and the data line 78 are parallel to each other. And common electrode The line 64 and the first and second scan lines 6〇, 62 intersect perpendicularly. It can be seen from the figure that the first pixel electrode 33 is disposed under the first scan line 60 and on the common electrode line 64 and the second scan. The ridge line 62, wherein the overlap area of the first halogen electrode 33 and the second snubber line 62 is smaller than the overlapping area of the first halogen electrode 33 and the common electrode line 64. The second halogen electrode 35 is disposed above the second scan line 62 and overlaps the common electrode line 64 and the first scan line 60 ′. The area of the second halogen element 35 and the first scan line 6 〇 is smaller than the first The dioxet electrode 35 overlaps the common electrode line 64. Next, please refer to Fig. 5, Fig. 6, and Fig. 7, and Fig. 7 is a cross-sectional view taken along line B-B of the circuit layout structure of Fig. 5. The ohmic contact layer 54 and the second metal layer 46 are covered with a protective layer 48 having a first layer on the first and second thin film transistors 26, 28 and the semiconductor layer 44. 1. The second through holes 80, 8彳, and a third through hole cover 48 located at the boundary between the virtual line 74 and the common electrode line 64 only partially cover the line width thereof, and __ is passed through the lower edge layer 42 In addition, the first layer and the first layer are engraved on the protective layer 48: Γ through the semiconducting layer 44 and continue to the insulating layer 42_: the first tmr degree system can only reach the half surface 44. The protective layer 48 in the first through-hole 8 〇 7 has no connected portion, and the third through-hole 82 is a portion of the cross-sectional view in which the protective layer 48 and the insulating layer 42 are not connected. An electrode layer 5 is disposed on the protective layer 48. The electrode layer 5 is not only two, but the second through holes 80 and 81 and the corresponding first and second thin film transistors 26 and 28 are not extremely ugly. The first 44 holes are in contact with the dummy wires 74 and the through electrode wires 64. As shown in Fig. 6, the second metal layer 46* of the semiconductor layer 44 is exposed to the outside due to the via hole, so that it can be in contact with the electrode layer 5?; as shown in Fig. 7, due to the via hole The second metal layer 46 as the dummy line 74 and the first metal layer 40 as the common electrode line 64 are also exposed, and thus can be in contact with the electrode layer 50, where the electrode layer 50 is an independent electrode layer block, The dummy line 74 is connected to the common electrode line 64 and turned on. ν Further, the portion of the electrode layer 5A which is in contact with the drain of the thin film transistor and the first metal layer 4A and the first metal layer 46 may form a storage capacitor of the thin film transistor. For example, a portion of the drain 70 of the first thin film transistor 26 extends toward the common electrode line 64, and a portion overlapping the common electrode line 64 and the electrode layer 50 is a storage valley of the first thin film transistor 26, and the second thin portion A portion of the pole 72 of the germanium transistor 28 extends toward the common electrode line, and a portion overlapping the common electrode line 64 and the electrode layer 50 is a storage capacitor of the second thin film capacitor 28. Further, the electrode layer 50 of this embodiment does not overlap with the first and second scanning lines 60 and 62 on the sides of the first and second thin film transistors 26 and 28, so that the electrode layer 50 is connected. At the edge of the electrode layer of each of the thin film transistors, a light shield, such as a black matrix (BM), must be disposed correspondingly in the color filter. In this way, when the display panel is fabricated into a liquid crystal display, light leakage does not occur at each edge of the pixel, which affects the alignment of the liquid crystal molecules, and the adjacent pixels do not appear to be mixed. The liquid crystal display panel which is slain by the above circuit layout is as shown in Fig. 4, and the third figure of the technique can be simultaneously displayed in the pixel display area of the other two pixels of the rotation axis 30 and the data line 32. Under the design of the present invention, the total $electrode line 36 does not encroach on the area of the light-transmitting region of the electrode layer 5G, and the number of common electrode lines 36 used in the fourth body is the same as the number of the common body electrode 36. 3 maps >, 'such as eight transistors, the hair _ (four) two common electrode lines, four, ^ Lai, domain cake navigation to enhance the picture _ mouth rate. Next, please refer to the second embodiment of the circuit layout of FIG. 4 and FIG. 9 at the same time, which differs from the first embodiment in that the electrode layer 5 and the first and second thin film transistors 26 and 28 have the poles 70 and 72. The first and second sweeping cat lines 6〇 and 62 on the side are partially overlapped, so that it is not necessary to color filter at the edge of the overlapping region of the electrode layer connecting each of the thin film transistors and the first and second sweeps _6〇, 62. The corresponding shading is set in the film. This design can increase the distribution area of the storage capacitor at the same time, thereby reducing the panel flicker rate and increasing the aperture ratio. Having completed the circuit layout of the present invention, please continue to refer to its equivalent circuit diagram, as shown in Figure 1. The equivalent circuit of the liquid crystal display panel of the present invention comprises a plurality of parallel scan lines 86 and a plurality of parallel data lines 84. The scan lines 86 include a first scan line 862 and a second scan line 864. The scan lines 86 are perpendicular to each other, and the data line 84 includes a first data line 842, the scan line 86 is parallel to the plurality of common electrode lines 88, and the common electrode line 88 includes a first common electrode line 882. The display panel further includes a plurality of double gate pixel units 92' arranged in a matrix and connected by a data line 84, a scan line 86 and a common electrode line 88. Each of the double gate pixel units 92 is connected to one. The data line 84, the two scanning lines 86 and one common electrode line 88. The double gate pixel unit 92 of the same row will share the same data line 84, and the double gate electrode unit 92 of the same row will share the same scanning line 86 and the common electrode line 88 in each double gate unit 102. The connection relationship and the positional relationship of the components are the same. For example, a double gate pixel unit 92 is taken as an example, and the first and second scan lines 862 and 864, the first data line 842, and the first common electrode line 882 are connected. The connection and positional relationship between a pair of gate pheromone units 92 are as follows. 1377423 Please also refer to FIG. 12 'Each double-gate pixel unit 92 includes a first thin film transistor 922 and a corresponding one of the first liquid crystal capacitor 925, a first storage capacitor 926' and a second thin film. The crystal 924 and its corresponding connection are a second liquid crystal capacitor 927 and a second storage capacitor 928, and the opposite sides of the first scan line 862 and the second scan line 864 are respectively provided with a thin film transistor and corresponding The connected liquid crystal capacitor and the storage capacitor are respectively provided with a thin film transistor and a correspondingly connected liquid crystal capacitor and storage capacitor on the opposite sides of the first data line 842, and the first scan line 862 and the second scan line 864 are respectively connected. The first thin film transistor 922 has a gate connected to the first scan line 862, a source connected to the first data line 842, and a drain connected to the first liquid crystal capacitor. 925 is connected to one end of the first storage capacitor 926, and the other end of the first liquid crystal capacitor 925 is connected to a common electrode of a color filter (CF) end to receive a first common electrode signal, and the other end of the first storage capacitor 926 is connected. First common electrode line 882, The first data line 842 and the first common electrode line 882 respectively transmit a data signal and a second common electrode signal to the first thin film transistor 922, and the first scan line 862 controls the first thin film transistor 922 to receive the data. The signal, in turn, controls the charging and discharging of the first liquid crystal capacitor 925, and the first storage capacitor 926 maintains the potential difference across the first liquid crystal capacitor 925 to prevent the first liquid crystal capacitor 925 from leaking. Similarly, the gate of the second germanium transistor 924 is connected to the second scan line 864, and the source is connected to the first data line 842, and the second electrode is connected to the second liquid crystal capacitor 927 and the second storage capacitor 928. The other end of the second liquid crystal capacitor 927 is connected to the common electrode of the color filter end to receive the first common electrode signal, and the other end of the second storage capacitor 928 is connected to the common electrode, the line 882, and the first data line. 842 and the first common electrode coil 2 respectively transmit the data signal and the second common electrode signal to the second thin film transistor 924, and the second scan: line=4 controls the second thin film transistor 924 to receive the data signal, thereby controlling The charging and discharging of the liquid crystal capacitor 927 and the second storage capacitor 928 are used to maintain the potential difference between the two liquid crystal capacitors to prevent the second liquid crystal capacitor 927 from leaking. The liquid crystal display panel further includes a plurality of virtual lines 9〇, each of the virtual lines 9 is connected between the adjacent two rows of double gates of the pixel unit 92, and is short-circuited to the common electrode line to sigh 9 1377423 due to the second common During the transmission of the common electrode line 88, the signal at the center of the panel is unstable due to the length of the wiring being too long. Therefore, the common electrode line 88 is short-circuited with the virtual lines 90 to stabilize the second common. Electrode signal. Figure 10 can be compared with Figure 2 of the prior art. As a result of the circuit layout comparison, the number of common electrode lines used in Figure 8 is less than that of Figure 2 under the same number of transistors. In other words, the aperture ratio of the pixel can be improved, and the circuit design can be applied to a vertical alignment type (VA type), a twisted nematic (TN type), a planar conversion type (IPStype) liquid crystal or an organic film. The design of the element. Please refer to FIG. 10 for the operation of the liquid crystal display panel of the present invention. First, each common electrode line 88 and the data line 84 respectively transmit a second common electrode signal φ and a data signal to the connected storage capacitor 98 and In the thin film transistor 94, each of the liquid crystal capacitors 96 receives a first common electrode signal, and at the same time, each of the common electrode lines 88 is short-circuited by the dummy line 90, and thus is in each common electrode line 88. The second common electrode signal is quite stable. Then, by using the scan line 86, the thin film transistor 94 of each row is sequentially controlled from top to bottom to receive the data signal, thereby controlling the charging and discharging of the liquid crystal capacitor 96, and the storage capacitor 98 connected to the liquid crystal capacitor 96 is used to maintain the liquid crystal capacitor 96. The potential difference between the two ends. Finally, referring to Fig. 12, the circuit design of the liquid crystal display panel of the present invention has an advantage that when the data line 842 is broken, the laser beam can be broken at the position of the dotted line box, At the position of the dotted circle, the first data line 842 is connected to the common electrode line 88 by using a laser, and the first virtual line 9〇2 can be used instead of the broken data line 842 to be repaired. rate. As described above, the present invention is not only capable of improving the pixel aperture ratio of the panel, but also short-circuiting the common electrode line and the dummy line to have better stability of the common signal, which is a practical invention. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, the shape, structure, and spirit of the present invention are equally varied. All should be included in the (4) patent scope 1374432 of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are circuit diagrams of a display panel of the prior art. FIG. 3 is a schematic diagram showing the circuit layout of the display panel of the prior art. 4 is a schematic view showing the circuit layout structure of the first embodiment of the liquid crystal display panel of the present invention. Fig. 5 is a partially enlarged schematic view showing the circuit layout structure of the first embodiment of the liquid crystal display panel of the present invention. Fig. 6 is a cross-sectional view showing the structure along the line A-A in the circuit layout structure of Fig. 5. Fig. 7 is a cross-sectional view showing the structure along the line B_B in the circuit layout structure of Fig. 5.
第8圖為本發明之竦晶顯示面板的第二實施例之電路佈局結構示意圖。 第9圖為本發明之液晶顯示面板的第三實施例之電路佈局結構:局部 放大示意圖。 ° 第10圖為本發明之液晶顯示面板的電路示意圖。 第11圖為本發明之賴極晝素單元的電路示意圖。 【主要元件符號說明】 第r I2”?狀液ί _邮進竹射賴後的電路示意圖Figure 8 is a schematic view showing the circuit layout structure of the second embodiment of the twin crystal display panel of the present invention. Figure 9 is a circuit layout structure of a third embodiment of the liquid crystal display panel of the present invention: a partially enlarged schematic view. ° Fig. 10 is a circuit diagram of the liquid crystal display panel of the present invention. Figure 11 is a circuit diagram of the immersed element unit of the present invention. [Main component symbol description] The r i2"? liquid ί _ postal into the bamboo after the circuit diagram
1〇薄膜電晶體 14資料線 18資料線 22共通電極線 26第一薄膜電晶體 30掃瞎線 33第一晝素電極 34虛擬線 36共通電極線 12掃瞄線 16薄膜電晶體 20虛擬線 24電極層 28第二薄膜電晶體 32資料線 35第二畫素電極 38透明基板 42絕緣層 40第一金屬層 44半導體層 11 1377423 46 第二金屬層 48 保護層 50 電極層 52 非晶矽層 54 歐姆接觸層 56 閘極 58 閘極 60 第一掃瞄線 62 第二掃猫線 64 共通電極線 66 源極 68 源極 70 汲極 72 汲極 74 虛擬線 78 資料線 80 第一通孔 81 第二通孔 82 第三通孔 84 資料線 842 第一資料線 86 掃瞒線 862 第一掃瞄線 864 第二掃瞄線 88 共通電極線 882 第一共通電極線 90 虛擬線 902 第一虛擬線 92 雙閘極晝素單元 922 第一薄膜電晶體 924 第二薄膜電晶體 925 第·一液晶電容 926 第一儲存電容 927 第二液晶電容 928 第二儲存電容 94 薄膜電晶體 96 液晶電容 98 儲存電容1〇 Thin film transistor 14 data line 18 data line 22 common electrode line 26 first thin film transistor 30 broom line 33 first halogen electrode 34 virtual line 36 common electrode line 12 scan line 16 thin film transistor 20 virtual line 24 Electrode layer 28 second thin film transistor 32 data line 35 second pixel electrode 38 transparent substrate 42 insulating layer 40 first metal layer 44 semiconductor layer 11 1377423 46 second metal layer 48 protective layer 50 electrode layer 52 amorphous germanium layer 54 Ohmic contact layer 56 gate 58 gate 60 first scan line 62 second sweep line 64 common electrode line 66 source 68 source 70 drain 72 drain 74 virtual line 78 data line 80 first through hole 81 Two-pass hole 82 third through hole 84 data line 842 first data line 86 broom line 862 first scan line 864 second scan line 88 common electrode line 882 first common electrode line 90 virtual line 902 first virtual line 92 double gate electrode unit 922 first film transistor 924 second film transistor 925 first liquid crystal capacitor 926 first storage capacitor 927 second liquid crystal capacitor 928 second storage capacitor 94 thin film transistor 96 liquid crystal The storage capacitor 98
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