1363418 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種半導體記憶裝置’特別是有關於一 種具有雙重溝槽電容的記憶裝置及其製造方法。 【先前技術】 隨著積體電路的發展技術日新月異，可攜式電子產 Φ 品’例如手機，具備了更多的功能。因此’使用於可攜式 電子產品内的高密度記憶裝置，例如低功率虛擬靜態隨機 存取記憶體（lower power pseudo SRAM )及/或低功率動離 . 隨機存取記憶體（lowerpowerDRAM)，必須能夠降低待 - 機電流（standby current)以延長電子產品的待機時間來應 付照相、音樂播放、或其他多媒體功能。 對於記憶裝置而言，更新電流（refresh current)佔了 一半以上的待機電流，而更新電流的大小又與資料保留日寺 間（retention time )的長短成反比與位元線的長短成正比 因此’增加資料保留時間及/或縮短位元線長度成為記憶果 置設計的重要的關鍵。 晶體與一個深溝槽 現今大多數的記憶單元是由一個電[Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a memory device having a dual trench capacitor and a method of fabricating the same. [Prior Art] With the rapid development of integrated circuit technology, portable electronic products such as mobile phones have more functions. Therefore, high-density memory devices used in portable electronic products, such as low-power virtual static random access memory (RAM) and/or low-power dynamic random access memory (lower power DRAM), must be used. It can reduce the standby current to extend the standby time of electronic products to cope with photography, music playback, or other multimedia functions. For a memory device, the refresh current accounts for more than half of the standby current, and the magnitude of the update current is inversely proportional to the length of the retention time of the data retention time and is proportional to the length of the bit line. Increasing data retention time and/or shortening bit line lengths is an important key to memory design. Crystals and a deep trench Most of the memory cells today are made up of one
容器所構成。在元件積集度要求越來越高的情況下，^ §己 憶單元與電晶體的尺寸需要大幅縮小，才可能製造出記愧 容量更高，處理速度更快的記憶體。在這種情形之下，端 短位元線長度將使記憶體的尺寸增加且更新電流的降巾昌有 96-064/0492-A41265-TW/final 1363418 限。因此，有人提出雙單元（twincell)記憶裝置。亦即， 記憶單元是由二個電晶體與二個深溝槽電容器所構成。此 種配置可藉由在二悔溝槽電容器儲存互補的資料信號來 有效降低因漏電所造成儲存資料的喪失，進而增加資料°保 留時間。再者，儲存的資料由深溝槽電容器對分，可有效 縮短寫入及讀取的時間，進而提高記憶體的逮度並降低工 作電壓H此種配置將使記㈣的尺寸增加，無法提 局記憶體積集度，而難以提升記憶體的記憶容量。 因此，有必要尋求一種新的記憶冑置結構’其能夠具 有雙早兀記憶裝置的優勢，且能夠縮小記憶裝置尺寸而改 善記憶體積集度。 【發明内容】 有鑑於此’本發明之目的在於提供一種具有雙重溝槽 電合的Z It裝置及其製造方法，其藉由使用雙重電晶體單 -閘極的電晶體結構與雙重溝槽電容組成一記憶單元，藉 以增加資料保㈣間’同時能夠縮小記憶裝置尺寸而改盖 記憶體積集度。 σ 祀據上述之目的，本發明提供一種具有雙重溝槽電容 的5己憶裝置，包括：—基底、二埋入式溝槽電容、以及-垂直電晶體結構。基底具有二深溝槽及-開口位於二深溝 槽之間纟中冰溝槽及開口彼此隔離。二埋入式溝槽電容 分別設置於深溝槽的下半部。垂直電晶體結構包括：一問 極電極、-閘極介電層、二源極區、以及二沒極區。閑極 96-064/0492-Α41265-TW/fmal 1363418 電極設置於開口内。閘極介電層設置於開口的側壁及底 部。二源極區分別設置於開口兩側的基底内且鄰近開口的 頂部。二汲極區分別設置於開口兩側的基底内且鄰近開口 的底部。其中，汲極區分別電性連接至埋入式溝槽電容。 又根據上述之目的，本發明提供一種具有雙重溝槽電 容的記憶裝置的製造方法，包括：提供一基底，具有二深 溝槽，且二深溝槽彼此隔離。在每一深溝槽下半部形成一 埋入式溝槽電容。在二深溝槽之間的基底内形成一開口， 且開口與深溝槽彼此隔離。在開口側壁及底部形成一閘極 介電層。在開口内形成一閘極電極。在開口兩側的基底内 且鄰近開口的底部形成二汲極區，以分別電性連接至埋入 式溝槽電容。在開口兩侧的基底内且鄰近開口的頂部分別 形成一源極區。 【實施方式】 以下配合第4F及5圖說明根據本發明實施例之具有雙 • 重溝槽電容的記憶裝置’例如低功率虛擬SRAM或低功率 DRAM，其中為了使第5圖更為清晰明瞭，僅繪示出些許 部件，例如位元線140、位元線接觸插塞138a及138b、深 溝槽對101a及101b、以及開口 120。在本實施例中，記憶 裝置包括：一基底100、複數埋入式溝槽電容、複數垂直 電晶體結構、複數字元線、以及複數位元線140。基底100, 例如一矽基底或其他半導體基底，具有由複數深溝槽對 101 a及10lb所構成的深溝槽陣列，其中深溝槽陣列的列 方向為位元線140的方向而行方向為字元線的方向。再 96-064/0492-A41265-TW/fmal 1363418 者，在列方向上兩相鄰的深溝槽對1 〇 1 a及10lb之間的基 底100内具有一開口 120，其中深溝槽對l〇la及101b及 開口 120彼此隔離。特別的是在本實施例的記憶裝置中’ 每一記憶單元的基底1〇〇包括：一開口 12〇以及位於開口 120兩侧的深溝槽101a及深溝槽l〇lb。 複數埋入式溝槽電容對應設置於深溝槽l〇la及l〇lb 的下半部，每一埋入式溝槽電容包括：埋入式下電極108、 一上電極112及介於兩電極及112之間的電容介電層 • 110。領型絕緣層106設置於每一深溝槽101a/101b的侧壁 且鄰近於上電極112頂部。複數隔離絕緣層118，對應設 置於每一深溝槽對101a及l〇lb的上半部。複數埋入帶層 (buried strap) 116，對應設置於每一深溝槽l〇la/101b内 ' 隔離絕緣層118與埋入式溝槽電容之間。 每一垂直電晶體結構包括：一字元線（由閘極電極127 及位於其上方的第二閘極電極129所構成）、一閘極介電 層124、一上蓋層13卜一絕緣間隙壁134、二源極區132、 鲁 二沒極區122、以及一隔離摻雜區121。閘極電極127設置 於開口 120内，可由摻雜的複晶矽所構成，而上方的第二 閘極電極129可由金屬或金屬石夕化物所構成。閘極介電層 124設置於開口 120的側壁及底部。上蓋層131設置於字 元線上方，而絕緣間隙壁134設置於字元線的側壁。二源 極區132分別設置於開口 120兩側的基底1〇〇内且鄰近開 口 120的頂部。二沒極區122分別設置於開口 120兩側的 基100内且鄰近開口 120的底部。其中，沒極區122藉由 96-064/0492-A41265-TW/fmal 1363418 對應的埋人帶層116而分別電性連接至埋人式溝槽電容。 隔離摻雜區121設置於開口 12〇下方的基底1〇〇内且與二 汲極區122相鄰。隔離摻雜區121與汲極區122具有不同 的導電型（N型或p型）。 位元線140平行設置於上蓋層131上方，其中二相鄰 的位疋線140，分別藉由位元線接觸插塞138a及13扑而 電性連接至直電晶體結構的二源極區1。 以下配合第1A至1B圖、第2A至2C圖、第3A至 圖、第4A至4F、及第5圖說明根據本發明實施例之具有Consisting of containers. In the case where the component integration requirements are getting higher and higher, the size of the cell and the transistor needs to be greatly reduced, and it is possible to manufacture a memory with a higher recording capacity and a faster processing speed. In this case, the length of the short bit line will increase the size of the memory and the current of the current will be 96-064/0492-A41265-TW/final 1363418. Therefore, a twin cell memory device has been proposed. That is, the memory unit is composed of two transistors and two deep trench capacitors. This configuration can effectively reduce the loss of stored data due to leakage by storing complementary data signals in the second-relay trench capacitor, thereby increasing the data retention time. Furthermore, the stored data is divided by deep trench capacitors, which can effectively shorten the writing and reading time, thereby improving the memory capture and reducing the operating voltage. H This configuration will increase the size of the memory (4) and cannot be improved. Memory volume is concentrated, and it is difficult to increase the memory capacity of the memory. Therefore, it is necessary to seek a new memory device structure which can have the advantages of a dual memory device and can reduce the size of the memory device to improve the memory volume. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a Zen device having dual trench junction and a method of fabricating the same by using a dual transistor single-gate transistor structure and a dual trench capacitor To form a memory unit, in order to increase the data protection (four), while reducing the size of the memory device and changing the memory volume. σ For the above purposes, the present invention provides a 5 memory device having a dual trench capacitor comprising: a substrate, a buried capacitor, and a vertical transistor structure. The substrate has two deep trenches and the opening is located between the two deep trenches. The ice trenches and openings are isolated from each other. The two buried trench capacitors are respectively disposed in the lower half of the deep trench. The vertical transistor structure includes: a polarity electrode, a gate dielectric layer, a two source region, and a second well region. Idle pole 96-064/0492-Α41265-TW/fmal 1363418 The electrode is placed in the opening. The gate dielectric layer is disposed on the sidewalls and the bottom of the opening. The two source regions are respectively disposed in the substrate on both sides of the opening and adjacent to the top of the opening. The dipole regions are respectively disposed in the substrate on both sides of the opening and adjacent to the bottom of the opening. The drain regions are electrically connected to the buried trench capacitors, respectively. Still in accordance with the above objects, the present invention provides a method of fabricating a memory device having dual trench capacitance, comprising: providing a substrate having two deep trenches and the two deep trenches being isolated from one another. A buried trench capacitor is formed in the lower half of each deep trench. An opening is formed in the substrate between the two deep trenches, and the opening and the deep trench are isolated from each other. A gate dielectric layer is formed on the sidewalls and the bottom of the opening. A gate electrode is formed in the opening. Diode regions are formed in the substrate on both sides of the opening and adjacent to the bottom of the opening to electrically connect to the buried trench capacitor, respectively. A source region is formed in each of the substrates on both sides of the opening and adjacent to the top of the opening. [Embodiment] Hereinafter, a memory device having a double-recessed trench capacitor, such as a low-power dummy SRAM or a low-power DRAM according to an embodiment of the present invention, will be described with reference to FIGS. 4F and 5, wherein in order to make FIG. 5 clearer, Only a few components are shown, such as bit line 140, bit line contact plugs 138a and 138b, deep trench pairs 101a and 101b, and opening 120. In this embodiment, the memory device includes a substrate 100, a plurality of buried trench capacitors, a plurality of vertical transistor structures, complex digital lines, and a plurality of bit lines 140. The substrate 100, such as a germanium substrate or other semiconductor substrate, has a deep trench array of complex deep trench pairs 101a and 10b, wherein the column direction of the deep trench array is the direction of the bit line 140 and the row direction is the word line. The direction. Further, 96-064/0492-A41265-TW/fmal 1363418, in the column direction, two adjacent deep trench pairs have an opening 120 in the substrate 100 between 1 〇 1 a and 10 lb, wherein the deep trench pair l〇la And 101b and opening 120 are isolated from each other. In particular, in the memory device of the present embodiment, the substrate 1 of each memory cell includes an opening 12 and a deep trench 101a and a deep trench 10b on both sides of the opening 120. The plurality of buried trench capacitors are correspondingly disposed in the lower half of the deep trenches l〇1a and 11b, and each of the buried trench capacitors includes a buried lower electrode 108, an upper electrode 112, and two electrodes And a capacitor dielectric layer between 112 and 110. A collar insulating layer 106 is disposed on the sidewall of each of the deep trenches 101a/101b and adjacent to the top of the upper electrode 112. A plurality of isolation insulating layers 118 are provided correspondingly to the upper half of each of the deep trench pairs 101a and 101b. A plurality of buried straps 116 are disposed between each of the deep trenches 10a/101b and between the isolation insulating layer 118 and the buried trench capacitor. Each vertical transistor structure comprises: a word line (consisting of a gate electrode 127 and a second gate electrode 129 located above), a gate dielectric layer 124, an upper cap layer 13 and an insulating spacer 134, a second source region 132, a Lu two-polar region 122, and an isolation doping region 121. The gate electrode 127 is disposed in the opening 120 and may be formed of a doped polysilicon, and the upper second gate electrode 129 may be composed of a metal or a metal compound. The gate dielectric layer 124 is disposed on the sidewalls and the bottom of the opening 120. The upper cap layer 131 is disposed above the word line, and the insulating spacer 134 is disposed on the sidewall of the word line. The two source regions 132 are respectively disposed in the substrate 1 两侧 on both sides of the opening 120 and adjacent to the top of the opening 120. The second well regions 122 are disposed in the base 100 on both sides of the opening 120 and adjacent to the bottom of the opening 120, respectively. The non-polar region 122 is electrically connected to the buried trench capacitor by the buried strap layer 116 corresponding to 96-064/0492-A41265-TW/fmal 1363418, respectively. The isolation doped region 121 is disposed in the substrate 1〇〇 below the opening 12〇 and adjacent to the second drain region 122. The isolation doping region 121 and the drain region 122 have different conductivity types (N-type or p-type). The bit lines 140 are disposed in parallel above the upper cap layer 131, wherein the two adjacent bit lines 140 are electrically connected to the two source regions 1 of the direct crystal structure by the bit line contact plugs 138a and 13, respectively. . Hereinafter, with reference to FIGS. 1A to 1B, 2A to 2C, 3A to 4, 4A to 4F, and 5, there is to be described with reference to an embodiment of the present invention.
雙重溝槽電容的記憶裝置製造方法。請參照第1A至、1B 圖’其中f 1A圖繪示出根據本發明實施例之具有用 憶裝置㈣溝槽陣列的基底平面示意圖，而f ib圖^ 示出/口第1A圖中’線的剖面示意圖。提供一基底1〇〇， 例如基錢其他半導體基底，其具有㈣數輯槽對 l〇la及l〇lb所構成的深溝槽陣列，其中深溝槽陣列的列 方向為位兀線14G的方向而行方向為字元線的方向。深溝 槽對101a及l〇lb可藉由形成於基底1〇〇上方的罩幕層定 義形，之。在本實施例中，罩幕層包括一塾氧化石夕層⑽ 及一虱化矽層104。另外，每一記憶單元的基底1〇〇包括： 深溝槽101a及深溝槽1〇lb，如第1A圖中由虛線圍成的區 域所示。 請參照第2Α至2C圖，其係繪示出根據本發明實施例 之埋入式溝槽電容的製造剖面示意圖。如第2a圖所示， 藉由習知製程步驟，在每一深溝槽對1〇la及1〇ib的上半 96-064/0492-A41265-TW/fmal 1363418 。卩形成領型絕緣層（collar insulator) 106且在下半部形成 埋入式下電極1〇8。舉例而言，將摻雜氣體藉由趨熱擴 散製程，使摻雜物擴散至深溝槽對101a及l〇lb下半部的 基底100中，而形成一擴散區，用以作為電容器之埋入式 下電極108。 然後，如第2B圖所示’於深溝槽對1〇la及1〇lb下半 部的側壁與底部形成電容介電層110，其為氮化矽層、氧 φ化矽-氮化矽（oxide-nitride，ON)的疊層結構、或是氧化 石夕氮化石夕-氧化矽（〇xide_nitride_〇xide，〇N〇)的疊層結 構。 . 接著’如第2C圖所示，於每一深溝槽對l〇la及101b .内填滿一推雜的複晶矽層（未繪示），並將摻雜的複晶矽 層回餘刻至—預定深度而完成埋人式溝槽電容的上電極 112的製作。 清參照第3A至3D圖’第3A圖係繪示出根據本發明 •實知例之定義埋入帶層區的平面示意圖，而第3B至3D圖 $ '會不出根據本發明實施例之埋人帶製造及主動區定義的 製以。]面不思圖。如第3八及3b圖所示，沿著深溝槽陣列 的仃方向形成複數平行排列的罩幕圖案層114，例如光阻 層以局^覆蓋每—深溝槽對l〇la及l〇lb。接著，進行 回似J Μ局部去除未被罩幕圖案層所覆蓋的領型絕 緣層106。 。接著’睛參照第3C圖，在每一埋入式溝槽 電容的上電 ° 7成埋入帶層1 16，例如摻雜的複晶石夕層。請 96-064/0492-Α41265-TW/fmal 11 1363418 參照第3D圖，藉由習知微影及蝕刻技術，在深溝槽陣列 的列方向上兩相鄰的深溝槽對l〇la及l〇lb之間定義出主 動區，而在每一深溝槽對l〇la及l〇lb上方定義出淺溝槽 隔離（shallow trench isolation，STI)區。接著，在主動區 的基底上方形成一絕緣材料（未繪示），例如氧化碎，並 填入淺溝槽隔離區。之後，可藉由化學機械研磨（chemical mechanic polishing，CMP )，去除多餘的絕緣材料及由氮化 矽層104與墊氧化矽層1〇2所構成的罩幕層，而在每一深 籲溝槽對101&及l〇lb的上半部形成一隔離絕緣層118。 請參照第4A至4F圖，其繪示出根據本發明實施例之 字元線及位元線的製造剖面示意圖。如第4A圖所示，在 深溝槽陣列的列方向上每兩相鄰的深溝槽對1〇1&及1〇lb • 之間的基底100内（即，主動區）形成與深溝槽l〇la/l〇lb 彼此隔離的一開口 120,以提供製作垂直電晶體結構之用。 如第4B圖所不，可藉由離子佈植製程，在開口 12〇 底部的基底1〇0内形成一隔離摻雜區121。可對基底1〇〇 實施-熱處理，使埋入帶層116因受熱而擴散至主動區的 基底100 Θ ’而在開C7 120兩側的基底1〇〇内且鄰近開口 120底部處形成與隔離摻雜區121相鄰的擴散區。此處， 擴散區係作為垂直電晶體結構的沒極區122，其導電型 (即’ N/P型）不同於隔離摻雜區的導電型。 如第4C圖所不’在每-開口 12㈣侧壁及底部形成一 問極介電層124，例如氧化石夕層。接著，在基底⑽及隔 離絕緣層118上形成一導電層以，例如掺雜的複μ層， 96-064/0492-Α41265-TW/fmal 12 1363418 並填入每一開口 120内。接著，在導電層126上依序形成 一導電層128及一絕緣層13〇。導電層128可由金屬戍金 屬矽化物所構成，而絕緣層130可由氧化矽、氮化矽或 如第4D圖所示，藉由習知微影及蝕刻技術，圖案化絕 緣層130,以形成具有字元線圖案的複數上蓋層131。接 著，以上蓋層131作為蝕刻罩幕，依序蝕刻下方的導電層 128及導電層126，以形成閘極電極127及第二閘極電^ 129。此處，閘極電極127及第二閘極電極129係作為記憶 裝置的字元線。接著，以上蓋層131作為佈植罩幕來進行 源極離子佈植’以在開口 120兩側的基底100内且鄰近開 口 120頂部處形成源極區132，其導電型相同於，沒極區 122的導電型。 接著，如第4E圖所示，在每一字元線的侧壁形成絕緣 間隙壁134。絕緣間隙壁134可由氧化石夕或氮化石夕所構成。 如此一來，便完成垂直電晶體結構的製作。之後，在間隙 壁134之間形成内層介電（interlayer dielectric，ILD)層 13 6，例如氧化石夕層。 接著，如第4F圖所示，在源極區132上方的内層介電 層136内形成二位元線導電插塞138a及138b，以與源極 區132電性連接。之後，在内層介電層136上，沿深溝槽 陣列的列方向形成平行排列且電性連接至位元線導電插塞 138a及138b的複數位元線140,如第5圖所示。如此一來， 便完成本實施例的記憶裝置製作。位元線140與導電插塞 96-064/0492-A41265-TW/fmal 13 1363418 138a及138b可由相同的材料所構成，例如鎢金屬，且可 藉由鑲嵌製程製作而成。另外，位元線140與導電插塞138a 及138b也可分別製作且可使用不同的金屬材料。須注意的 是導電插塞138a及138b分別電性連接至兩相鄰的位元線 140。因此，每一記憶單元由一垂直電晶體結構以及位於其 兩側的二埋入式溝槽電容。而每一記憶單元的埋入式溝槽 電容可藉由二位元線140寫入 根據本發明，每一記憶單元由一垂直電晶體結構以及 ® 位於其兩側的二埋入式溝槽電容。而每一記憶單元的埋入 式溝槽電容可藉由二位元線140儲存互補的資料信號來有 效降低漏電流對儲存資料的影響，進而增加資料保留時 間。再者，儲存的資料由深溝槽電容器對分，可有效縮短 ' 寫入及讀取的時間，進而提高記憶體的速度並降低工作電 壓。另外，由於每一記憶單元中二埋入式溝槽電容係共用 一字元線，因此相較於傳統雙單元記憶裝置而言，本實施 例之記憶裝置可具有較小的裝置尺寸而改善記憶體積集 鲁度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1A圖係繪示出根據本發明實施例之具有用於記憶 裝置的深溝槽陣列的基底平面示意圖； 96-064/0492-A41265-TW/fmal 14 1363418 第1B圖係繪示出沿第1A圖中l-Γ線的剖面示意圖； ' 第2Α至2C圖係繪示出根據本發明實施例之埋入式溝 . 槽電容的製造剖面示意圖； 第3Α圖係繪示出根據本發明實施例之定義埋入帶層 區的平面示意圖； 第3Β至3D圖係繪示出根據本發明實施例之埋入帶製 造及主動區定義的製造剖面示意圖； 第4Α至4F圖係繪示出根據本發明實施例之字元線及 籲 位元線的製造剖面示意圖；以及 第5圖係繪示出根據本發明實施例之具有雙重溝槽電 容的記憶裝置平面示意圖。 【主要元件符號說明】 100〜基底；101a、101b〜深溝槽；102〜墊氧化矽層； 104〜氮化矽層；106〜領型絕緣層；108〜埋入式下電極；110~ 電容介電層；112〜上電極；114〜罩幕圖案層；116〜埋入帶 • 層；118〜隔離絕緣層；120〜開口； 121〜隔離摻雜區；122〜 汲極區；124〜閘極介電層；126、128〜導電層；130〜絕緣 層；127〜閘極電極；129〜第二閘極電極；131〜上蓋層；132〜 源極區；134〜絕緣間隙壁；136~内層介電層；138a、138b〜 位元線導電插塞；140〜位元線。 96-064/0492-A41265-TW/final 15A method of manufacturing a memory device with a double trench capacitor. Please refer to FIGS. 1A to 1B, where f 1A is a schematic plan view of a substrate having a memory array using a memory device according to an embodiment of the present invention, and f ib is shown in FIG. Schematic diagram of the section. Providing a substrate, such as a base semiconductor, having a deep trench array of (4) a plurality of groove pairs l〇la and l〇lb, wherein the column direction of the deep trench array is in the direction of the bit line 14G The row direction is the direction of the word line. The deep groove pairs 101a and 101b can be defined by a mask layer formed above the substrate 1〇〇. In this embodiment, the mask layer comprises a layer of ruthenium oxide (10) and a layer of germanium germanium 104. Further, the substrate 1 of each memory cell includes: a deep trench 101a and a deep trench 1 lb as shown by a region surrounded by a broken line in Fig. 1A. Referring to Figures 2 to 2C, there are shown schematic cross-sectional views showing the fabrication of a buried trench capacitor in accordance with an embodiment of the present invention. As shown in Fig. 2a, by the conventional process steps, in each deep trench pair 1〇la and 1〇ib the upper half 96-064/0492-A41265-TW/fmal 1363418. The crucible forms a collar insulator 106 and forms a buried lower electrode 1〇8 in the lower half. For example, the doping gas is diffused into the substrate 100 of the lower half of the deep trench pair 101a and 10b by a thermal diffusion process to form a diffusion region for use as a capacitor. Lower electrode 108. Then, as shown in FIG. 2B, a capacitor dielectric layer 110 is formed on the sidewalls and the bottom of the deep trench pair 1〇1a and the lower half of the 1〇1b, which is a tantalum nitride layer and an oxygen yttrium-yttrium nitride layer ( A stacked structure of oxide-nitride, ON) or a laminated structure of oxidized cerium nitride-cerium oxide (〇xide_nitride_〇xide, 〇N〇). Then, as shown in Fig. 2C, each deep trench pair l〇la and 101b is filled with a doped polysilicon layer (not shown), and the doped polysilicon layer is returned. The fabrication of the upper electrode 112 of the buried trench capacitor is completed to a predetermined depth. 3A to 3D, FIG. 3A is a plan view showing a buried layer zone according to the definition of the present invention, and FIGS. 3B to 3D are not shown according to an embodiment of the present invention. Buried man-made belt manufacturing and active area definition system. I don't think about it. As shown in Figures 3 and 3b, a plurality of parallel-arranged mask pattern layers 114 are formed along the meandering direction of the deep trench array, such as a photoresist layer covering each of the deep trench pairs l〇la and l〇lb. Next, the collar-type insulating layer 106 which is not covered by the mask pattern layer is locally removed. . Next, referring to Fig. 3C, the dielectric layer 7 of each buried trench capacitor is buried into the layer 1 16, for example, a doped layer of the polycrystalline layer. Please refer to Figure 3D for the two adjacent deep trench pairs l〇la and l〇 in the column direction of the deep trench array by conventional lithography and etching techniques. An active region is defined between lbs, and a shallow trench isolation (STI) region is defined above each of the deep trench pairs l〇la and l〇lb. Next, an insulating material (not shown), such as oxidized ash, is formed over the substrate of the active region and filled into the shallow trench isolation region. Thereafter, the excess insulating material and the mask layer composed of the tantalum nitride layer 104 and the pad yttria layer 1〇2 may be removed by chemical mechanical polishing (CMP), and each deep groove is formed. An isolation insulating layer 118 is formed on the upper half of the pair of trenches 101 & Referring to Figures 4A through 4F, there are shown schematic cross-sectional views of the fabrication of word lines and bit lines in accordance with an embodiment of the present invention. As shown in FIG. 4A, in the column direction of the deep trench array, every two adjacent deep trenches are formed in the substrate 100 between the two adjacent deep trench pairs 1〇1 & and 1〇lb • (ie, the active region) and the deep trenches La/l〇l is an opening 120 that is isolated from each other to provide a vertical transistor structure. As shown in Fig. 4B, an isolation doping region 121 is formed in the substrate 1?0 at the bottom of the opening 12? by an ion implantation process. The substrate 1 may be subjected to a heat treatment to diffuse the buried belt layer 116 to the substrate 100 Θ ' of the active region due to heat, and is formed and isolated in the substrate 1 两侧 on both sides of the C7 120 and adjacent to the bottom of the opening 120 A diffusion region adjacent to the doped region 121. Here, the diffusion region serves as the non-polar region 122 of the vertical transistor structure, and its conductivity type (i.e., 'N/P type) is different from that of the isolation doped region. A dielectric layer 124, such as a oxidized stone layer, is formed on the sidewalls and bottom of each opening 12 (four) as shown in Fig. 4C. Next, a conductive layer is formed on the substrate (10) and the isolation insulating layer 118, for example, a doped complex layer, 96-064/0492-Α41265-TW/fmal 12 1363418, and filled into each opening 120. Next, a conductive layer 128 and an insulating layer 13 are sequentially formed on the conductive layer 126. The conductive layer 128 may be composed of a metal ruthenium metal ruthenium, and the insulating layer 130 may be formed of yttrium oxide, tantalum nitride or patterned as shown in FIG. 4D by conventional lithography and etching techniques to form The upper cap layer 131 of the word line pattern. Then, the upper cap layer 131 serves as an etching mask to sequentially etch the underlying conductive layer 128 and the conductive layer 126 to form the gate electrode 127 and the second gate electrode 129. Here, the gate electrode 127 and the second gate electrode 129 serve as word lines of the memory device. Next, the upper cap layer 131 serves as a seed mask to perform source ion implantation 'to form a source region 132 in the substrate 100 on both sides of the opening 120 and adjacent to the top of the opening 120, and the conductivity type is the same as that of the non-polar region. Conductive type of 122. Next, as shown in Fig. 4E, insulating spacers 134 are formed on the sidewalls of each of the word lines. The insulating spacer 134 may be composed of oxidized stone or cerium nitride. In this way, the fabrication of the vertical transistor structure is completed. Thereafter, an interlayer dielectric (ILD) layer 13, such as a oxidized layer, is formed between the spacers 134. Next, as shown in FIG. 4F, two bit line conductive plugs 138a and 138b are formed in the inner dielectric layer 136 above the source region 132 to be electrically connected to the source region 132. Thereafter, on the inner dielectric layer 136, a plurality of bit lines 140 arranged in parallel and electrically connected to the bit line conductive plugs 138a and 138b are formed along the column direction of the deep trench array, as shown in FIG. In this way, the memory device fabrication of the embodiment is completed. The bit line 140 and the conductive plug 96-064/0492-A41265-TW/fmal 13 1363418 138a and 138b may be formed of the same material, such as tungsten metal, and may be fabricated by a damascene process. In addition, the bit line 140 and the conductive plugs 138a and 138b can also be fabricated separately and different metal materials can be used. It should be noted that the conductive plugs 138a and 138b are electrically connected to two adjacent bit lines 140, respectively. Therefore, each memory cell consists of a vertical transistor structure and two buried trench capacitors on either side of it. The buried trench capacitor of each memory cell can be written by the two bit line 140 according to the invention, each memory cell consisting of a vertical transistor structure and two buried trench capacitors on both sides thereof. . The buried trench capacitor of each memory cell can store the complementary data signal by the two bit line 140 to effectively reduce the influence of the leakage current on the stored data, thereby increasing the data retention time. Furthermore, the stored data is divided by deep trench capacitors, which can effectively shorten the time of writing and reading, thereby increasing the speed of the memory and reducing the operating voltage. In addition, since the two buried trench capacitors share a word line in each memory cell, the memory device of the embodiment can have a smaller device size and improve memory than the conventional two-cell memory device. Volume set Ludu. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic plan view of a substrate having a deep trench array for a memory device according to an embodiment of the present invention; 96-064/0492-A41265-TW/fmal 14 1363418 1B FIG. 2A to 2C are schematic cross-sectional views showing the manufacturing of a buried trench according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the manufacturing of a trench capacitor according to an embodiment of the present invention; A schematic plan view of a buried belt zone according to an embodiment of the present invention; FIGS. 3A to 3D are schematic cross-sectional views showing the manufacturing of the buried tape and the active zone definition according to an embodiment of the present invention; FIGS. 4 to 4F A schematic cross-sectional view of a word line and a bit line in accordance with an embodiment of the present invention is shown; and FIG. 5 is a plan view of a memory device having a dual trench capacitor in accordance with an embodiment of the present invention. [Description of main components] 100~substrate; 101a, 101b~deep trench; 102~pad oxide layer; 104~ tantalum nitride layer; 106~ collar type insulating layer; 108~buried lower electrode; 110~ capacitor dielectric Electrical layer; 112~ upper electrode; 114~ mask pattern layer; 116~ buried tape layer; 118~ isolation insulating layer; 120~ opening; 121~ isolation doped region; 122~ drain region; 124~ gate Dielectric layer; 126, 128~ conductive layer; 130~ insulating layer; 127~ gate electrode; 129~ second gate electrode; 131~ upper cap layer; 132~ source region; 134~ insulating spacer; Dielectric layer; 138a, 138b~ bit line conductive plug; 140~bit line. 96-064/0492-A41265-TW/final 15