TWI356962B - Substrate for display device, manufacturing method - Google Patents
Substrate for display device, manufacturing method Download PDFInfo
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- TWI356962B TWI356962B TW099146408A TW99146408A TWI356962B TW I356962 B TWI356962 B TW I356962B TW 099146408 A TW099146408 A TW 099146408A TW 99146408 A TW99146408 A TW 99146408A TW I356962 B TWI356962 B TW I356962B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/50—Protective arrangements
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
1356962 六、發明說明: 專利申請第 之整體已含 本專利乃依2004年5月25曰申請之日本國 2004-154506號而主張優先權者。該申請内容 於本專利中作為參照。 【發明所屬之技術領域】 本發明關於顯示裝置用基板、其製造方法及顯示裝置。 更詳細而言,本發明關於適用於液晶顯示裝置等之顯示 置用基板、其製造方法及具有其之顯示裝置。 丁裝 【先前技術】 目前,液晶顯示裝置具有小型、薄型、低消費電力及軻 量的特徵,被廣泛於用於各種電子設備、尤其,將開關元 件作為主動元件之主動矩陣型液晶顯示裝置(液晶顯示^ 板),由於可得到與CRT(Cath〇d Ray Tube;陰極射線管)相 同之顯示特性,因此,廣泛地被應用於個人電腦等之〇A 設備、電視等之AV設備 '行動電話等。上述般的液晶顯 示裝置,近年來,在大型化、高精細化、像素有效面積比 率提升(高開口率)等之品質提升上急速地取得進展。因 此’被用於液晶顯示裝置等之顯示裝置的顯示裝置用基板 同樣地亦被要求更進一步的高性能化’推動設計面、製造 技術面等之改良。 作為顯示裝置用基板,主動矩陣式基板被廣泛地用於液 晶顯示裝置等。作為主動矩陣式基板之製造技術,已知有 在基板上將像素電極及源極線(信號線)形成於同一平面上 之技術,在此技術中,如欲實現高精細化及高開口率的 153051.doc s為了增加有效像素區域,乃採以像素與源極線之距離 =縮短、源極線之細線化等。然而,如縮短像素與源極線 間之距離的話,容易發生短路不良,如細線化源極線的 話,容易發生斷線不良。亦即,在基板上將像素電極及源 極線形成於同—平面上之主動矩陣之製造技術中,對於因 短路不良之發生“導致產能降低—事,仍有 間。 因此’為了防止此等短路不良及斷線不良,從而改善 f能降低,關於主動矩陣式基板之製造方法,例如已被 提案具有如下⑷至⑷所示之特徵的穿透型液晶顯示裝置 之製造方法(例如’參照特開平9_152625號公較(第⑴ 頁))。 ⑷在形成開關元件(主動元件)及源極配線(源極線)後, 配置(透明)層間絕緣膜。 (b)使開關元件與(透明)像素電極經由接觸孔接觸 接)。 0)藉在層間絕緣膜上形成像素電極’使源極配線與像素 電極由同一平面分離。 液晶顯示裝置係使上述般地製成之主動料式基板相向 地貼合彩色濾光片基板,在此等基板與基板間注入液晶而 製成。作為钐色濾光片基板,例如有將R(紅)、G(綠j、 B(藍)之色區域會被設成與主動矩陣式基板側之像素區域 致,並且,將黑矩陣(遮光膜)設於各像素區域以外之部 分者。 153051.doc 1356962 圖13係以往之主動矩陣式基板(薄膜電晶體陣列基板)中 之一像素及位於與其相鄰位置之像素之一部分的平面模式 圖。如圖13所示,主動矩陣式基板13〇之一像素中,閘極 線(掃描線)101及源極線(信號線)1〇2被配置成彼此交又。 在3玄父叉部分,配置有作為開關元件之薄膜電晶體(以下 稱為TFT)114及像素電極103。TFTU4由被連接於閘極線 101之閘極104、被連接於源極線1〇2之源極1〇5、被連接於 像素電極103之汲極1〇6、及島狀之半導體層125所形成、 像素電極103上,介以接觸孔1〇9,連接有汲極引出電極 106。此外,汲極引出電極丨〇6,隔著閘極絕緣膜11〗而與輔 助電容線107相向,從而形成輔助電容。 接著,就關於主動矩陣式基板,尤其有關於薄膜電晶體 陣列基板之製造方法,以圖13至17簡單加以說明。此外, 圖14係圖13所示之薄膜電晶體陣列基板之H-H,線之箭頭方 向。面圖,圖15係圖丨3所示之薄膜電晶體陣列基板之乙工, 線之箭頭方向剖面圖。圖16係閘極線外部引出端子之平面 概略圖’圖17係源極線外部引出端子之平面概略圖。 在製造薄膜電晶體陣列基板時,首先,在由玻璃等之透 ^緣基板所形成之基板11〇上藉由成膜、光刻及姓刻 5升^成閘極(掃描線)1 〇 1、閘極104、及輔助電容線 107。 接著,在此等上,成膜由閘極絕緣膜111、活性半導體 層 1 12、N 刑a t — 非Ba妙專所形成之低電阻半導體層113,並以 光刻、蝕刻形成為島狀125。 153051.doc 接者’藉由成膜、光刻及钱刻來同時形成源極線ι〇2、 源極105、沒極1〇6、及汲極引出電極⑽,並且,連續地 對低:阻半導體層113施以源極暨汲極分離蝕刻。 =者,成冑出由SiNx等形成之下層層間絕緣膜12〇來被 '正面接著,藉由光刻由感光性丙烯酸樹脂等形成之上 运有機層間絕緣膜115,形成為具有:接觸孔^⑽用圖案、 ^極線外部^端子接點用圖案(圖ΐ6^χ)、及源極線外 部弓丨出端子接點用圖案(圖17之Y)。 接著,為了形成接觸孔109、閘極線外部引出端子2〇〇、 ’二、良外np引出端子300,以上層有機層間絕緣膜11 5為 掩模二連續地钕刻下層層間絕緣膜12〇及閘極絕緣膜⑴。 接著被覆接觸孔1 09、閘極線外部引出端子2〇〇及源極 線外部引出端子300般地,形成像素電極1G3、閘極線外部 引出端子200之最上層電極2〇1及源極線外部引出端子3〇〇 之最上層電極301。此外,藉由接觸孔1〇9, TFTU4之汲極 106與像素電極103會介汲極引出電極丨〇6,而連接。 藉由上述之製造方法,在主動矩陣式基板上,可將源極 線102及像素電極1〇3隔著層間絕緣膜115、12〇來加以分 離。藉由源極線1〇2及像素電極1〇3之分離,不僅可防止像 素電極103與源極線丨〇2之短路所致之產能下滑並且,如 圖13所示般地’可重疊像素電極103及源極線1〇2,因此, 可改善液晶顯示裝置等之開口率。 然而’上述之顯示裝置用基板之製造方法中,當上層有 機層間絕.緣膜發生膜缺損肖,下層絕緣膜及閘極絕緣膜會 153051.doc 1356962 被以膜缺損部分蝕刻’而與在上層有機層間絕緣膜上形成 之像素電極短路,構成顯示缺陷,顯示裝置之品質降低, 產能下降,由此看來仍有改善之空間。 關於以往之顯示裝置用基板,已提案有閘極絕緣層為由 氧化金屬膜之氧化絕緣層及閘極絕緣膜形成之雙層構造的 技術(例如,參照特開平3_153217號公報(第i、3頁))。然 而,即使藉此技術來多層化絕緣層,在以最上層層間絕緣 膜作為掩模而蝕刻去除存在於比最上層還下層的絕緣獏的 情況中,無法得到防止因為層間絕緣膜缺陷導致短路缺陷 的效果。此外,此技術為針對閘極絕緣膜之膜缺損的對策 技術,然而,並非對像素電極形成於層間絕緣膜上之顯示 裝置用基板中存在於閘極線、源極線等之配線與像素電極 間存在之絕緣膜缺損所致之漏電而發生之像素缺陷的對策 技術。 【發明内容】 本發明為有鑑於上述現狀者,其目的在於提供顯示裝置 用基板、其製造方法、及使用其之顯示裝置,其特別可在 製作高開口率之顯示裝置用基板時’防止像素電極與掃描 線、信號線等之配線的短路,從而能以高產能得到高顯示 品質之顯示裝置。 本發明人等在對高精細、高開口率,並能以高產能得到 高顯示品質之顯示裝置的顯示裝置用基板進行種種探討 時’發現在以往之基板構造中,掃描線(閘極匯流排線)、 信號線(源極匯流排線)等之配線與像素電極在平面上重疊 J5305J.doc 1356962 之區域(由基板面垂直方向來 於德去^ ;^之£域)内’有時會發 在…,下之(上層)層間絕緣膜剝離等之膜缺陷, 二況巾在以(上層)層間絕緣膜為掩模進行蝕刻時, =刀之間極絕緣膜等會被㈣,使得掃描線 '信號線 (源極匯流排線)等之绫 ’ 配線θ路出,稭由之後的像素電極之 :暨圖案化’露出之配線會與像素電極接觸,從而導致 缺陷發生。亦即,上述般的配線與像素電極的漏電發1356962 VI. INSTRUCTIONS: The patent application number is included in the whole. This patent claims the priority according to Japanese Patent No. 2004-154506 filed on May 25, 2004. This application is incorporated herein by reference. [Technical Field of the Invention] The present invention relates to a substrate for a display device, a method of manufacturing the same, and a display device. More specifically, the present invention relates to a display substrate suitable for use in a liquid crystal display device or the like, a method of manufacturing the same, and a display device having the same. Ding [Prior Art] At present, liquid crystal display devices are characterized by small size, thin type, low power consumption and high power consumption, and are widely used in active matrix type liquid crystal display devices for various electronic devices, in particular, switching elements as active elements ( The liquid crystal display panel (LCD) is widely used in personal computers, such as A-devices, TVs, etc., because it has the same display characteristics as CRT (Cath〇d Ray Tube). Wait. In the above-mentioned liquid crystal display device, in recent years, progress has been rapidly progressed in quality improvement such as enlargement, high definition, and improvement in pixel effective area ratio (high aperture ratio). Therefore, the substrate for a display device used in a display device such as a liquid crystal display device is also required to further improve the performance of the design surface, the manufacturing technology, and the like. As a substrate for a display device, an active matrix substrate is widely used for a liquid crystal display device or the like. As a manufacturing technique of an active matrix substrate, a technique of forming a pixel electrode and a source line (signal line) on the same plane on a substrate is known. In this technique, if high definition and high aperture ratio are desired, 153051.doc s In order to increase the effective pixel area, the distance between the pixel and the source line is shortened, and the thin line of the source line is thinned. However, if the distance between the pixel and the source line is shortened, short-circuit defects are likely to occur, and if the source line is thinned, the disconnection is likely to occur. In other words, in the manufacturing technique of forming an active matrix in which the pixel electrode and the source line are formed on the same plane on the substrate, there is still room for the occurrence of a short-circuit defect, which causes a decrease in productivity. Therefore, in order to prevent such In the manufacturing method of the active matrix substrate, for example, a manufacturing method of the transmissive liquid crystal display device having the characteristics shown in the following (4) to (4) is proposed (for example, 'refer to Kaiping No. 9_152625 (page (1)). (4) After forming the switching element (active element) and the source wiring (source line), the (transparent) interlayer insulating film is placed. (b) The switching element is made (transparent) The pixel electrode is contacted via the contact hole. 0) The pixel electrode is formed on the interlayer insulating film to separate the source wiring from the pixel electrode by the same plane. The liquid crystal display device is configured such that the active substrate prepared in the above manner is opposed to each other. A color filter substrate is bonded, and liquid crystal is injected between the substrate and the substrate. As the color filter substrate, for example, R (red) and G (green j, B (blue) are used. The color region is set to be a pixel region on the active matrix substrate side, and a black matrix (light shielding film) is provided in a portion other than each pixel region. 153051.doc 1356962 FIG. 13 is a conventional active matrix substrate ( A planar pattern diagram of one of the pixels in the thin film transistor array substrate and a portion of the pixel located adjacent thereto. As shown in FIG. 13, one of the active matrix substrates 13 闸, the gate line (scanning line) 101 And the source line (signal line) 1〇2 are arranged to overlap each other. A thin film transistor (hereinafter referred to as TFT) 114 and a pixel electrode 103 as switching elements are disposed in the 3d-parent portion. The TFTU4 is connected. The gate 104 of the gate line 101, the source 1〇5 connected to the source line 1〇2, the drain 1〇6 connected to the pixel electrode 103, and the island-shaped semiconductor layer 125 are formed, and the pixel is formed. On the electrode 103, a drain electrode 106 is connected via a contact hole 1〇9. Further, the drain electrode 6 is opposed to the storage capacitor line 107 via a gate insulating film 11 to form an auxiliary capacitor. Next, about the active matrix The board, in particular, the manufacturing method of the thin film transistor array substrate, will be briefly described with reference to Figs. 13 to 17. In addition, Fig. 14 is the HH of the thin film transistor array substrate shown in Fig. 13, the direction of the arrow of the line. Figure 15 is a cross-sectional view of the thin-film transistor array substrate shown in Figure 3, and the arrow direction of the line. Figure 16 is a schematic plan view of the external terminal of the gate line. Figure 17 is a schematic outline of the external terminal of the source line. In the manufacture of a thin film transistor array substrate, first, a film is formed on a substrate 11 formed of a transparent substrate such as glass by a film formation, photolithography, and a 5 liter gate (scanning line). 〇1, gate 104, and auxiliary capacitance line 107. Next, a low-resistance semiconductor layer formed of the gate insulating film 111, the active semiconductor layer 12, and the N-type 113, and formed into an island shape 125 by photolithography and etching. 153051.doc The receiver's film source, photolithography and money engraving simultaneously form the source line ι2, the source 105, the gate 1〇6, and the drain electrode (10), and continuously to the low: The resistive semiconductor layer 113 is subjected to source and drain separation etching. In the case where the interlayer insulating film 12 is formed by SiNx or the like, the interlayer insulating film 12 is formed as a front surface, and an organic interlayer insulating film 115 is formed by photolithographic acrylic resin or the like by photolithography, and is formed to have a contact hole. (10) Use the pattern, the pattern of the external electrode terminal contact (Fig. 6^χ), and the outer line of the source line to pull out the pattern of the terminal contact (Y in Fig. 17). Next, in order to form the contact hole 109, the gate external lead terminal 2〇〇, the 'two, the good outer np lead terminal 300, the upper organic interlayer insulating film 11 5 is used as a mask 2 to continuously etch the lower interlayer insulating film 12〇 And gate insulating film (1). Then, the contact hole 109, the gate external lead terminal 2, and the source line external lead terminal 300 are formed to form the pixel electrode 1G3, the uppermost electrode 2〇1 of the gate external lead terminal 200, and the source line. The uppermost layer electrode 301 of the external lead terminal 3〇〇. Further, by the contact holes 1〇9, the drain electrode 106 of the TFTU4 and the pixel electrode 103 are connected to the drain electrode 6 by the drain electrode. According to the above manufacturing method, the source line 102 and the pixel electrode 1〇3 can be separated from each other via the interlayer insulating films 115 and 12 on the active matrix substrate. By the separation of the source line 1〇2 and the pixel electrode 1〇3, not only the capacity loss caused by the short circuit between the pixel electrode 103 and the source line 丨〇2 but also the “overlapping pixels” as shown in FIG. 13 can be prevented. Since the electrode 103 and the source line 1 are 2, the aperture ratio of the liquid crystal display device or the like can be improved. However, in the above-described method for manufacturing a substrate for a display device, when a film defect occurs between the upper organic layer, the underlying insulating film and the gate insulating film are etched by the film defect portion and the upper layer is 153051.doc 1356962 The pixel electrode formed on the organic interlayer insulating film is short-circuited to constitute a display defect, the quality of the display device is lowered, and the productivity is lowered, and thus there is still room for improvement. In the conventional display device substrate, a technique in which the gate insulating layer is a two-layer structure formed of an oxide insulating layer and a gate insulating film of a metal oxide film has been proposed (for example, see Japanese Patent Laid-Open No. Hei No. Hei. page)). However, even if the insulating layer is multilayered by this technique, in the case where the insulating layer which is present in the lower layer than the uppermost layer is etched and removed by using the uppermost interlayer insulating film as a mask, it is impossible to prevent short-circuit defects due to defects of the interlayer insulating film. Effect. In addition, this technique is a countermeasure against a film defect of a gate insulating film. However, it is not a wiring and a pixel electrode existing in a gate line, a source line, or the like in a substrate for a display device in which a pixel electrode is formed on an interlayer insulating film. A countermeasure technique for pixel defects that occur due to leakage due to insulation film defects. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the invention is to provide a substrate for a display device, a method for manufacturing the same, and a display device using the same, which can particularly prevent a pixel when a substrate for a display device having a high aperture ratio is produced. The electrode is short-circuited with the wiring such as the scanning line or the signal line, so that a display device with high display quality can be obtained with high productivity. When the present inventors have conducted various investigations on a substrate for a display device having a high-definition, high aperture ratio, and a display device having high display quality with high productivity, it has been found that in the conventional substrate structure, the scanning line (gate busbar) The wiring of the line), the signal line (source bus line), etc. overlaps the pixel electrode on the plane J5305J.doc 1356962 (from the vertical direction of the substrate surface to the area of the ^^^^) When the film is etched under the (upper layer) interlayer insulating film, the second insulating film is etched with the (upper layer) interlayer insulating film as a mask. Line 'signal line (source bus line), etc.' wiring θ out, straw from the subsequent pixel electrode: cum patterned 'exposed wiring will contact the pixel electrode, resulting in defects. That is, the above-mentioned wiring and the leakage of the pixel electrode
時’被寫人之像素電位將無法保持,成為顯示裝置中之 :缺陷。為此’發現作為對蝕刻之保護膜,藉由在掃描 卷、k號線(源極匯流排線)等之配線的上層上設置保護 層’可防止像素電極與配線之接觸,從而可防止藉此等短 路所致,漏電缺陷。例如,發現藉由在掃描線及像素電極 平面重$之區域上配置構成開關元件之半導體層之圖案的 即使層間絕緣膜剝離’此半導體層圖案會成為钱刻保 護膜’無需增加基板製造工序,便可防止像素電極及掃描 線之漏電,能以高產能來提供高精細、高開口率之液晶顯 不裝置等之顯示裝置,想到可非常有技巧地解決上述問 題’從而得到本發明。 亦即本發明為絕緣性基板上具有掃描線、信號線及開 關元件,並進一步具有層間絕緣膜及像素電極之顯示裝置 用基板’且上述開關元件被設於掃描線與信號線交叉的交 叉部,具有被連接於掃描線之閘極、被連接於信號線之源 極及被連接於像素電極之及極,上述層間絕緣膜具有使 開關元件之沒極與像素電極連接之接觸孔,上述顯示裝置 153051.doc 1356962 用基板為在掃描線及/或信號線上層上設有保護層者。 本發明亦為絕緣性基板上具有掃描線、信號線、辅助電 容線及開關元件,並進一步具有層間絕緣膜及像素電極之 顯示裝置用基板,且上述開關元件被設於掃描線與信號線 交叉的交叉部’具有被連接於掃描線之閘極'被連接於信 號線之源極、及被連接於像素電極之汲極,上述層間絕緣 膜具有使開關元件之汲極與像素電極連接之接觸孔,上述 顯不裝置用基板為在掃描線、信號線及輔助電容配線所形 成之群組中選出之至少一個配線之上層上設有保護層者。 【實施方式】 本發明之顯示裝置用基板係具有(A)在絕緣性基板上備 有掃描線、信號線及開關元件,並進一步備有層間絕緣臈 及像素電極的構造者,或(B)在絕緣性基板上備有掃描 線' 信號線、輔助電容配線及開關元件,並進一步備有^ 間絕緣膜及像素電極的構造者。上述(A)的構造中,以具 有依序為⑴絕緣性基板、⑺掃描線、信號線及開關^ 件' ⑴層間絕緣膜、⑷像素電極等之層積構造為佳,具 體而言,以信號線及掃描線設於絕緣性基板上,信號線及 掃描線交叉之每一交又部上設有開關元件及像素電極^信 號線 '掃描線及開關元件之上部設有層間絕緣膜,層門; 緣膜上設有像素電極之方式為佳。上述(B)構造中二 有依序為⑴絕緣性基板、⑺掃描線、信號線、輔助電: 配線及開關元件、(3)層間絕緣膜、(4)像素電 : 構造為佳。 續積 153051.doc 1356962^ 上述開關元件被設於掃描線與信號線交叉之交又部上, 具有被連接於掃描線之閘極、被連接於信號線之源極'及 被連接於像素電極之汲極。此外,通常,掃描線(閘極)、 信號線(源極)及汲極之間形成有閘極絕緣膜。此外,層間 絕緣膜具有使開關元件之汲極與像素電極連接之接觸孔。At the time of writing, the pixel potential of the person to be written cannot be maintained, and it becomes a defect in the display device. For this reason, it has been found that, as a protective film for etching, a protective layer is provided on the upper layer of wiring such as a scanning roll or a k-line (source bus bar) to prevent contact between the pixel electrode and the wiring, thereby preventing borrowing These short circuits are caused by leakage defects. For example, it has been found that even if the interlayer insulating film is peeled off by disposing the pattern of the semiconductor layer constituting the switching element in the region of the scanning line and the pixel electrode plane weight, the semiconductor layer pattern becomes a protective film, and there is no need to increase the substrate manufacturing process. It is possible to prevent leakage of the pixel electrode and the scanning line, and to provide a display device such as a liquid crystal display device having a high definition and a high aperture ratio with high productivity, and it is thought that the above problem can be solved very skillfully. In other words, the present invention is a substrate for a display device having a scanning line, a signal line, and a switching element, and further having an interlayer insulating film and a pixel electrode, and the switching element is provided at an intersection of a scanning line and a signal line. a gate connected to the scan line, a source connected to the signal line, and a gate connected to the pixel electrode, wherein the interlayer insulating film has a contact hole for connecting the gate of the switching element to the pixel electrode, and the display Device 153051.doc 1356962 The substrate is a layer provided with a protective layer on the scan line and/or signal line layer. The present invention is also a substrate for a display device having a scanning line, a signal line, a storage capacitor line, and a switching element, and further having an interlayer insulating film and a pixel electrode, and the switching element is provided on the scanning line and the signal line. The intersection portion 'having a gate connected to the scan line' is connected to the source of the signal line and the drain connected to the pixel electrode, and the interlayer insulating film has a contact for connecting the drain of the switching element to the pixel electrode In the hole, the substrate for the display device is provided with a protective layer on the upper layer of at least one of the groups selected from the group consisting of the scanning line, the signal line, and the auxiliary capacitor line. [Embodiment] The substrate for a display device of the present invention has (A) a structure in which a scanning line, a signal line, and a switching element are provided on an insulating substrate, and further includes an interlayer insulating layer and a pixel electrode, or (B) A scanning line 'signal line, a storage capacitor line, and a switching element are provided on the insulating substrate, and a structure of an insulating film and a pixel electrode is further provided. In the structure of the above (A), it is preferable to have a laminated structure of (1) an insulating substrate, (7) a scanning line, a signal line, and a switch member (1) an interlayer insulating film, (4) a pixel electrode, etc., specifically, The signal line and the scan line are disposed on the insulating substrate, and each of the intersection of the signal line and the scan line is provided with a switching element and a pixel electrode. The signal line 'the scanning line and the upper part of the switching element are provided with an interlayer insulating film. The door is provided with a pixel electrode on the film. In the above (B) structure, the order is (1) an insulating substrate, (7) a scanning line, a signal line, an auxiliary power: a wiring and a switching element, (3) an interlayer insulating film, and (4) a pixel electric: a structure is preferable. Continuation 153051.doc 1356962^ The switching element is disposed on the intersection of the scan line and the signal line, has a gate connected to the scan line, is connected to the source of the signal line', and is connected to the pixel electrode Bungee jumping. Further, in general, a gate insulating film is formed between the scanning line (gate), the signal line (source), and the drain. Further, the interlayer insulating film has a contact hole for connecting the drain of the switching element to the pixel electrode.
本發明之顯示裝置用基板中,由於為上述般之構造,不 僅可藉由流經掃描線之電流(閘極信號)來進行開關元件之 驅動控制,並可在開關元件為開(ON)狀態時,藉由流經信 號線之電流(資料信號)來進行像素電極之驅動控制,此 外,藉層間絕緣膜則可防止像素電極與信號線之短路等。 依本發明,在上述(A)之構造中,掃描線及/或信號線上 層設有保護層,在上述(B)之構造中,由掃描線、信號線 及輔助電容配線形成之群組中選出之至少—配線之上層設 有保護層。亦即,本發明中,至少掃描線、信號線或辅助 電容配線中之任一者上層設有保護層。藉此,在進行為了 層間絕緣膜之接觸孔形忐^ 较蜩札办成荨之蝕刻時,保護層對蝕刻而言 會起作用為保護膜,因此,g站Λ、 U此即使成為蝕刻掩模之層間絕緣 膜之圖案中一部分發生膜缺μ达、。丄 生瞑缺的情況中,仍可防止蝕刻後 之掃描線等之配線露出。依此社 此果’可防止層間絕緣膜上 之像素電極與掃描線等之綠 氷寻之配線接觸而防止短路,因此,可 防止像素缺陷之發生,特別在 一 一 农忭阿精細、咼開口率之顯 不裝置用基板時,可提升所媒夕瓶_ 扠幵所侍之顯不品質及產能。 作為上述保護層,如可發禮陡l β 播 軍防止在層間絕緣膜之蝕刻時 知也線4之配線露出之作用 作用成效的話,材質及厚度等並無 153051.doc Ϊ356962 特别之限疋&外,保護層如可在姓刻時保護該下層部分 的話,即使以與相鄰之其他層,例如層間絕緣膜及間㈣ 緣膜相同的材料構造亦可,在此情況中,在剖面形狀上, 保護層與相鄰之其他層會一體化,如難以判別層之邊界的 治,错由確認與保護層相鄰之其他層之平面形狀之差显, 即-體化之部分(保護層+相鄰之其他層)與未一體化之部 =僅保護層或僅相鄰之其他層)的厚度差異,便可判別保 邊層。 此外’本發明中’「上層上設有保護層」-事,可指在 掃描線等之配線之-層上層上,將保護層設成與掃描線等 之配線接觸’或指在掃描線等之配線之複數層上層上,將 保護層設置成不會與掃描線等之配線接觸。例如,作為保 護層被設置成不與掃描線接觸之方式,舉例來說有在閘極 絕緣膜上設置保護層之方式、在層間絕緣膜中設置保護層 之方式等。 尽 接著’說明本發明之顯示裝置用基板包含之保護層以外 之各構成材料。 ,作為絕緣性基板,適用的為由玻璃等之透明的絕緣體所 形成者。 作為掃描線、信號線及輔助電容配線之材料,如為可得 到所需之配線電阻者的話,並無特別之限制,例如可1 = (Ta)、鈦(Ti)、鉻(C〇、鋁(A1)等之金屬、此等金屬 金、或將此等層積而成之Ti/A丨/Ti等之層積膜等。掃二 線、信號線及輔助電容配線之寬度、厚度'圖案形狀等田 153051 .doc •12- 1356962 並無特別之限制。 作為開關元件,如五目女 為具有間極、源極及没極者的話,並 …特別之限制,舉例來却 A _ 薄膜電晶體、聚J 為非…膜電晶體、微晶碎 sn. . 4 矽缚膜電晶體、CGs(c〇ntinuous Grain lc〇n,連續粒界結晶矽)薄膜電晶體等、此外 =極會與掃料-體成形,源極及沒極會與㈣線—體成 作為層間絕緣膜之材料,如為可得到所需之介電率、穿 來^可=選擇比等之材料的話,並無特別之限制,舉例 為=W(SlNx)、感光性透明樹脂、氧化邦叫 =可用於層間絕緣膜之感光性透明樹脂,例如有丙 :樹脂、環氧系樹脂,、聚亞胺醋系樹脂、聚硫亞醯系 ^脂專。作為層間絕緣膜,可為由旧構成者,亦可為由2 層以上構成者,厚度等並無特別限制。In the substrate for a display device of the present invention, the above-described structure can drive control of the switching element not only by the current flowing through the scanning line (gate signal) but also in the ON state of the switching element. At the time, the driving control of the pixel electrode is performed by the current (data signal) flowing through the signal line, and the interlayer insulating film prevents the short circuit between the pixel electrode and the signal line. According to the invention, in the structure of the above (A), the scan line and/or the signal line layer are provided with a protective layer, and in the structure of the above (B), the scan line, the signal line, and the auxiliary capacitor line are formed in a group. At least selected - the upper layer of the wiring is provided with a protective layer. That is, in the present invention, at least one of the scanning line, the signal line or the auxiliary capacitance wiring is provided with a protective layer. Therefore, when etching is performed for the contact hole shape of the interlayer insulating film, the protective layer acts as a protective film for etching, and therefore, even if it is an etching mask, A part of the pattern of the interlayer insulating film of the mold has a film defect. In the case of a shortage of defects, it is possible to prevent the wiring of the scanning line or the like after the etching from being exposed. According to this, it can prevent the pixel electrode on the interlayer insulating film from coming into contact with the green ice-seeking wiring such as the scanning line to prevent the short circuit, thereby preventing the occurrence of pixel defects, especially in the fine-grained opening. When the rate is not used for the substrate, it can improve the quality and productivity of the medium-sized bottle _ fork. As the above-mentioned protective layer, if the effect of the wiring of the line 4 is prevented during the etching of the interlayer insulating film, the material and the thickness are not 153051.doc Ϊ 356962 Special Limits & In addition, if the protective layer can protect the lower layer portion at the time of the last name, it may be constructed of the same material as the adjacent other layers, such as the interlayer insulating film and the interlayer film, in this case, in the cross-sectional shape. The protective layer is integrated with other adjacent layers. For example, it is difficult to discriminate the boundary of the layer. The difference between the planar shapes of the other layers adjacent to the protective layer is confirmed, that is, the part of the body (protective layer + The edge-preserving layer can be discriminated by the difference in thickness between the adjacent layers and the un-integrated portion = only the protective layer or only the other layers adjacent thereto. Further, in the present invention, the "protective layer is provided on the upper layer" may mean that the protective layer is placed in contact with a wiring such as a scanning line on the upper layer of the wiring such as a scanning line, or in a scanning line or the like. On the upper layer of the plurality of layers of the wiring, the protective layer is disposed so as not to be in contact with wiring such as a scanning line. For example, a protective layer is provided so as not to be in contact with the scanning line, and a protective layer is provided on the gate insulating film, and a protective layer is provided in the interlayer insulating film. The constituent materials other than the protective layer included in the substrate for a display device of the present invention will be described next. As the insulating substrate, those formed by a transparent insulator such as glass are used. The material of the scanning line, the signal line, and the auxiliary capacitor wiring is not particularly limited as long as the required wiring resistance can be obtained, for example, 1 = (Ta), titanium (Ti), chromium (C〇, aluminum). a metal such as (A1), such a metal gold, or a laminated film of Ti/A丨/Ti formed by laminating the same, etc. Width, thickness 'pattern of the second line, the signal line, and the auxiliary capacitor wiring There is no particular limitation on the shape of the field 153051 .doc •12- 1356962. As a switching element, such as a five-mesh female with a pole, a source and a pole, and ... particularly limited, for example, A _ thin film transistor , J is not... Membrane crystal, microcrystalline shr. 4 矽 bond film transistor, CGs (c〇ntinuous Grain lc〇n, continuous grain boundary crystal 矽) thin film transistor, etc. Material-body forming, source and immersion will be combined with (4) wire as the material of the interlayer insulating film. If there is a material that can obtain the required dielectric constant, wearable ratio, etc., there is no special. The limitation is, for example, =W(SlNx), photosensitive transparent resin, oxidized state = can be used for photosensitive transmission of interlayer insulating film The bright resin may be, for example, a resin such as a resin, an epoxy resin, a polyurethane resin, or a polysulfide resin. The interlayer insulating film may be composed of an old one or two or more layers. The constituents, thickness, and the like are not particularly limited.
作為被形成於層間絕緣膜上之接觸孔,如能使開關元件 之及極與像素電極相連接的話,並無特別之限制’且 於形狀、大小、數量、配置等。此外,在接觸孔内通常J =有為了使開關元件之沒極與像素電極電性相連之導電性 作為像素電極之材料,適用的有汀〇(1_咖仏 〇邊;氧化铜錫)、IZ〇(IndiumZinc〇xide :氧化銦辞)等 之透明導電性材料’如為反射型液晶顯示裝置等所用之顯 不裝置用基板的話,亦適用鋁、銀等之金屬。 作為本發明之顯示裝置用基板之構造,如為以上述般之 153051.doc -13- 1356962 構件為必要而構成者的話,亦可包含其他之構件,並無特 別之限制。 關於本發明之顯示裝置用基板之偏好方式,以下詳細說 明。 上述保護層以設於層間絕緣膜之下層為佳。藉此,在為 了層間絕緣膜之接觸孔形成等而進行蝕刻時,保護層會發 揮對姓刻之保護膜之㈣,並且與將保護層形成於層^絕 緣膜中之方式相比,可簡易地形成保護層。 此外,本發明中’ Γ層間絕緣膜之下層」可指層間絕緣 膜之-層下層,亦可指複數層下層’具體而言,可為閘極 絕緣膜上設有掃描線之保護層之方式,亦可為在掃描線之 一層上層上,接觸掃描線般地設有掃描線之保護層之方 式。 上述保護層以藉半導體構成者為佳,此外,以與構成開 關兀件之半導體層大致相同之組成來形成為佳。在此等情 況中,由於在形成構成開關元件之半導體層之際,可同時 進行保護層之形成,因此,無需在以往之顯示裝置用基板 的製造工序中另加保護層之形成工序,便可製造本發明之 顯示裝置用基板,有助於製造工序之縮短。作為半導體, 以構成開關元件之半導體層者為佳,具體而言,主要有由 非晶石夕構成者等。 此外,「大致相同之組成」乃以被評估為實質上相同之 組成者為佳,惟能以CVD(化學蒸鍍)法等同時進行構成開 關元件之半導體層之形成及保護層之形成的程度範圍内即 I53051.doc •14· 1356.962 可 〇 上述保護層以與構成開關元件之半導體層分離為佳。如 此一來,即使假設被設於掃描線上層之保護層(半導體層) 與相鄰·於開關元件並被連接於開關元件之信號線發生漏3電 的情況中,仍可防止此等與連接於開關元件之沒極發生漏 電’因此,可防止像素缺陷。 上述保護h由氮切(siNx)、:氧切⑽2)或樹脂 構成者為仏依此等,為了層間絕緣膜之接觸孔形成而 進純刻的情況中,不僅保護層可充分有效地發揮對㈣ 之保護層的作用’並且’可簡易地進行保護層之形成。作 為樹脂,基於易於圖案化,以感光性透明樹脂為佳。作為 :用^為保護層之感光性透明樹脂,例如有丙烯酸系樹 氧系枒月曰、聚亞胺酯系樹脂、聚硫亞醯系樹脂等。 如保4層之形成使用感光性樹脂以外之材料的話,可在成 ^ ’塗佈液狀的感光性樹脂後,藉由進行光刻(曝光及 顯衫)、乾式钱刻之方法等進行圖案化。 上述保4層以與構成開關元件之源極及/或沒極之大致 相同組成來形成為佳。扃 ^ ^ 在此情況中,在形成構成開關元件 之源極及汲極之際,可 j時進仃保濩層之形成,無需對以 =!裝置用基板之製造工序另加保護層之形成工序, 使可製造本發明之顯示穿 褒置用基板,從而有助於製造工序 之縮短。· 此外,「大致相同之鈿Λ、 . 、成」乃以被評估為實質上相同之 、-且成者為佳,惟能同# 時進行構成開關元件之源極及汲極之 I53051.doc -15· 1356962 形成及保護層之形成的程度範圍内即可。 上述保護層,以由相對於絕緣性基板表面為垂直方向來 看時’至少被配置於掃描線與像素電極重疊之部分為佳。 藉此’可充分防止蝕刻所致之掃描線露出,充分地發揮防 止像素電極與掃描線之短路的本發明之作用成效。並且, 以保護層在由相對於絕緣性基板表面為垂直方向來看時, 僅被配置於掃描線與像素電極重疊之部分為更佳。在此方 式中,不僅可充分地發揮防止像素電極與掃描線之短路的 本發明之作用成效,並且,可將掃描線之負載電容抑制至 最小,例如相較於保護層被設置成完全覆蓋掃描線上的情 況’亦更能抑制掃描線之負載電容之增加。 此外,上述「由相對於絕緣性基板表面為垂直方向來看 時」,換言之乃指「在絕緣性基板上,觀察成為對象者之 正投影時」之意。更具體而言,乃指「對由成為對象者之 各點垂下至絕緣性基板表面上之垂線的端點集合進行觀察 時」。從而,在此情況中,意謂著絕緣性基板上之掃描線 之正投影、保護層之正投影、及像素電極之正投影會重 疊。此外’上ϋ「掃描線與像*電極之大致重疊部分」乃 以評估實質上為掃描線與像素電極之重疊部分為佳,惟可 得到將掃描線之負載電容之增加抑龍最小的成效的話, 亦可包含該週邊部分。 時 此 上述保護層以由相對於絕緣性基板表面為垂直方向來看 ’被設置成與掃描線重疊而不與信號線重疊為佳。辭 ’在保護層由半導體構成者時等,可防止掃描線與信; 15305 丨.doc 線之間發生漏電。 上述層間絕緣膜以至少由 夕傾这W 由2層的絕緣膜構成’且最上芦 之浥緣膜為有機膜為佳。葬 曰 ,„ ^ 错此,能以構成層間絕緣膜之最 上層的有機膜作為掩模進杆為、 报忐地 、蝕刻,與在層間絕緣膜上另行 體作為掩模進行餘…的情況、及以層間絕緣膜整 率。 進订㈣的情況相比,可提升基板之製造效The contact hole formed on the interlayer insulating film is not particularly limited in shape, size, number, arrangement, or the like, as long as the electrode of the switching element can be connected to the pixel electrode. In addition, in the contact hole, generally, J = there is a material for electrically connecting the electrode of the switching element to the pixel electrode as a material of the pixel electrode, and the applicable one is Ting (1_Curry side; copper tin oxide), A transparent conductive material such as IZ (Indium Zinc® xide) is used as a substrate for a display device used for a reflective liquid crystal display device or the like, and a metal such as aluminum or silver is also used. The structure of the substrate for a display device of the present invention may be other members as long as it is constituted by the above-described 153051.doc -13 - 1356962 member, and is not particularly limited. The preferred mode of the substrate for a display device of the present invention will be described in detail below. The protective layer is preferably provided under the interlayer insulating film. Therefore, when etching is performed for the formation of contact holes of the interlayer insulating film or the like, the protective layer functions as a protective film for the surname (4), and is simpler than the method of forming the protective layer in the insulating film. A protective layer is formed on the ground. In addition, in the present invention, the "lower layer of the interlayer insulating film" may mean the lower layer of the interlayer insulating film, or may be the lower layer of the plurality of layers. Specifically, the protective layer of the scanning line may be provided on the gate insulating film. Alternatively, the protective layer of the scan line may be provided on the upper layer of one of the scan lines in contact with the scan line. The protective layer is preferably formed by a semiconductor, and is preferably formed of substantially the same composition as the semiconductor layer constituting the switching element. In these cases, since the formation of the protective layer can be simultaneously performed when the semiconductor layer constituting the switching element is formed, it is not necessary to additionally form a protective layer in the manufacturing process of the conventional display device substrate. The substrate for a display device of the present invention is produced to contribute to shortening of the manufacturing process. As the semiconductor, it is preferable to constitute the semiconductor layer of the switching element, and specifically, it is mainly composed of amorphous austenite or the like. In addition, it is preferable that the "substantially the same composition" is evaluated as substantially the same composition, and the formation of the semiconductor layer and the formation of the protective layer which constitute the switching element can be simultaneously performed by a CVD (Chemical Vapor Deposition) method or the like. In the range of I53051.doc • 14· 1356.962, it is preferable that the above protective layer is separated from the semiconductor layer constituting the switching element. In this way, even if it is assumed that the protective layer (semiconductor layer) provided on the scanning line layer and the signal line adjacent to the switching element and connected to the switching element are leaky, the connection can be prevented. Leakage occurs in the pole of the switching element. Therefore, pixel defects can be prevented. In the case where the above-mentioned protection h is formed by nitrogen dicing (siNx), oxygen dicing (10) 2) or resin, in order to form a contact hole for the interlayer insulating film, the protective layer can be sufficiently effectively used. (4) The role of the protective layer 'and' can be easily formed by the protective layer. As the resin, a photosensitive transparent resin is preferred because it is easy to pattern. The photosensitive transparent resin using the protective layer is, for example, an acrylic sulfonium sulfonate, a polyurethane resin, or a polysulfide resin. If a material other than the photosensitive resin is used for the formation of the four layers, the pattern can be applied by photolithography (exposure and display), dry etching, etc. after the liquid photosensitive resin is applied. Chemical. It is preferable that the above-mentioned layer 4 is formed in substantially the same composition as that of the source and/or the gate which constitutes the switching element.扃^ ^ In this case, when the source and the drain of the switching element are formed, the formation of the protective layer can be formed without the need for a protective layer for the manufacturing process of the substrate for the device. In the step, the substrate for display through the present invention of the present invention can be produced, which contributes to shortening the manufacturing process. · In addition, "substantially the same, ., cheng" is evaluated as being substantially the same, and the winner is better, but I can use the #53051.doc that constitutes the source and the drain of the switching element. -15· 1356962 The extent to which the formation and protection layers are formed is sufficient. It is preferable that the protective layer is disposed at least in a portion where the scanning line overlaps the pixel electrode when viewed in a direction perpendicular to the surface of the insulating substrate. Thereby, the scanning line due to etching can be sufficiently prevented from being exposed, and the effect of the present invention for preventing the short circuit between the pixel electrode and the scanning line can be sufficiently exhibited. Further, when the protective layer is viewed in a direction perpendicular to the surface of the insulating substrate, it is preferably disposed only in a portion where the scanning line overlaps the pixel electrode. In this manner, not only the effect of the present invention for preventing the short circuit between the pixel electrode and the scanning line but also the load capacitance of the scanning line can be minimized, for example, the full coverage scan is set as compared with the protective layer. The condition on the line 'is also more able to suppress the increase in the load capacitance of the scan line. In addition, the above-mentioned "when viewed from the surface of the insulating substrate in the vertical direction" means "on the insulating substrate, when the projection of the target person is observed". More specifically, it means "when the point set of the perpendicular to the surface of the insulating substrate is observed from the point of the object to be observed". Therefore, in this case, it means that the orthographic projection of the scanning line on the insulating substrate, the orthographic projection of the protective layer, and the orthographic projection of the pixel electrode overlap. In addition, it is preferable to evaluate the overlap between the scan line and the pixel electrode, and it is preferable to evaluate the overlap between the scan line and the pixel electrode, but the effect of reducing the load capacitance of the scan line is minimized. , can also include the surrounding part. It is preferable that the protective layer is disposed so as to overlap with the scanning line and not overlap with the signal line as viewed in a direction perpendicular to the surface of the insulating substrate. When the protective layer is composed of a semiconductor, it is possible to prevent leakage between the scanning line and the signal; 15305 丨.doc line. The interlayer insulating film is preferably formed of an insulating film of at least two layers, and the edge film of the uppermost reed is an organic film. In the case of the burial, the above-mentioned organic film which constitutes the uppermost layer of the interlayer insulating film can be used as a mask, and it can be etched, and the other layer can be used as a mask on the interlayer insulating film. And the interlayer insulating film is completed. Compared with the case of the order (4), the manufacturing efficiency of the substrate can be improved.
作為有機膜,如為可得到 選擇比耸… 介電率、穿透率, k擇比等之材料的話,盔As an organic film, if it is possible to obtain materials such as dielectric ratio, transmittance, k-ratio, etc., the helmet
…別之限制,可依蝕刻條件I 適虽地選擇,例如有丙稀酸糸 佈-夂系树月日、環氧系樹脂、聚亞用 酯系樹脂、聚硫亞醯系樹脂等。 - 本發明亦為形成具由與構成開m半導體層大致相 同組成而叙«層之本發明之顯示裝置絲板之製造方 =且上述顯示裝置用基板之製造方法為具有同時形成保 護層、及構成開關元件之半導體層者。本發明更進—步為In other words, it may be selected depending on the etching conditions I, and examples thereof include acrylic acid sulphate, fluorene resin, epoxy resin, polyalkylene resin, and polysulfide resin. - the present invention is also a method of manufacturing a display device of the present invention having a composition substantially the same as that of the semiconductor layer, and the method for manufacturing the substrate for a display device has a protective layer at the same time, and The semiconductor layer constituting the switching element. The invention is further advanced
形成具由與構成開關元件之源極及/或汲極大致相同組成 而成之保護層之本發明之顯示裝置用基板之製造方法,且 上述顯示裝置用基板之製造方法為具有同時形成保護層、 及構成開關元件之源極及/或沒極者。藉由上述,無需在 以往之顯示裝置用基板的製造工序中另加保護層之形成工 序’便可製造本發明之顯示裝置用基板,有助於製造工序 之縮短。 層 本發明更進一步為具由至少2層之絕緣膜所構成且最上 之絕緣膜為有冑膜之本發明之顯示t置用基板之製造方 153051.doc 17 1356962 法’且亦為上述顯示衷置用基板之製造方法具有以構成層 間絕緣膜之最上層之有機膜作為掩模進行钱刻,同時形成 接觸孔、掃描線之外部引出端子及信號線之外部引出端子 之工序者。藉此,與在層間絕緣膜上另行形成掩模而在姓 刻後加以去除的情況、及以層間絕緣膜整體作為掩模進行 蝕刻的情況相比,可提升基板之製造效率。此外,在接觸 孔之形成工序中,藉一併進行掃描線之外部引出端子及信 號線之外部引出端子之形成,亦可提升基板之製造效率Γ 此外,最上層之有機膜部分之接觸孔會在有機膜形成時 預先形成’因此,在上述接觸孔等之形成工序中,會藉由 蝕刻形成最上層之有機膜部分以外之接觸孔。 本發明攸而為具有本發明之顯示裝置用基板,或具有藉 本發明之顯示裝置用基板之製造方法製成之顯示裝置用^ 板之顯示裝置。顯示裝置如為可藉供應電氣信號至顯示裝 置用基板之掃描線、信號線等而進行顯示之控制者的話,、A method of manufacturing a substrate for a display device of the present invention having a protective layer substantially composed of a source and/or a drain constituting a switching element, and the method for manufacturing the substrate for a display device has a protective layer simultaneously And the source of the switching element and/or the infinite. According to the above, it is possible to manufacture the substrate for a display device of the present invention without adding a protective layer forming step to the conventional manufacturing process of the substrate for a display device, which contributes to shortening the manufacturing process. The present invention is further a method for producing a substrate for display of the present invention having at least two layers of an insulating film and having an uppermost insulating film as a tantalum film. 153051.doc 17 1356962 Method 'and also for the above display The manufacturing method of the substrate for use has a process of forming a contact hole, an external lead terminal of a scanning line, and an external lead terminal of a signal line by using an organic film constituting the uppermost layer of the interlayer insulating film as a mask. Thereby, the manufacturing efficiency of the substrate can be improved as compared with the case where the mask is separately formed on the interlayer insulating film and removed after the last name, and when the entire interlayer insulating film is used as a mask. Further, in the step of forming the contact hole, the external lead-out terminal of the scanning line and the external lead-out terminal of the signal line are collectively formed, and the manufacturing efficiency of the substrate can be improved. Further, the contact hole of the uppermost organic film portion is When the organic film is formed, it is formed in advance. Therefore, in the step of forming the contact hole or the like, a contact hole other than the organic film portion of the uppermost layer is formed by etching. The present invention is a display device for a display device according to the present invention or a display device for a display device produced by the method for producing a substrate for a display device of the present invention. The display device is a controller that can display by displaying an electric signal to a scanning line or a signal line of a substrate for a display device,
f無特別之限制。作為此種之顯示裝置,可為液晶顯示裝 、有機電致發光(EL)顯示裝置等,其中亦以液晶顯示裝 =為佳。依上述般的顯示裝置’可防止像素電極與掃描線 之配線的短路,有效地防止像素缺陷發生,因此 採高精細、高開口率’亦可得到像素缺陷少之良好的顯干 品質,從而提升產能。 :本發明之顯示裝置用基板,像素電極會被設於與形成 *描線 '信號線及開關元件之平面相異之平面上,並 且’具有掃描線等之配線之上層上設有保護層之構造,因 153051 .(Joe -18- 1356962 此,防止了層間絕緣膜上之 之短路所致之像素缺陷發生 板的情況中,尤其在高精細 得到像素缺陷少而良好的顯 成效。 像素電極與掃描線等之配線間 、使用上述般的顯示裝置用基 、向開口率的顯示裝置中,可 示品質’從而得到提升產能之 步詳細說明本發明,惟本發 以下揭示實施方式,更進一 明並不限於此等實施方式。 (第一實施方式)f There are no special restrictions. As such a display device, a liquid crystal display device, an organic electroluminescence (EL) display device, or the like can be used, and a liquid crystal display device is also preferable. According to the display device as described above, the short circuit between the pixel electrode and the scanning line can be prevented, and the pixel defect can be effectively prevented. Therefore, the high-definition and high aperture ratio can be obtained, and the good dry quality with less pixel defects can be obtained. Capacity. In the substrate for a display device of the present invention, the pixel electrode is provided on a plane different from the plane on which the signal line and the switching element are formed, and the structure in which the protective layer is provided on the upper layer of the wiring having the scanning line or the like 153051. (Joe -18- 1356962, in the case of preventing the pixel defect occurrence plate caused by the short circuit on the interlayer insulating film, especially in the high-definition, the pixel defect is small and good effect is obtained. Pixel electrode and scanning In the wiring room such as the line, the display device using the above-described display device and the display device having the aperture ratio can be expressed in terms of the quality of the display device, and the present invention will be described in detail. Not limited to these embodiments. (First embodiment)
說明 關於本發明之一實施方式之第_實施方式,以下依圖i 至錄加以說明。此外,本實施方式中,作為顯示裝置用 基板之具體例,乃以液晶顯示裝置用之主動矩陣式基板來 圖1係本發明之液晶顯示裝置之剖面構造之一例之到面 模式圖。 如圖1所示,液晶顯示裝置40具有主動矩陣式基板(顯示 裝置用基板)30、及具彩色濾光片34及遮光膜35等之對向 基板33,此等基板夾有液晶層32。此外,液晶層被夹在 對向基板33之配向膜(未圖示)、及主動矩陣式基板%之配 向膜(未圖示)之間。 圖2係本發明之主動矩陣式基板对之—像素之平面模 式圖。此外,圖3係圖2所示之顯示裝置用基板之a_a,線上 之箭頭剖面圖,圖4係圖2所示之顯示裝置用基板之心犷線 上之箭頭剖面圖。 如圖2所示,主動矩陣式基板3〇中,閘極線(掃描線)】、 153051.doc •19- 1356962 源極線(信號線)2及像素電極3被層積於絕緣性基板丨〇上。 閘極線1及源極線2被配置成彼此交又。並且,在此等交又 的每一個交叉部上’設有開關元件(TFT) 14及像素電極3。 此外’絕緣性基板1 0位於圖2之最背面’並配置於圖3及圖 4之刮面圖記載之位置。閘極線!上形成有開關元件〗4之閘 極4,源極線2上形成有開關元件14之源極5。此外,像素 電極3介以汲極引出電極6,而連接於開關元件14之汲極6。 此/及極引出電極6 ’則隔著閘極絕緣膜π而與辅助電容匯流 排線7相向,藉此形成輔助電容。 如圖4所示,主動矩陣式基板30中,在閘極絕緣膜丨丨上 設有保護膜(保護層)8,以被覆閘極線1之表面。此外,如 圖2所示,主動矩陣式基板30,在由相對於絕緣性基板i 〇 之表面為垂直方向來看時,具有閘極線1、被覆閘極線1表 面之保遵膜8、及像素電極3重疊之區域〇亦即,具有絕緣 性基板10表面上之閘極線丨之正投影、絕緣性基板1〇表面 上之保護膜8之正投影、絕緣性基板10表面上之像素電極3 之正投影重疊之區域。 接著,就液晶顯示裝置40中之電流及電壓之控制,簡單 說明。 液晶顯示裝置40中’如閘極線!被選擇的話,閘極4上會 破施加電壓。藉由此被施加於閘極4上之電壓,源極5及汲 極6間流通之電流會受到控制。接著,依據由源極線2傳來 之k號’藉電流由源極5流向汲極6,並由汲極6經汲極引 出電極6·而流向像素電極3,從而使像素電極3進行指定之 153051.doc “肩不。輔助電容匯流排線7係為了維持像素電極3之指定顯 不而被辅助性地設置。 接著,對於本mu主動辑式基板狀製造方法 之—例,利用圖2、3及4來加以說明。 在製造本實施方式之主動矩陣式基板3〇之際,首先,在 玻璃等之透明絕緣體所形成之絕緣性基板1〇上,藉濺鍍來 成膜出由Ti/A1/Ti形成之層積膜,並施以光刻後,藉乾式 蝕刻、光阻剝離來同時形成閘極線丨、閘極4及輔助電路線 7。接著,在此等表面上,使厚度約4〇〇〇 A2SiNx(氮化 矽)膜形成之閘極絕緣膜U乃使用SiH4氣體、NH3氣體及N2 虱體之混合氣體,使厚度約1500入之非晶矽形成之活性半 導體層12乃使用SiH4氣體及&氣體之混合氣體,進一步使 厚度約500 A之摻雜磷之N型低阻抗半導體層13乃使用SiH4 氣體、PH3氣體及Η:氣體之混合氣體,藉CVD連續地成膜 後’施以光刻、乾式蝕刻、光阻剝離,從而形成島狀25。 接著’藉濺鍍成膜Ti/Al/Ti所形成之層積膜後,施以光 刻、乾式蝕刻,以同時形成源極線2、源極5、汲極6及汲 極引出線6'。更進一步地’連續地對η型低電極半導體層J 3 進行源極暨汲極分離钱刻’剝離光阻。如此,形成薄膜電 晶體(TFT)14。 接著’覆蓋基板整面般地,使用SiH4氣體、NH3氣體及 氣體之混合氣體以CVD成膜出厚約30〇〇 A之由SiNx形成 之下層層間絕緣膜20。接著,使用SiH4氣體、NH3氣體及 K氣體之混合氣體以CVD成膜出厚約4000 A之SiNx,並藉 J53051.doc -21 - 1356962 由光刻處理及使用CL氣體及&氣體之混合氣體之乾式蝕 刻來形成保護膜8。 之後,藉光刻將厚約3 μιη之正片型感光型丙稀酸樹脂形 成之上層冑機層絕緣膜15形成為具有接觸孔9、Μ極線外 部引出端子接點用圖案(圖16之幻、源極線外部 接點用圖案(圖17之¥)。 接著,為了形成接觸孔9、間極線外部引出端子2〇〇、及 源極線外部引出端子300,乃以上層有機層絕緣_為掩 杈’藉使用CF4氣體及〇2氣體之混合氣體的乾式蝕刻,連 續地蝕刻下層層間絕緣膜20及閘極絕緣膜丨!。 之後,被覆含接觸孔9之基板整面般地,藉濺鍍來成膜 透明的電極。接著,藉光刻、濕絲刻來圖案化成膜之透 明電極並剝離光阻,而得到像素電極3。 '此外,在本實施方式中,作為閘極線1及源極線2之材 料,使用的為Ti/A1/Ti,惟如為可得到所需之線電極者的 話並無特別之限制’例如可使用组(Ta)、鈦⑺)、鉻 (Cr·)' IS (A1)等之金屬及此等金屬之合金等。此外,作為 閘極線1源極線2之材料,可使用由丁汪赂a/TaN等之層積 構以戶成之膜。更進一步地,作為源極線2之材料,除 了 &的金屬膜以外’亦可使用ITQ等之透明導電性膜。 jkL· Ηκ v., 工,作為開關元件14,使用的為非晶石夕薄 膜電明體’惟例如同樣地亦可使用微晶石夕薄膜電晶體、聚 石夕薄膜電晶體、CGS薄膜電晶體等。 方式中’作為像素電極3’使用的為IT〇,惟亦可 I53051.doc -22- 1356962‘ 使用IZ〇等之透明電極。此外,反射型液晶顯示裝置之情 況中’作為像素電極3,如為可反射外光之電極材料的二 即可,例如亦可為A卜Ag等之金屬。 本實施方式中,作為上層層間絕緣膜15,使用的為正片 型的丙稀酸系感光性透明樹脂,惟如為可得到所需之介電 率、穿透率、及下層層間絕緣膜15及閘極絕緣膜u間之蝕Description The first embodiment of an embodiment of the present invention will be described below with reference to FIG. In the present embodiment, a specific example of a substrate for a display device is an active matrix substrate for a liquid crystal display device. Fig. 1 is a plan view showing an example of a cross-sectional structure of a liquid crystal display device of the present invention. As shown in Fig. 1, the liquid crystal display device 40 includes an active matrix substrate (substrate for display device) 30, and an opposite substrate 33 having a color filter 34, a light shielding film 35, and the like, and a liquid crystal layer 32 is interposed between the substrates. Further, the liquid crystal layer is sandwiched between an alignment film (not shown) of the counter substrate 33 and an alignment film (not shown) of the active matrix substrate. Figure 2 is a plan view of a pixel matrix of the active matrix substrate of the present invention. 3 is a cross-sectional view taken along the line a_a of the substrate for a display device shown in FIG. 2, and FIG. 4 is an arrow cross-sectional view on the center line of the substrate for a display device shown in FIG. 2. As shown in FIG. 2, in the active matrix substrate 3, a gate line (scanning line), a 153051.doc 19- 1356962 source line (signal line) 2, and a pixel electrode 3 are laminated on an insulating substrate. 〇上. The gate line 1 and the source line 2 are arranged to cross each other. Further, a switching element (TFT) 14 and a pixel electrode 3 are provided at each of the intersections of the intersections. Further, the 'insulating substrate 10 is located at the rearmost side of Fig. 2' and is disposed at the position described in the shave views of Figs. 3 and 4 . Gate line! A gate 4 of a switching element 4 is formed thereon, and a source 5 of the switching element 14 is formed on the source line 2. Further, the pixel electrode 3 is connected to the drain 6 of the switching element 14 via the drain electrode 6. This/and the pole extraction electrode 6' faces the auxiliary capacitance bus line 7 via the gate insulating film π, thereby forming an auxiliary capacitor. As shown in Fig. 4, in the active matrix substrate 30, a protective film (protective layer) 8 is provided on the gate insulating film to cover the surface of the gate line 1. Further, as shown in FIG. 2, the active matrix substrate 30 has a gate line 1, a gate film covering the surface of the gate line 1 when viewed from a vertical direction with respect to the surface of the insulating substrate i, The area where the pixel electrode 3 overlaps, that is, the front projection of the gate line on the surface of the insulating substrate 10, the front projection of the protective film 8 on the surface of the insulating substrate 1 , and the pixel on the surface of the insulating substrate 10 The area where the orthographic projections of the electrodes 3 overlap. Next, the control of the current and voltage in the liquid crystal display device 40 will be briefly described. In the liquid crystal display device 40, such as the gate line! If selected, the voltage applied to the gate 4 will be broken. By the voltage applied to the gate 4, the current flowing between the source 5 and the drain 6 is controlled. Then, according to the k number transmitted from the source line 2, the current flows from the source 5 to the drain electrode 6, and the drain electrode 6 flows through the drain electrode 6 to the pixel electrode 3, thereby causing the pixel electrode 3 to be specified. 153051.doc "Shoulders. The auxiliary capacitor bus bar 7 is provided in an auxiliary manner in order to maintain the designation of the pixel electrode 3. Next, for the example of the present mu active layout substrate-like manufacturing method, use FIG. 2 In the production of the active matrix substrate 3 of the present embodiment, first, a conductive substrate 1 formed of a transparent insulator such as glass is formed by sputtering. a laminated film formed of /A1/Ti, and subjected to photolithography, simultaneously forming a gate line, a gate 4, and an auxiliary circuit line 7 by dry etching and photoresist stripping. Then, on the surfaces, the thickness is about The gate insulating film U formed of the 4? A2SiNx (tantalum nitride) film is a mixed gas of SiH4 gas, NH3 gas, and N2 germanium, and the active semiconductor layer 12 formed of amorphous germanium having a thickness of about 1,500 is used. SiH4 gas and & gas mixture, further thick The N-type low-resistance semiconductor layer 13 doped with about 500 Å is formed by using a mixed gas of SiH 4 gas, PH 3 gas, and krypton gas to form a film by CVD, followed by photolithography, dry etching, and photoresist stripping. Island shape 25. Then, after depositing a laminated film formed by filming Ti/Al/Ti, photolithography and dry etching are applied to simultaneously form source line 2, source 5, drain 6 and drain lead lines. 6'. Further, 'continuously performing source and 汲-polar separation of the n-type low-electrode semiconductor layer J 3 'peeling photoresist. Thus, a thin film transistor (TFT) 14 is formed. Then 'covering the entire surface of the substrate The SiH4 gas, the NH3 gas, and the gas mixture gas are used to form a lower interlayer insulating film 20 from SiNx by a CVD film having a thickness of about 30 A. Then, a mixed gas of SiH4 gas, NH3 gas, and K gas is used. CVD is performed to form SiNx having a thickness of about 4000 A, and a protective film 8 is formed by photolithography processing and dry etching using a mixed gas of CL gas and & gas by J53051.doc -21 - 1356962. Thereafter, by photolithography Forming a photosensitive acrylic resin with a thickness of about 3 μm The upper layer of the interlayer insulating film 15 is formed to have a contact hole 9 and a pattern for the external lead terminal contact of the drain line (the phantom of FIG. 16 and the pattern of the external line of the source line (Fig. 17). Next, in order to form The contact hole 9, the inter-pole external lead terminal 2〇〇, and the source line external lead-out terminal 300 are the above-mentioned organic layer insulation _ a mask 杈 continuous dry etching using a mixed gas of CF4 gas and 〇2 gas, continuous The lower interlayer insulating film 20 and the gate insulating film are etched back. Then, a transparent electrode is formed by sputtering on the entire surface of the substrate including the contact hole 9. Next, the film-formed transparent electrode was patterned by photolithography and wet wire etching, and the photoresist was peeled off to obtain a pixel electrode 3. Further, in the present embodiment, as the material of the gate line 1 and the source line 2, Ti/A1/Ti is used, but there is no particular limitation as long as the desired wire electrode can be obtained. A metal such as a group (Ta), titanium (7), or a chromium (Cr.)' IS (A1), an alloy of these metals, or the like can be used. Further, as the material of the source line 2 of the gate line 1, a film formed by a layer structure such as Ding Wangbiao a/TaN or the like can be used. Further, as the material of the source line 2, a transparent conductive film such as ITQ can be used in addition to the metal film of & jkL· Ηκ v., work, as the switching element 14, an amorphous thin-film electro-optical body is used. However, for example, a microcrystalline lithography film, a polycrystalline film, or a CGS film can also be used. Crystals, etc. In the mode, 'IT 〇 is used as the pixel electrode 3', but I53051.doc -22- 1356962' uses a transparent electrode such as IZ〇. Further, in the case of the reflective liquid crystal display device, the pixel electrode 3 may be, for example, an electrode material which can reflect external light, and may be, for example, a metal such as Ag or Ag. In the present embodiment, as the upper interlayer insulating film 15, a positive-type acrylic-based photosensitive transparent resin is used, but the desired dielectric constant, transmittance, and underlying interlayer insulating film 15 can be obtained. Between the gate insulating film u
刻選擇比的材料的話,並無特別之限制,例如可使用負片 型感光性樹脂、Si02(氧化矽)膜等。 在本實施方式中,作為下層層間絕緣膜2〇,使用的為藉 CVD法之“>^膜,惟亦可使用正片型及負片型之感光性透 明樹脂等。此外,關於保護膜8同樣地,除了 siNx膜以 外’亦可使用感光性透明樹脂、Si〇2膜等。作為可用於下 層層間絕緣膜20及保護膜8之感光性透明樹脂’例如可為 丙烯酸系樹脂 '環氧系樹脂、聚亞胺酯系樹脂、聚硫亞醯 系樹脂等。 接著,參照圖4,說明本實施方式中之上層有機層絕緣 膜15上有膜缺損的情況中閘極線丨及像素電極3上不會漏電 的作用成效。圖11係顯示以往之主動矩陣式基板中上層層 間絕緣膜剝離而像素電極及閘極線在漏電位置800漏電的 情形之平面模式圖。此外,圖12係圖11中之沿G_G,線切開 之漏電位置800的剖面之剖面模式圖。 以往之主動矩陣式基板130中,如在塗佈成膜上層層間 絕緣膜115時捲入異物等、塗佈成膜時之密合力不足所致 之上層層間絕緣膜115剝離(漏電位置800之部分)的話,由 153051.doc -23· 1356962 上述製造工序可知:在上層層間絕緣膜115缺陷之位置, 下層層間絕緣膜120及閘極絕緣膜lu會被蝕刻。因此,如 圖12所示’像素電極103會與閘極線1〇1接觸,因為漏電而 發生像素缺陷’從而成為降低顯示品質及產能之原因。The material to be selected is not particularly limited, and for example, a negative-type photosensitive resin, a SiO 2 (yttria) film, or the like can be used. In the present embodiment, as the lower interlayer insulating film 2, a "> film" by the CVD method is used, but a positive photosensitive film or a negative photosensitive photosensitive resin may be used. In addition to the siNx film, a photosensitive transparent resin, a Si 2 film, etc. can be used. The photosensitive transparent resin which can be used for the lower interlayer insulating film 20 and the protective film 8 can be, for example, an acrylic resin epoxy resin. A polyimine resin, a polysulfide resin, etc. Next, a gate defect and a pixel electrode 3 in the case where a film defect occurs in the upper organic layer insulating film 15 in the present embodiment will be described with reference to FIG. Fig. 11 is a plan view showing a state in which the upper interlayer insulating film is peeled off and the pixel electrode and the gate line are leaked at the leakage position 800 in the conventional active matrix substrate. Further, Fig. 12 is shown in Fig. 11. A schematic cross-sectional view of a cross section of the leakage current position 800 along the line G_G. In the conventional active matrix substrate 130, when a film is formed by coating a film on the upper interlayer insulating film 115, a foreign material or the like is wound up. When the upper interlayer insulating film 115 is peeled off (part of the leakage position 800) due to insufficient resultant force, it is known from the above manufacturing process of 153051.doc -23· 1356962 that the lower interlayer insulating film 120 and the gate are located at the position where the upper interlayer insulating film 115 is defective. The electrode insulating film lu is etched. Therefore, as shown in FIG. 12, the pixel electrode 103 is in contact with the gate line 1〇1, and pixel defects occur due to leakage, which causes deterioration in display quality and productivity.
然而,本發明在閘極❸上會另藉由絕緣材料等來 形成保護膜8’因此,在以上層層間絕緣膜15作為掩模來 姓刻之際,可保護閘極線1免於被姓刻,保護膜8殘留在像 素電極3與問極線1之間’從而發揮抑制像素缺陷發生之作 用成效。具體而言,在以上層層間絕緣膜15作為掩模,蝕 刻由厚約3000 A之SiNx形成之下層層間絕緣膜2〇、及由厚 約4000 A之SiNx形成之閘極絕緣膜u的工序中將相當於 钱刻合計厚約7_ kSiNx,惟作為保護膜8, 會另 加厚約4000 A,因此,在保護膜8形成之部分,可充分確 保SiNx膜之膜厚(合計约11〇〇〇入),從而可充分地抑制問極 線1與像素電極接觸。 (第二實施方式) 關於本發明之其他實施方式之第二實施方式,以下依圖 5至圖7來說明之。此外,基於方便說明,具有與第一實施 方式相關圖式所示之構件相同功能之構件,將標示相同之 符號,並省略其說明。 第二實施方式中,保護層在與形成開關元件(tft)之半 導體層同時形成後,被由開關元件之半導體層切離,且被 構成為不與源極線重疊。對於上述設有保護層(以下亦稱 為保護半導體層)之第二實施方式的主動矩陣式基板(顯示 I5305l.doc -24. 1356962, 裝置用基板),依圖5至7來說明之。 此外’圖5係以本發明之主動矩陣式基板3 〇中之一像素 為不之平面模式圖。圖6係圖5所示之顯示裝置用基板之C- C線上之箭頭剖面圖’圖7係圖$所示之顯示裝置用基板之 D-D'線上之箭頭剖面圖。However, in the present invention, the protective film 8' is formed by an insulating material or the like on the gate electrode. Therefore, when the above interlayer insulating film 15 is used as a mask, the gate line 1 can be protected from being surnamed. In the engraving, the protective film 8 remains between the pixel electrode 3 and the interrogation line 1 to exert an effect of suppressing the occurrence of pixel defects. Specifically, in the above process, the interlayer insulating film 15 is used as a mask to etch a lower interlayer insulating film 2A formed of SiNx having a thickness of about 3000 Å and a gate insulating film u formed of SiNx having a thickness of about 4000 Å. It is equivalent to a total thickness of about 7_ kSiNx, but as the protective film 8, it is further thickened by about 4000 A. Therefore, in the portion where the protective film 8 is formed, the film thickness of the SiNx film can be sufficiently ensured (total of about 11 〇〇〇) Into, the contact between the interrogation line 1 and the pixel electrode can be sufficiently suppressed. (Second embodiment) A second embodiment of another embodiment of the present invention will be described below with reference to Figs. 5 to 7 . In addition, members having the same functions as those of the members shown in the drawings related to the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted. In the second embodiment, the protective layer is formed simultaneously with the semiconductor layer forming the switching element (tft), and is cut away from the semiconductor layer of the switching element, and is configured not to overlap with the source line. The active matrix substrate (display I5305l.doc - 24.1359582, device substrate) of the second embodiment in which the protective layer (hereinafter also referred to as a protective semiconductor layer) is provided will be described with reference to Figs. Further, Fig. 5 is a plan view showing one of the pixels of the active matrix substrate 3 of the present invention. Fig. 6 is a cross-sectional view taken along the line C-C of the substrate for a display device shown in Fig. 5, and Fig. 7 is a cross-sectional view taken along line DD' of the substrate for display device shown in Fig. $.
首先’說明本實施方式之主動矩陣式基板3〇之製造方法 之一例。在製造本實施方式之主動矩陣式基板3〇之際,首 先’在由玻璃等之透明絕緣基板所形成之基板1〇上,以同 一工序形成閘極線丨、閘極4、及輔助電容線7。接著,在 此等表面上’厚度約4000人之SiNx形成之閘極絕緣膜11乃 使用SiH4氣體、NH3氣體及A氣體之混合氣體,厚度約 1500 A之非晶矽形成之活性半導體層12乃使用SiH4氣體及 &氣體之混合氣體,進一步地厚度約5〇〇 a之摻雜磷之打型 低電阻半導體層13乃使用SiH4氣體、ΡΗ3氣體及η2氣體之 混合氣體,藉CVD連續地成膜後,施以光刻、乾式蝕刻、 光阻剝離,從而形成島狀25。此時,同時形成保護半導體 層26。接著,施以成膜、光刻、乾式蝕刻,同時形成源極 線2、源極5、汲極ό及汲極引出線6,。更進一步地,連續地 對η型低電極半導體層13進行源極.汲極分離蝕刻,剝離 光阻。如此般地’形成薄膜電晶體(TFT)14。 接著,覆蓋基板整面般地,使用SiH4氣體、Nh3氣體及 A氣體之混合氣體以CVD成膜出由厚約3〇〇〇 A之siNx形成 之下層層間絕緣膜20。之後,藉光刻將厚約3从瓜之正片型 感光型丙烯酸樹脂形成之上層有機層絕緣膜15形成為具有 153051.doc •25- 1356962 接觸孔9、閘極線外部引出端子接點用圖案(圖μ之& 源極線外部⑽端子接點用®案⑽17之Υ)β 接著,為了形成接觸孔9、間極線外部引出端子細 二極卜部引出端子3〇〇,乃以上層有機層絕緣膜15為掩 二藉使用CF4氣體及〇2氣體之混合氣體的乾式㈣,連 續刻下層層間絕緣膜2〇及閉極絕緣膜11β 之後’被覆含接觸孔9之基板整面般地,藉軸來成膜 透明的電極。接著,葬氺約丨 、 先心 '式姓刻來圖案化成膜之透 月電極並剝離光阻,而得到像素電極3。 接著,參照圖7,說明上層有機層絕緣_上有膜 的情況中閘極m及像素電極3上不會漏電的作用成效。、 膜板中,如在塗佈成膜上層層間絕、緣 膜時捲入異㈣、塗佈成膜時之密合力不足所致之 間絕緣膜剝離(漏電位置800部 ^^ )的活,由上述製造工序 了知在上層層間絕緣膜缺陷之位 極絕緣膜合被钮,"+ 1 卜層層間絕緣膜及閘 =曰破㈣。因此,如圖12所示,像素電極 與閘極線101接觸,因為漏電 降低顯示品質及產能之原因。像素缺陷’從而成為 層at而因t發明中’在閘極線1上會另行形成保護半導體 ^ ^ ’在以上層層間絕緣膜15作為掩模來姓刻之 :专:保護問極線1免於被钮刻,保護半導體 I:·,之間:從而發揮抑制像素缺陷發生之 _由厚約刪kSiNx形成; 攻之下層層間絕緣膜20、及由 153051.doc -26· 1356962 •ί « · 厚約4000 Α之SiNx形成之閘極絕緣膜丨丨的工序中,將相當 於蝕刻合計厚約7000 AiSiNx,惟保護半導體層26具有約 1500 A之厚度,且藉CF«4氣體及〇2氣體之混合氣體來蝕刻 SiNx之際,SiNx及保護半導體層26之蝕刻選擇比會約為 1 : 1〇,因此,可充分確保閘極絕緣膜〗丨之殘留膜,從而 可充分地抑制閘極線1與像素電極3接觸。First, an example of a method of manufacturing the active matrix substrate 3 of the present embodiment will be described. When manufacturing the active matrix substrate 3 of the present embodiment, first, the gate line 闸, the gate 4, and the auxiliary capacitance line are formed in the same process on the substrate 1 formed of a transparent insulating substrate such as glass. 7. Then, on the surface, the gate insulating film 11 formed by SiNx having a thickness of about 4,000 is a mixed gas of SiH4 gas, NH3 gas and A gas, and the amorphous semiconductor layer 12 having a thickness of about 1500 A is formed. Using a mixed gas of SiH4 gas and & gas, a phosphorus-doped low-resistance semiconductor layer 13 having a thickness of about 5 〇〇a is continuously formed by CVD using a mixed gas of SiH4 gas, ΡΗ3 gas, and η2 gas. After the film, photolithography, dry etching, and photoresist peeling are applied to form an island shape 25. At this time, the protective semiconductor layer 26 is simultaneously formed. Next, film formation, photolithography, and dry etching are applied, and a source line 2, a source 5, a drain electrode, and a drain lead line 6 are formed. Further, the n-type low-electrode semiconductor layer 13 is continuously subjected to source-drain separation etching to peel off the photoresist. A thin film transistor (TFT) 14 is formed as such. Then, an interlayer insulating film 20 formed of a SiNx having a thickness of about 3 A is formed by CVD using a mixed gas of SiH 4 gas, Nh 3 gas, and A gas over the entire surface of the substrate. Thereafter, a top layer of the organic layer insulating film 15 is formed from a positive-type photosensitive acrylic film of a melon by photolithography to have a contact hole of 153051.doc •25-1356962, and a pattern of contact terminals of the external terminal of the gate line. (Fig. μ & source line external (10) terminal contact for the case (10) 17) β Next, in order to form the contact hole 9, the interpole line external lead terminal, the thin two-pole terminal lead terminal 3〇〇, is the above organic The layer insulating film 15 is a dry type (four) which uses a mixed gas of CF4 gas and 〇2 gas, and continuously scribes the interlayer insulating film 2〇 and the closed-electrode insulating film 11β, and then covers the entire surface of the substrate including the contact hole 9. The transparent electrode is formed by the axis. Next, the pixel electrode 3 is obtained by patterning the vapor-transparent moon electrode and patterning the photoresist. Next, the effect of the electric leakage of the gate electrode m and the pixel electrode 3 in the case where the upper organic layer is insulated and the film is formed will be described with reference to Fig. 7 . In the film, for example, when the film is applied between the upper layers of the film, when the film is entangled, the film is entangled in the film (4), and the film is peeled off (the leakage position is 800). In the above-described manufacturing process, the terminal insulating film is bonded to the upper interlayer insulating film defect, and the "+1 interlayer insulating film and the gate = broken" (4). Therefore, as shown in Fig. 12, the pixel electrode is in contact with the gate line 101 because leakage causes a decrease in display quality and productivity. The pixel defect 'is thus a layer at. In the invention, 'the protective semiconductor is formed separately on the gate line 1 '. The above interlayer insulating film 15 is used as a mask to name it: special: protect the question line 1 The button is engraved to protect the semiconductor I:·, between: thereby suppressing the occurrence of pixel defects, which is formed by thickening kSiNx; underlying interlayer insulating film 20, and by 153051.doc -26·1356962 • ί « · In the process of forming a gate insulating film of SiNx having a thickness of about 4,000 Å, the etching is equivalent to a total thickness of about 7000 AiSiNx, but the protective semiconductor layer 26 has a thickness of about 1500 Å, and the CF «4 gas and the 〇 2 gas are used. When the mixed gas is used to etch SiNx, the etching selectivity ratio of the SiNx and the protective semiconductor layer 26 is about 1:1, so that the residual film of the gate insulating film can be sufficiently ensured, and the gate line can be sufficiently suppressed. 1 is in contact with the pixel electrode 3.
此外,本實施方式中,保護半導體層26會與形成開關元 件(TFT)14之半導體層同時形成,因此,相較於第一實施 方式’有助於工序之縮短化。 更進一步地,本實施方式中,保護半導體層26乃與形成 開關元件之半導體層分離,且被構成為不與源極線2重 疊,因此,假設即使被設於閘極線(掃描線)丨上之保護半導 體層26、及相鄰於開關元件14而連接於開關元件14之源極 線(彳§號線)2發生漏電的情況’乃可防止此等與被連接於開 關元件14之汲極6發生電性漏電,因此,可防止像素缺 陷、 (第三實施方式) 關於本發明之其他實施方式之第三實施方式,以下依圖 8至10來說明之。此外,基於說明上之方便,具有與第一 及第二實施方式相關圖式所示之構件相同功能之構件,將 標不相同之付號’並省略其說明。 第三實施方式中,其特徵在於加以第二實施方式之構 造,保護半導體層由相對於絕緣性基板表面為垂直方向來 看時,至少被配置在閘極線(掃描線)及像素電極重疊之部 153051.doc -27- 1356962 分。對於上述設有保護半導體層之第三實施方式的主動矩 陣式基板30,依圖8至1〇來說明之。 此外’圖8係以本發明之主動矩陣式基板30中之一像素 為不之平面模式圖。圖9係圖8所示之顯示裝置用基板之E_ Ε·線上之箭頭剖面圖’圖1〇係圖8所示之顯示裝置用基板 之F-F1線上之箭頭剖面圖。 首先’說明本實施方式之主動矩陣式基板3〇之製造方法 之一例。在製造本實施方式之主動矩陣式基板3〇之際,首 先’在由玻璃等之透明絕緣基板所形成之基板1〇上,以同 一工序形成閘極線丨、閘極4、及輔助電容線7。接著,在 此等表面上’厚度約4〇〇〇人之SiNx形成之閘極絕緣膜丨i乃 使用SlH4氣體、NH3氣體及N2氣體之混合氣體,厚度約 1500人之非晶矽形成之活性半導體層12乃使用SiH4氣體及 H2氣體之混合氣體’進一步地厚度約5〇〇 a之掺雜峨之订型 低電阻半導體層U乃使用SiH4氣體、ΡΗ3氣體及Η2氣體之 混合氣體,藉CVD連續地成膜後,施以光刻、乾式蝕刻、 光阻剝離,從而形成島狀25。此時,同時形成保護半導體 層26。接著’施以成膜、光刻、乾式姓刻,同時形成源極 線2、源極5、汲極6及汲極引出線6·。更進一步地,連續地 對η型低電極半導體層丨3進行源極暨沒極分離钱刻,剝離 光阻°如此般地,形成薄膜電晶體(TFT)丨4。 接著’覆蓋基板整面般地’使用SiH4氣體、NH3氣體及 N2氣體之混合氣體以CVD成膜出由厚約3000 A之SiNx形成 之下層層間絕緣膜20。之後,藉光刻將厚約3 μιη之正片型 I53051.doc -28· ^56962 感光型丙_樹脂形成之上層有制絕緣膜15形成為且有 接觸孔9、間極線外部5/出端子接點用圖案(圖16之^及 源極線外部5|出端子接點用圖案(圖! 了之Y)。 接著為了形成接觸孔9、間極線外部引出端子2〇〇、及 源極線外部引出端子300,乃以上層有機層絕緣膜15為掩 拉’藉使用CF4氣體及〇2氣體之混合氣體的乾式蝕刻,連 續地姓刻下層層間絕緣膜2 0及閘極絕緣膜丨!。 之後,被覆含接觸孔9之基板整面般地,藉濺鍍來成膜 雩.翻的電極。接著,藉光刻、濕式触刻來圖案化成膜之透 月電極並剝離光阻,而得到像素電極3。 接著,參照圖10,說明上層有機層絕緣膜〗5上有膜缺損 的清況中閘極線1及像素電極3上不會漏電的本實施方式中 之作用成效。 以在之主動矩陣式基板中,如在塗佈成膜上層層間絕緣 膜時捲入異物等、塗佈成膜時之密合力不足所致之上層層 間絕緣膜剝離的話,由上述製造工序可知在上層層間絕緣 膜缺陷之位置,下層層間絕緣膜及閘極絕緣膜會被蝕刻。 因此,如圖12所示,像素電極1〇3會與閘極線1〇1接觸,因 為漏電而發生像素缺陷,從而成為降低顯示品質及產能之 原因。 然而’本發明中,在閘極線1上會另行形成保護半導體 層26,因此,在以上層層間絕緣膜15作為掩模來姓刻之 際’可保護閘極線1免於被#刻,保護半導體層26在像素 電極3與閘極線1之間殘留’從而發揮抑制像素缺陷發生之 153051.doc -29- 1356962 作用成效。具體而言,在以上層層間絕緣膜丨5作為掩模, 蝕刻由厚約3000 A之SiNx形成之下層層間絕緣膜2〇 '及由 厚約4000 A之Si,Nx形成之閘極絕緣膜丨丨的工序中,將相當 於蝕刻合計厚約7000 A之SiNx,惟保護半導體層26具有約 1500 A之厚度,且藉CF4氣體及〇2氣體之混合氣體來蝕刻 SiNx之際,SiNx及保護半導體層%之蝕刻選擇比會約為 1 · 10 ,因此,可充分確保閘極絕緣膜丨丨之殘留膜,從而 可充分地抑制閘極線1與像素電極3接觸。 此外,本實施方式之主動矩陣式基板(顯示裝置用基 板)3〇,其特徵在於加以第二實施方式之構造,保護半導 體層26由相對於絕緣性基板1〇之表面為垂直方向來看時, 至少被配置在閘極線(掃描線}1及像素電極3重疊之部分, 且依此構造,可將閘極線丨之負載電容之增加抑制至最小 紅度,比保護半導體層26被設置成完全覆蓋於閘極線丨上 之It况’更能抑制閘極線!之負載電容之增加。 此外,上述第一至第三實施方式中,僅閘極線丨上設有 ^護層8(保護半導體層26),惟本發明中,亦可同樣地將保 4膜(保5蔓半導體膜)設於輔助電容線7上從而得到防止辅 助電容線7與像素電極3之間發生漏電之成效。 【圖式簡單說明】 圖1係以本發明之液晶顯示裝置之剖面構造之一例為示 之剖面模式圖(第一實施方式)。 圖2係以本發明之主動矩陣式基板(顯示裝置用基板)中 之一像素為示之平面模式圖(第一實施方式)。 153051.doc 圖 圖 圖3係圖2所 示之顯示裝置用基板之A-A'線上之 圖4係圖2所示 箭頭剖 面 之顯示裝置用基板之Β_Β·線上之箭頭剖 面 圖5係以本發明之主動矩陣式基板(顯示裝置用基板 之一像素為示之平面模式圖(第二實施方式)。 圖6係圖5所示之顯示裝置用基板之線上之箭頭剖面 圖 不之顯示裝置用基板之D-D·線上之箭頭剖面 圖8係以本發明之主動矩陣式基板⑽示裝置用基板)中 之一像素為示之平面模式圖(第三實施方式)。 圖9係圖8所示之顯示裝置用基板之E-E,線上之箭頭剖面 圖。 圖1 〇係圖8所示之顯示裝置用基板之F · F,線上之箭頭剖面 圖。 圖11係以往之主動矩陣式基板中,上層層間絕緣膜制離 而像素電極與閘極線在漏電位置800漏電時之情況之 模式圖。 Q 12係由圖11中之g_g,線切開而顯示漏電位置之剖 面之剖面模式圖。 圖13係以往之主動矩陣式基板(薄膜電晶體陣列基板)中 之一像素及位於與該像素相鄰位置之像素之一部分之平面 模式圖。 153051.doc •31 - 1356962 圖I4係圖13所示之顯示裝置用基板之H-H,線上之箭頭剖 面圖。 圖15係圖13所示之顯示裝置用基板之w,線±之箭 面圖。 ^ 圖16係顯示裝置基板之閘極線外部弓丨出山 阁。 ^子之平面概略 圖17係顯示裝置基板之閘極線外 。 。Μ出端子之平面概略 \ 【主要元件符號說明】 1 閘極線(掃描線) 2 源極線(信號線) 3 像素電極 4 閘極 5 源極 6 沒極 6' 汲極引出電極 7 輔助電容線 8 保護膜 9 接觸孔 10 絕緣性基板 11 閘極絕緣膜 12 活性半導體層 13 低電阻半導體層 14 薄膜電晶體(開關元件)Further, in the present embodiment, since the protective semiconductor layer 26 is formed simultaneously with the semiconductor layer forming the switching element (TFT) 14, it is advantageous in shortening the process as compared with the first embodiment. Further, in the present embodiment, the protective semiconductor layer 26 is separated from the semiconductor layer forming the switching element, and is configured not to overlap with the source line 2, and therefore, even if it is provided on the gate line (scanning line) 丨The upper protective semiconductor layer 26 and the case where the source line (彳 号 line 2) connected to the switching element 14 adjacent to the switching element 14 is leaked can prevent the connection between the switching element 14 and the switching element 14 Since the electrode 6 is electrically leaky, it is possible to prevent pixel defects. (Third Embodiment) A third embodiment of another embodiment of the present invention will be described below with reference to Figs. In addition, for the convenience of the description, members having the same functions as those of the members shown in the drawings of the first and second embodiments will be denoted by the same reference numerals, and the description thereof will be omitted. According to a third embodiment, in the second embodiment, the protective semiconductor layer is disposed at least in a gate line (scanning line) and a pixel electrode when viewed in a direction perpendicular to the surface of the insulating substrate. Ministry 153051.doc -27- 1356962 points. The active matrix substrate 30 of the third embodiment in which the protective semiconductor layer is provided will be described with reference to Figs. Further, Fig. 8 is a plan view showing a pattern of one of the pixels of the active matrix substrate 30 of the present invention. Fig. 9 is a cross-sectional view taken along line E- Ε of the substrate for a display device shown in Fig. 8. Fig. 1 is an arrow sectional view taken along line F-F1 of the substrate for a display device shown in Fig. 8. First, an example of a method of manufacturing the active matrix substrate 3 of the present embodiment will be described. When manufacturing the active matrix substrate 3 of the present embodiment, first, the gate line 闸, the gate 4, and the auxiliary capacitance line are formed in the same process on the substrate 1 formed of a transparent insulating substrate such as glass. 7. Then, on the surface, the gate insulating film 'i formed by SiNx having a thickness of about 4 Å is an amorphous ruthenium having a thickness of about 1,500 people using a mixed gas of SlH4 gas, NH3 gas and N2 gas. The semiconductor layer 12 is a mixed gas of a mixed gas of SiH4 gas and H2 gas, and is further doped with a thickness of about 5 Å. The patterned low-resistance semiconductor layer U is a mixed gas of SiH4 gas, ΡΗ3 gas, and Η2 gas by CVD. After continuous film formation, photolithography, dry etching, and photoresist peeling are applied to form an island shape 25. At this time, the protective semiconductor layer 26 is simultaneously formed. Then, film formation, photolithography, and dry-type etching are applied to form source line 2, source 5, drain 6 and drain lead line 6. Further, the n-type low-electrode semiconductor layer 丨3 is continuously subjected to source and immersion separation, and the photoresist is peeled off to form a thin film transistor (TFT) 丨4. Then, the interlayer insulating film 20 formed of SiNx having a thickness of about 3000 Å was formed by CVD using a mixed gas of SiH 4 gas, NH 3 gas, and N 2 gas as the entire surface of the substrate. After that, a positive-working type I53051.doc -28·^56962 photosensitive type propylene-resin having a thickness of about 3 μm is formed by photolithography to form an upper insulating film 15 and has a contact hole 9 and an external electrode 5/out terminal. The contact pattern (Fig. 16 and the source line outside 5| the terminal contact pattern (Y!). Next, in order to form the contact hole 9, the interpole line external lead terminal 2, and the source The external lead-out terminal 300 is the dry etching of the above-mentioned organic layer insulating film 15 by using a mixed gas of CF4 gas and 〇2 gas, and the interlayer insulating film 20 and the gate insulating film are successively engraved! Then, the entire surface of the substrate including the contact hole 9 is coated, and the electrode is formed by sputtering. Then, the vapor-transparent electrode is patterned by photolithography and wet etching to peel off the photoresist. Then, the pixel electrode 3 is obtained. Next, an effect of the present embodiment in which the gate electrode 1 and the pixel electrode 3 are not leaked in the state in which the film defect is present in the upper organic layer insulating film 5 will be described with reference to FIG. In the active matrix substrate, such as coating the upper interlayer insulating film When the adhesion between the foreign material and the like is insufficient due to insufficient adhesion, the interlayer insulating film is peeled off. In the above manufacturing process, the lower interlayer insulating film and the gate insulating film are etched at the position of the upper interlayer insulating film defect. Therefore, as shown in FIG. 12, the pixel electrode 1〇3 is in contact with the gate line 1〇1, and pixel defects occur due to leakage, which causes deterioration in display quality and productivity. However, in the present invention, at the gate The protective semiconductor layer 26 is separately formed on the line 1. Therefore, when the above interlayer insulating film 15 is used as a mask, the gate line 1 can be protected from being engraved, and the semiconductor layer 26 is protected at the pixel electrode 3 153051.doc -29-1356962 is effective in suppressing the occurrence of pixel defects. Specifically, the above interlayer insulating film 丨 5 is used as a mask, and etching is formed by SiNx having a thickness of about 3000 Å. In the lower interlayer insulating film 2'' and the gate insulating film 形成 formed by Si and Nx having a thickness of about 4000 A, it is equivalent to etching a total of about 7000 A of SiNx, but the protective semiconductor layer 26 has about 1500. A When the SiNx is etched by a mixed gas of CF4 gas and 〇2 gas, the etching selectivity ratio of the SiNx and the protective semiconductor layer is about 1·10, so that the residual film of the gate insulating film can be sufficiently ensured. In addition, the active matrix substrate (substrate for display device) of the present embodiment is characterized in that the structure of the second embodiment is applied to protect the semiconductor layer 26. When viewed from the surface of the insulating substrate 1A in the vertical direction, at least the gate line (the scanning line}1 and the pixel electrode 3 overlap each other, and the structure of the gate line can be loaded. The increase in capacitance is suppressed to a minimum redness, and the load capacitance of the gate line! is more suppressed than the case where the protective semiconductor layer 26 is disposed to completely cover the gate line. Further, in the above-described first to third embodiments, only the gate layer 8 is provided with the protective layer 8 (protective semiconductor layer 26), but in the present invention, the protective film 4 can also be protected. It is provided on the auxiliary capacitance line 7 to obtain an effect of preventing leakage between the auxiliary capacitance line 7 and the pixel electrode 3. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional schematic view showing an example of a cross-sectional structure of a liquid crystal display device of the present invention (first embodiment). Fig. 2 is a plan view schematically showing one of the pixels of the active matrix substrate (substrate for display device) of the present invention (first embodiment). 153051.doc FIG. 3 is a diagram showing a line on the A-A' line of the display device substrate shown in FIG. 2, and FIG. 4 is a cross-sectional view of the substrate for the display device shown in FIG. The active matrix substrate of the invention (the pixel of one of the substrates for the display device is shown as a plan view (second embodiment). FIG. 6 is a view showing the arrow of the line on the substrate for the display device shown in FIG. FIG. 8 is a schematic plan view showing a pixel of the active matrix substrate (10) of the present invention as a plan view (third embodiment). Fig. 9 is a cross-sectional view taken along the line E-E of the substrate for a display device shown in Fig. 8. Fig. 1 is a cross-sectional view taken along the line F·F of the substrate for a display device shown in Fig. 8 and on the line. Fig. 11 is a schematic view showing a state in which the upper interlayer insulating film is separated and the pixel electrode and the gate line are leaked at the drain position 800 in the conventional active matrix substrate. Q 12 is a cross-sectional schematic view showing a section of the leakage position by the g_g in Fig. 11 and the line cut. Fig. 13 is a plan view showing a portion of a pixel of a conventional active matrix substrate (thin film transistor array substrate) and a portion of a pixel located adjacent to the pixel. 153051.doc • 31 - 1356962 Fig. I4 is a cross-sectional view taken along the line H-H of the substrate for a display device shown in Fig. 13 . Fig. 15 is a cross-sectional view showing the line w of the display device shown in Fig. 13 and the line ±. ^ Figure 16 shows the outside of the gate line of the device substrate. ^Subplanar outline Fig. 17 shows the gate line of the device substrate. . Plane outline of the output terminal \ [Description of main component symbols] 1 Gate line (scanning line) 2 Source line (signal line) 3 Pixel electrode 4 Gate 5 Source 6 No pole 6' Bungee extraction electrode 7 Auxiliary capacitor Line 8 Protective film 9 Contact hole 10 Insulating substrate 11 Gate insulating film 12 Active semiconductor layer 13 Low-resistance semiconductor layer 14 Thin film transistor (switching element)
153051.doc -32* 1356962. 15 上層層間絕緣膜 20 下層層間絕緣膜 25 島狀半導體層圖案 26 保護半導體層 30 主動矩陣式基板(顯示裝置用基板) 32 液晶層 34 彩色濾光片 35 遮光膜153051.doc -32* 1356962. 15 Upper interlayer insulating film 20 Lower interlayer insulating film 25 Island-shaped semiconductor layer pattern 26 Protective semiconductor layer 30 Active matrix substrate (substrate for display device) 32 Liquid crystal layer 34 Color filter 35 Light-shielding film
40 液晶顯示裝置 101 閘極線(掃描線) 102 源極線(信號線) 103 像素電極 104 閘極 105 源極 106 汲極 106' 汲極引出電極40 Liquid crystal display device 101 Gate line (scanning line) 102 Source line (signal line) 103 Pixel electrode 104 Gate 105 Source 106 Deuterium 106' Deuterium extraction electrode
107 輔助電容線 109 接觸孔 110 基板 111 閘極絕缘膜 112 活性半導體層 113 低電阻半導體層 114 薄膜電晶體(開關元件) 115 上層有機層間絕緣膜 153051.doc -33- 1356962 120 下層層間絕緣膜 125 島狀半導體層圖案 130 主動矩陣式基板(顯示裝置用基板) 200 閘極線外部引出端子 201 閘極線外部引出端子之最上層電極 300 源極線外部引出端子 301 源極線外部引出端子之最上層電極 153051.doc -34-107 auxiliary capacitor line 109 contact hole 110 substrate 111 gate insulating film 112 active semiconductor layer 113 low-resistance semiconductor layer 114 thin film transistor (switching element) 115 upper organic interlayer insulating film 153051.doc -33- 1356962 120 lower interlayer insulating film 125 Island-shaped semiconductor layer pattern 130 Active matrix substrate (display device substrate) 200 Gate line external lead terminal 201 Gate line external lead terminal uppermost layer electrode 300 Source line external lead terminal 301 Source line external lead terminal Upper electrode 153051.doc -34-
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JP5117667B2 (en) * | 2005-02-28 | 2013-01-16 | カシオ計算機株式会社 | Thin film transistor panel |
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US8022559B2 (en) * | 2005-09-22 | 2011-09-20 | Sharp Kabushiki Kaisha | Substrate for a display panel, and a display panel having the same |
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DE602007013761D1 (en) * | 2006-07-07 | 2011-05-19 | Sharp Kk | MATRIX SUBSTRATE, METHOD FOR REPAIRING THE SAME AND LIQUID CRYSTAL DISPLAY |
JP2008233399A (en) * | 2007-03-19 | 2008-10-02 | Sony Corp | Pixel circuit, display device, and manufacturing method of display device |
WO2009150862A1 (en) * | 2008-06-12 | 2009-12-17 | シャープ株式会社 | Tft, shift register, scanning signal drive circuit, and display, and method for forming tft |
JP5102878B2 (en) * | 2008-12-05 | 2012-12-19 | シャープ株式会社 | Display device substrate and display device |
JP2010245480A (en) * | 2009-04-10 | 2010-10-28 | Hitachi Displays Ltd | Display device |
WO2011021425A1 (en) * | 2009-08-20 | 2011-02-24 | シャープ株式会社 | Array substrate, method for manufacturing array substrate, and display device |
KR101793176B1 (en) * | 2010-08-05 | 2017-11-03 | 삼성디스플레이 주식회사 | Display device |
JP5443619B2 (en) * | 2010-12-08 | 2014-03-19 | シャープ株式会社 | Active matrix substrate and display device |
JP6124668B2 (en) | 2013-04-26 | 2017-05-10 | 三菱電機株式会社 | Thin film transistor substrate and manufacturing method thereof |
KR102247678B1 (en) | 2013-09-13 | 2021-04-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device |
CN108292685B (en) * | 2015-11-24 | 2020-10-30 | 夏普株式会社 | Semiconductor device and manufacturing method of semiconductor device |
CN105931987A (en) * | 2016-05-27 | 2016-09-07 | 京东方科技集团股份有限公司 | Display substrate, preparation method of display substrate, display panel and display device |
JP2018018006A (en) * | 2016-07-29 | 2018-02-01 | 株式会社ジャパンディスプレイ | Display device |
KR102633986B1 (en) * | 2016-09-12 | 2024-02-06 | 삼성디스플레이 주식회사 | Transparent display device |
CN108873526B (en) * | 2018-07-19 | 2021-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
WO2020213102A1 (en) * | 2019-04-17 | 2020-10-22 | シャープ株式会社 | Display device |
CN111105704A (en) * | 2019-12-23 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | Display device |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03153217A (en) | 1989-11-10 | 1991-07-01 | Casio Comput Co Ltd | Tft panel and its manufacture |
JPH03211526A (en) | 1990-01-17 | 1991-09-17 | Matsushita Electric Ind Co Ltd | Active matrix substrate and liquid crystal display device |
JP2780539B2 (en) | 1991-10-25 | 1998-07-30 | 日本電気株式会社 | Liquid crystal display |
JPH05249478A (en) * | 1991-12-25 | 1993-09-28 | Toshiba Corp | Liquid crystal display device |
JPH05341323A (en) | 1992-06-11 | 1993-12-24 | Canon Inc | Liquid crystal display device |
DE69332142T2 (en) | 1992-12-25 | 2003-03-06 | Sony Corp., Tokio/Tokyo | Active matrix substrate |
JP3383047B2 (en) | 1992-12-25 | 2003-03-04 | ソニー株式会社 | Active matrix substrate |
JPH06337436A (en) | 1993-05-27 | 1994-12-06 | Fujitsu Ltd | Method of manufacturing thin film transistor matrix |
KR970011972A (en) | 1995-08-11 | 1997-03-29 | 쯔지 하루오 | Transmission type liquid crystal display device and manufacturing method thereof |
JP2933879B2 (en) | 1995-08-11 | 1999-08-16 | シャープ株式会社 | Transmissive liquid crystal display device and method of manufacturing the same |
US5852485A (en) * | 1996-02-27 | 1998-12-22 | Sharp Kabushiki Kaisha | Liquid crystal display device and method for producing the same |
JP3019047B2 (en) | 1997-11-07 | 2000-03-13 | 日本電気株式会社 | Active matrix type TFT element array |
TW565719B (en) | 1998-03-13 | 2003-12-11 | Toshiba Corp | Manufacturing method of array substrate for display device |
JP2000029071A (en) | 1998-07-14 | 2000-01-28 | Toshiba Corp | Array substrate for display device and its production |
JP3362008B2 (en) | 1999-02-23 | 2003-01-07 | シャープ株式会社 | Liquid crystal display device and manufacturing method thereof |
JP4781518B2 (en) * | 1999-11-11 | 2011-09-28 | 三星電子株式会社 | Reflective transmission composite thin film transistor liquid crystal display |
JP2001296551A (en) | 2000-04-12 | 2001-10-26 | Hitachi Ltd | Liquid crystal display device |
KR100628257B1 (en) * | 2000-10-20 | 2006-09-27 | 엘지.필립스 엘시디 주식회사 | Reflective and transflective LC structures |
JP4831716B2 (en) * | 2001-03-15 | 2011-12-07 | Nltテクノロジー株式会社 | Active matrix liquid crystal display device |
JP2004054069A (en) | 2002-07-23 | 2004-02-19 | Advanced Display Inc | Display device and method for repairing disconnection of display device |
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US20050264736A1 (en) | 2005-12-01 |
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US7732820B2 (en) | 2010-06-08 |
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TW201115245A (en) | 2011-05-01 |
JP4522145B2 (en) | 2010-08-11 |
US7319239B2 (en) | 2008-01-15 |
US20090085038A1 (en) | 2009-04-02 |
TWI348582B (en) | 2011-09-11 |
KR100668567B1 (en) | 2007-01-16 |
TW200617550A (en) | 2006-06-01 |
JP2005338238A (en) | 2005-12-08 |
KR20060048075A (en) | 2006-05-18 |
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