1345839 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種積體電路封裝構造之測試方法。 【先4技術】 隨著電子裝置曰漸輕薄短小，晶片的速度及複雜性相對越來 越向，因此對於封裝效能的要求也越來越高。於是目前便有很多 不同的封裝構造發展以滿足目前晶片的需求，例如覆晶封裝便是 test)、= test)等。 而晶片封裝後、出廠前，為保證晶片一切運作正常，已滿足 客戶的要求，通常仍需接受-些可靠度賴，例如銲接點測試 (Solder 扣如 reliability test)、冷熱循環測試(temperature 哪如 三點彎曲測試(three point bending test)、震動測試(vibrati〇n 關於焊接點相關的測試技術，例如有中華民國專利第5222知1345839 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a test method for an integrated circuit package structure. [First Technology] As electronic devices become lighter and thinner, the speed and complexity of the wafers are relatively more and more, and therefore the requirements for package performance are becoming higher and higher. So there are a lot of different package configurations to meet the needs of current wafers, such as test flip chip, test, test, etc. After the chip is packaged and before leaving the factory, in order to ensure that the chip is operating normally and has met the customer's requirements, it is usually still necessary to accept some reliability, such as solder joint test (Solder deduction test), thermal cycle test (temperature like Three point bending test, vibration test (vibrati〇n related to welding point related testing techniques, such as the Republic of China Patent No. 5222
狀设日爛顺提肢良，以有_鶴轉通過峨的甚^The shape of the day is bad, the limbs are good, and there are _ cranes that pass through the 峨
否有影響等。 5 1345839 因此’在此發展已漸趙成熟的領域中，仍存有改善的可能性。 【發明内容】 有雲於上述的問題，本發明的主要目的在於提供一種積體電 麟裝職綠，藉由_給卜縣駄電流與溫度循 環’來決定該封裝體的可靠性。 因此’為達上述目的’本發明所揭露之一種積體電路封裝構 造測試方^ _體電路縣構造具有—基板設有複數個第一接 整’該些第—接㈣、以—第—雛菊電路®案連接，每-第一接塾 ，又有焊錫^塊’此方法包含:提供—賴板，具有複數個第二接 墊，該些第二接墊係以一第二離菊電路圖案連接，且每—第二接 整與複數個測試藝連接；將該積體電路封農構造設置於該測顺 上其中該些第一接塾與該些第一接塾電性連接；及對該積體電 路封襄構造施加-溫度循環測試與一電源時，該電源經測試塾、 弟-以及第二離菊電路圖案連接而通過各個焊錫凸塊。 本發明的詳細特徵及優點將在實施方式中詳細敘述，1内容 足以使任何綱_技藝者了解本發明之技術並據以實施，，、且任 =與本發_關之優點及目的係可輕易地從本說明書所揭露之 谷、申請專利範圍及圖式中理解。 、_以上之關於本發明内容之制及以下之實施方式之說明係用 ^不乾與娜本翻之原理，並且類本發明之翻 進一步之解釋。 尺 【實施方式】 U45839 明如發料特徵與實作，紐合@式作最佳實施例样細說 又以下圖7F僅為簡單說明’並非依實際尺寸描緣，亦即 應出f路板結構中各層次之實際尺寸與特色，先予敘明。 塾圖戶斤示為一傳統的半導體裝置測試板’其包含複數個接 弟1圖中的接墊A1-U21)以及複數個測試塾3〇(如第 中的測試塾丨_17)。所有的触1G與測試墊％係 路^ 接。接塾㈣肋連接至待測積體電路封㈣造上之銲錫凸^ 丁於圖中）。ij此，當該賴電路縣構造安設於戦扳上時一 在積體電路封⑽造上之銲錫凸塊係簡於_試板的接塾= 上，然後在這樣的狀態下，進彳情裝體可靠職，脚藉由一雷 =1=器決定職體的電性連接是否完整，例如根據鲜錫點是 2有疲勞破壞(fatiguedamage)的現象產生判斷其電性連接是否完 而本發明封賴造測試方法的—概念在於同時給予定㈣以 及溫度循環以對該封裝構造進行測試。藉由上述方法，便;二 此封裝構造的可靠度，也可從得到的電性㈣之中判斷是^疲 勞破壞(faugue damage)或電子遷移(elect_gr_ 生，此方法較接近產品在實際應用時的狀況。 以下將配合第2圖’敘述本發明之方法流程。 首先，提供-測試板與-積體電路封裳構造，此積體電路封 裝構造具有-基板，設有複數個第—雜，該些第—接塾係以一 7 第一離菊電路圖案連接，每一 具有複數個第二接塾，_第_接=;有焊錫凸塊，測試板 接，每-笛_ -弟一接塾k以一第二雛菊電路圖案連 、〜第—接墊可與複數個測試塾連接(步驟201)。 此安；:驟:裳步驟將一積體電_構造安設於-測試板上。 係在將封裝構造上的焊錫凸塊與測試板上的接塾對齊 麦進仃。鱗，藉由將賴凸塊 體電路封料肪衫/料板以麵而使此積 連接。植測試板上’並使第二接塾與第—接塾電性 時K板與其上的麵電路縣構造通常處於-電性測 騎境下，在此環境下係可提供加热、冷卻等溫度控 1 :二此’騎為真空狀態或充填有惰性氣體以避免測試時，受 到二氣憎質或外界環境的景彡響(步驟2〇2)。 …接者，在電性測試顧中將制試板絲完成後，將-電性 針連接至測試塾，並且在給予定電流的同時，對其施加一 變化’物溫度循環測試以決定此龍電路封裝構造的電性 貝特別疋疲勞破壞（fatigue damage)或電子遷移 (electr0-migratiGn)的性f。此時電流經測試墊、第—以及第二雜菊 電路圖案而通過各個焊錫凸塊(步驟2〇3)。 在通過電流之步驟後，更可測量該等谭接凸塊的阻抗值。當 該阻抗值大於-駭值時，判定_體電路封裝構造有焊錫凸塊 失效。 另外，上述測試板可包含一對主測試墊，與該些第二接墊連 1345839 接使探針只要與主測試墊接觸便可使該些第二接塾通電。 上述係以積體電路封裝構造在電性測試儀器的密閉環境下為 =子’但’實際上有時為了瞭解環賴此韻電路構造的影 f，也可將其置於大氣底下，同樣同時給予定電流與溫度變化來 得头/、電n，知·別是疲勞破壞(fatigue dama辟）或電子遷移 (electro-migration)的性質。 另外-方面’雖以上相關說明以及圖式皆以—測試板以及一 積體電路封裝構造作為·。但實際上，為了有效增進測試效率， 本發明也可躺於具有概侧試單元之測試板上，也就是說，No effect, etc. 5 1345839 Therefore, there is still the possibility of improvement in the field where development has gradually matured. SUMMARY OF THE INVENTION In view of the above problems, the main object of the present invention is to provide an integrated body-mounted green, which determines the reliability of the package by _ giving the county current and temperature cycle. Therefore, in order to achieve the above object, an integrated circuit package structure test method disclosed in the present invention has a structure in which the substrate is provided with a plurality of first alignments, the first to the fourth (four), and the first to the daisy. The circuit® case is connected to each of the first connection and the soldering piece. The method comprises: providing a board, having a plurality of second pads, the second pads being in a second daisy circuit pattern Connecting, and each of the second and the plurality of test art connections; the integrated circuit sealing structure is disposed on the measurement, wherein the first interfaces are electrically connected to the first interfaces; When the integrated circuit is sealed and applied with a temperature cycle test, the power supply is connected to each of the solder bumps via the test 塾, -, and the second daisy circuit pattern. The detailed features and advantages of the present invention will be described in detail in the embodiments. The content of the present invention is sufficient for any skilled person to understand the technology of the present invention and to implement the same, and the advantages and objectives of the present invention can be It is easily understood from the valley, patent application scope and drawings disclosed in this specification. The above description of the present invention and the following description of the embodiments are based on the principles of the present invention and the further explanation of the invention. Ruler [Embodiment] U45839 is as clear as the characteristics and implementation of the material, and the best example is the same as the following. Figure 7F is only a simple explanation. 'It is not based on the actual size, that is, the f-board should be out. The actual dimensions and characteristics of each level of the structure are described first.塾 户 示 示 示 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统All touch 1G and test pad% are connected. The ribs are connected to the solder bumps of the integrated circuit package (4) to be tested (in the figure). Ij, when the Lai circuit county structure is installed on the board, the solder bumps made in the integrated circuit package (10) are simplified on the interface of the _ test board, and then in this state, The erotic body is reliable, and the foot determines whether the electrical connection of the body is complete by a lightning = 1 = device. For example, according to the fact that the fresh tin point is 2 fatigue fatigue, it is judged whether the electrical connection is complete or not. The concept of the invention of the test method is to simultaneously give (4) and temperature cycles to test the package construction. By the above method, the reliability of the package structure can also be judged from the obtained electrical properties (four) as fatigue damage (faugue damage) or electron migration (elect_gr_sheng, which is closer to the product in practical application) The following describes the method flow of the present invention in conjunction with FIG. 2 . First, a test board and an integrated circuit sealing structure are provided. The integrated circuit package structure has a substrate and a plurality of first and second impurities. The first connection system is connected by a 7 first daisy circuit pattern, each having a plurality of second interfaces, _ _ _ connection =; solder bumps, test board connection, each - flute _ - brother one The interface k is connected to a plurality of test files by a second daisy circuit pattern (step 201). The security:: step: the step of placing an integrated body _ structure on the test board The solder bumps on the package structure are aligned with the joints on the test board. The scales are connected by laminating the bumps and the bulk of the circuit board. On the test board, 'the second junction and the first connection are connected to the K-plate and the surface circuit county on it. In the environment of electric riding, in this environment, it can provide temperature control such as heating and cooling. 1: This is a vacuum or filled with inert gas to avoid testing, subject to dioxins or external environment. The scene is ringing (step 2〇2). ... pick-up, after the test board is completed in the electrical test, the electric needle is connected to the test 塾, and a constant current is applied thereto. Change the 'temperature cycle test to determine the electrical properties of this dragon circuit package structure, especially the fatigue damage or electron migration (electr0-migratiGn). At this time, the current passes through the test pad, the first and the second The daisy circuit pattern passes through the respective solder bumps (step 2〇3). After the step of passing the current, the impedance values of the tan bumps can be measured. When the impedance value is greater than -骇, the _ body circuit is determined. The package structure has a solder bump failure. In addition, the test board may include a pair of main test pads, and the second pads are connected with the 1345839 so that the probes can be energized by contacting the main test pads. Integrated circuit package In the closed environment of the electrical test instrument, it is = child's but in fact, in order to understand the shadow f of the circuit structure, it can also be placed under the atmosphere, and simultaneously give constant current and temperature changes. /, electric n, knowing the nature of fatigue damage (fatigue dama) or electron migration (electro-migration). In addition - the above description and drawings are all - test board and an integrated circuit package structure However, in practice, in order to effectively improve the test efficiency, the present invention can also be placed on a test board having an almost lateral test unit, that is,
-個測試板上可同時與複數個積體電路封㈣造連接而進行本發 明的測試方法。 X 根據以上所述，同時給予積體電路封裝構造定電流以及溫度 變化’便可时精準的得知频電路構造的可靠度，因得到 的電㈣貝’可用以判斷其焊錫凸塊是否具有疲勞破壞脚娜 damage)或電子遷移(eiectr〇_migrati〇n)現象。 雖然本發日肢前述之較佳實施_露如上，然其並非用以限 定本發明’任何熟f相像技藝者，在不_本發明之精神和範圍 内1可作些許之更動與潤飾，因此本發明之專梅護範圍須視 本說明書所附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖，顯示傳統的半導體裝置測試板；及 第2圖’為依照本㈣之龍難構造測試方法流程圖。 1345839 【主要元件符號說明】 10 接墊 30 測試塾 201 提供一測試板與一積體電路封裝構造 202 進行一安裝步驟將一積體電路封裝構造安設 於一測試板上 203 對該積體電路封裝構造同時施加一溫度循環 測試與一電流A test board can be connected to a plurality of integrated circuit packages (4) at the same time to perform the test method of the present invention. X According to the above, the constant current and temperature change can be accurately given to the integrated circuit package structure at the same time. The reliability of the frequency circuit structure can be accurately determined, and the obtained electric (four) shell can be used to judge whether the solder bump has fatigue. Destroy the foot of the damage or electron migration (eiectr〇_migrati〇n) phenomenon. Although the preferred embodiment of the present invention has been described above, it is not intended to limit the invention to any skilled person, and may not be modified or retouched within the spirit and scope of the present invention. The scope of the invention is defined by the scope of the patent application attached to the specification. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a conventional semiconductor device test board; and Fig. 2 is a flow chart of the test method for the dragon difficult structure according to the present invention. 1345839 [Major component symbol description] 10 pad 30 test 塾 201 provides a test board and an integrated circuit package structure 202 for a mounting step, an integrated circuit package structure is mounted on a test board 203. The integrated circuit The package structure simultaneously applies a temperature cycle test with a current