1343155 九、發明說明： 【發明所屬之技術領域】 本發明之實施例係關於一種防止在連接一 USB型連接器 期間發生靜電放電之方法，及一種藉此形成之USB型連接 器。 【先前技術】 對可攜式消費電子裝置之需求之強烈增長推動著對高容 量儲存裝置之需要。諸如快閃記憶體儲存卡之非揮發性半 導體記憶體裝置正變得廣泛用於滿足對數位資訊儲存及交 換之不斷增長之需求。其可攜性、通用性及堅固設計，連 同其高可靠性及大儲存容量已使此類記憶體裝置可理想地 用於各種各樣之電子裝置，包括例如數位相機、數位音樂 播放器、視訊遊戲控制臺、PDA及蜂巢式電話。 用於在裝置（例如’上文所提及之彼等）與其他組件（例 如’桌上計算機及類似物）之間傳遞信號之通用串列匯流 排（USB)介面同樣普遍存在《該USB介面由一公插頭及若 干母插座連接器組成。插頭通常具有一個或多個插入至配 合插座中之開口中之插腳》雖然存在數種類型之USB連接 器’但最常用的是其上具有一 4插腳連接器且由一屏蔽環 繞之類型A插頭。在圖1至3之先前技術中，以橫載面形式 顯示一習用類型A插頭及插座。例如，圖丨中所示之習用 USB插頭20可附裝至一電子裝置，且包括一其上形成有一 信號電力插腳24、一對信號插腳26及28以及一信號接地插 腳30之基座22。該基座及該等插腳由一護罩32覆蓋。★玄習 127830.doc 用USB插座36可倂入一主機裝置中且包括一基座38及形成 於该基座上的四個端子4〇至46。如在圖3中所見，該插頭 可藉助與插腳4〇至46配合之插腳24至30而被接納於該插座 内，以允許在該電子裝置與主機裝置之間傳遞信號。 在習用USB連接中，該護罩係藉由該電子裝置中一已建 立電路路徑而電耦合至該信號接地插腳。特定而言，一旦 邊罩附著在基座22及插腳26至30周圍，通常，該護罩便可 在一耦合至該信號接地插腳之位置處銲接至一印刷電路 板。該護罩至接地之電耦合之諸多功能中之一者係防止在 該護罩與該電子裝置之電路之多個部件之間發生靜電放電 (ESDp特定而言，在該護罩與電子電路處於不同之電位 (例如，因該護罩中之靜電積累）之情形下，一靜電電荷可 自該護罩跳躍至該電子電路上，其中該靜電電荷可損壞該 電路中之半導體組件。 如所指示，若將該護罩接地，則該護罩中之靜電電荷可 透過該接地連接無害地放電。然而，當前已知提供其中包 括一護罩之USB連接半導體裝置，但不銲接至該印刷電路 板且不具有接地連接。該等裝置具有因該護罩與電子電路 之間的ESD所致之損壞危險。 【發明内容】 一個實施例係關於一種防止在連接—USB型連接器之期 間發生靜電放電之方法，及一種藉此形成之USB型連接 器。該連接器包括一分層基塊，其第一層包括複數個信號 插腳，且其第二層包括一ESD接地夾。該接地夾可提供於 127830.doc 1343155 一至少部分地向下形成於該基塊之第二層之表面中之凹部 内。該接地夾可具有一附著至該複數個信號插腳之—信號 接地插腳之一近端之近端，但該接地夾和信號接地插腳可 在沿其長度之其他位置處耦合。 可將包括該接地夾之連接器附著至一半導體裝置。在實 施例中，可將一護罩附著在該連接器周圍，且可能附著在 該半導體裝置周圍。該接地夾之一部分提供在該基塊之表 面以上之一高度處，以便在該護罩環繞該基塊滑動時，該 護罩嚙合該接地夾並與其保持接觸。因此，該護罩中積累 之任何靜電放電自該護罩透過ESD接地夾行進至該信號接 地插腳’並在此處無害地耗散掉。 【實施方式】 現在將參照圖4至！2闞釋實施例，該等實施例係關於一 種防止在連接一 USB型連接器期間發生靜電放電之方法及 一種藉此形成之USB型連接器。應瞭解，本發明可按諸多 不同之形式體現，而不應視為僅限於本文所述之實施例。 而是，提供該等實施例旨在使本揭示内容透徹和完整並將 本毛明全面傳達給熟習此項技術者。實際上，本發明意欲 涵蓋該等實施例之替代、修改及等效形式，該等實施例之 替代、修改及等效形式仍歸屬於由隨附申請專利範圍所界 疋之本發明之範疇及精神内。此外，於本發明之以下詳細 說月中，闡述了衆多特定細節以提供對本發明之徹底理 解。然而，熟習此項技術者易知，無需該等特定細節亦可 實施本發明。 I27830.doc 1343155 首先參照圖4至6之透視圖、俯視圖及邊視圖，圖中顯示 一根據本發明之一實施例之一不具有一護罩之usb連接器 100。所示連接器100係用於一類型A USB連接，但如後文 所述，本發明涵蓋其他類型之USB連接器可包括本發明。 連接器100包括一分層基塊102，該分層基塊包括一第一層 104及一第二層114，該第二層整體地形成或附著至層 。第一層104包括複數個信號插腳1〇6至112，其每一者 具有靠近層104之一遠端Π 8之端部。層114包括一遠端12〇 及一近端122。基塊1〇2可由已知用於USB型連接器之一材 料形成’例如各種具有介電特性性之塑膠之任何一種。可 將基塊102模製成一包括層104、114及信號插腳1〇6至112 之整體單元。另一選擇為，可將信號插腳1〇6至112附著至 層1 04，且其後將層丨14以所示之一偏移組態結合至層 104。儘管本文所述之本發明之一實施例包括一分層基 塊’但應瞭解’下文所述之ESD接地夾亦可與不包括一分 層基塊之其他USB連接器設計一起使用。 4吕號插腳106至112可係一可在類型a USB連接器中找到 的習用信號插腳。插腳1 06可係一信號電力插腳，如下文 所解釋，其用於向一 USB連接器1〇〇附接至其之半導體裝 置供應一電壓。信號插腳108及110可在該半導體裝置與一 USB連接器100連接至其之主機裝置之間傳輸信號。插腳 112可係一向半導體裝置提供一接地路徑之信號接地插 腳。插腳106至112中之每一者可暴露於連接器ι〇〇之第一 層104之一表面上。信號插腳1〇6至112可掩埋於連接器丨00 127830.doc -10- 之一部分内，其中層1〇4及U4重聶， ^ 且該專插腳可暴露在 層114之一底部表面I%處。如 11Λβ Λ Τ對圖4中之信號接地插腳 112及針對圖5中該等插腳之每—去 _ 考所不，該等插腳之每一 者之-近端可延伸穿過層114之近端122。如下文所解釋， 插腳1〇6至112之近端部分用於將料插腳銲接至該半導體 裝置之一印刷電路板。1343155 IX. Description of the Invention: TECHNICAL FIELD Embodiments of the present invention relate to a method of preventing electrostatic discharge occurring during connection of a USB type connector, and a USB type connector formed thereby. [Prior Art] The strong demand for portable consumer electronic devices is driving the need for high capacity storage devices. Non-volatile semiconductor memory devices such as flash memory cards are becoming widely used to meet the growing demand for digital information storage and exchange. Its portability, versatility and robust design, along with its high reliability and large storage capacity, have made such memory devices ideal for use in a wide variety of electronic devices including, for example, digital cameras, digital music players, video Game console, PDA and cellular phone. A universal serial bus (USB) interface for transmitting signals between devices (such as 'the ones mentioned above) and other components (such as 'desktops and the like) is also ubiquitous. It consists of a male plug and several female socket connectors. The plug typically has one or more pins that are inserted into the openings in the mating socket. Although there are several types of USB connectors, the most common one is a type A plug with a 4-pin connector on it and surrounded by a shield. . In the prior art of Figures 1 to 3, a conventional type A plug and socket are shown in the form of a cross-sectional surface. For example, the conventional USB plug 20 shown in the figure can be attached to an electronic device and includes a base 22 having a signal power pin 24, a pair of signal pins 26 and 28, and a signal ground pin 30 formed thereon. The base and the pins are covered by a shield 32.玄 127830.doc The USB socket 36 can be inserted into a host device and includes a base 38 and four terminals 4〇 to 46 formed on the base. As seen in Figure 3, the plug can be received within the socket by pins 24 through 30 that cooperate with pins 4A through 46 to allow signals to be transmitted between the electronic device and the host device. In conventional USB connections, the shield is electrically coupled to the signal ground pin by a built circuit path in the electronic device. In particular, once the side cover is attached around the base 22 and the pins 26 to 30, typically the shield can be soldered to a printed circuit board at a location coupled to the signal ground pin. One of the many functions of the shield to ground electrical coupling prevents electrostatic discharge from occurring between the shield and the various components of the circuitry of the electronic device (ESDp, in particular, where the shield is in electrical circuit In the case of different potentials (eg, due to static buildup in the shield), an electrostatic charge can jump from the shroud to the electronic circuit, wherein the electrostatic charge can damage the semiconductor components in the circuit. If the shield is grounded, the electrostatic charge in the shield can be discharged harmlessly through the ground connection. However, it is currently known to provide a USB-connected semiconductor device including a shield, but not soldered to the printed circuit board. There is no ground connection. These devices have a risk of damage due to ESD between the shield and the electronic circuit. SUMMARY OF THE INVENTION One embodiment relates to preventing electrostatic discharge from occurring during a connection-USB type connector. And a USB type connector formed thereby. The connector includes a layered base, the first layer of which includes a plurality of signal pins, and the second layer of which includes An ESD ground clip. The ground clip can be provided at 127830.doc 1343155 at least partially downwardly formed in a recess in a surface of the second layer of the base block. The ground clip can have an attached to the plurality of signal pins - the proximal end of the proximal end of one of the signal ground pins, but the ground clip and the signal ground pin can be coupled at other locations along its length. The connector including the ground clip can be attached to a semiconductor device. In an embodiment A shield may be attached around the connector and may be attached around the semiconductor device. One of the ground clips is partially provided at a height above the surface of the base to slide around the shield The shroud engages and maintains contact with the ground clip. Therefore, any electrostatic discharge accumulated in the shroud travels from the shroud through the ESD ground clip to the signal ground pin ' and is harmlessly dissipated therein. [Embodiment] Embodiments will now be explained with reference to FIGS. 4 to 2, which relate to a method and a method for preventing electrostatic discharge from occurring during connection of a USB type connector The USB-type connector thus formed. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. And the present invention is intended to cover alternatives, modifications and equivalents of the embodiments. The alternatives, modifications and equivalents of the embodiments are still The scope and spirit of the present invention is defined by the scope of the appended claims. It will be appreciated that the invention may be practiced without these specific details. I27830.doc 1343155 Referring first to perspective, top and side views of FIGS. 4-6, there is shown one embodiment of the present invention having no The shield of the usb connector 100. The connector 100 is shown for use with a type A USB connection, but as will be described hereinafter, other types of USB connectors are contemplated by the present invention to include the present invention. The connector 100 includes a layered base block 102 that includes a first layer 104 and a second layer 114 that are integrally formed or attached to the layer. The first layer 104 includes a plurality of signal pins 1〇6 through 112, each of which has an end adjacent one of the distal ends 8 of the layer 104. Layer 114 includes a distal end 12A and a proximal end 122. The base block 1 2 can be formed of any of the materials known to be used in the USB type connector, for example, various plastics having dielectric properties. The base block 102 can be molded into an integral unit comprising layers 104, 114 and signal pins 1 - 6 through 112. Alternatively, signal pins 1〇6 through 112 can be attached to layer 104, and then layer 14 is bonded to layer 104 in one of the illustrated offset configurations. Although one embodiment of the invention described herein includes a layered block' it should be understood that the ESD ground clips described below can also be used with other USB connector designs that do not include a layered base block. The LV pin 106 to 112 can be a conventional signal pin found in the Type a USB connector. Pin 106 can be a signal power pin that, as explained below, is used to supply a voltage to a semiconductor device to which a USB connector 1 is attached. Signal pins 108 and 110 can transmit signals between the semiconductor device and a host device to which a USB connector 100 is connected. Pin 112 can be a signal ground pin that provides a ground path to the semiconductor device. Each of the pins 106 to 112 can be exposed on one of the surfaces of the first layer 104 of the connector ι. Signal pins 1〇6 to 112 can be buried in a portion of connector 丨00 127830.doc -10- where layers 1〇4 and U4 are re-entered, and the dedicated pins can be exposed to one of the bottom surfaces of layer 114. At the office. For example, 11 Λβ Λ Τ for the signal ground pin 112 of FIG. 4 and for each of the pins of FIG. 5, the proximal end of each of the pins may extend through the proximal end of the layer 114. 122. As explained below, the proximal portions of pins 1〇6 through 112 are used to solder the material pins to one of the semiconductor devices.
基塊102包括一形成於層114中之凹部部分13〇。在實施 例中’凹部130可在該信號接地插腳上方且沿該信號接地 插腳之-長度形成。然而’在下文所解釋之替代實施例 中，凹部130可形成於層114之其他處。如在㈣之邊 視圖令之最佳所見，凹部13〇可部分地向下延伸穿過基塊 102距離d，以便不暴露凹部130下方的信號接地插腳112 之任何。p刀。如下文所解釋’在替代實施例中，凹部1 3 〇 可向下延伸至一深度’其中信號接地插腳112之部分暴露 在凹。卩13 0内。在實施例中’如圖所示，凹部1 3 〇可通至層 114之近端122’但不會延伸至層ι14之遠端12〇。在替代實 把例中’凹部13〇可一直延伸至層ι14之遠端12〇。在下文 所解釋之另一替代實施例中，可完全省略凹部丨3〇。 可將一 ESD接地夾134附著於凹部130内。接地夾134可 由銘 '銅、其他金屬及其合金形成。夾134可鍍覆亦可不 锻覆。在一實施例中，ESD接地夾134可包括一近端136， 其（例如）可藉由銲料丨38以實體方式及以電方式耦合至信號 接地插腳112之一近端（如圖4及5辛所示）。本發明涵蓋可以 實體方式及電方式將夾134耦合至信號接地插腳112之近端 127830.doc • 11 - 1343155 之其他方法。在實施例中，夾134可包括—支點14〇(如在 圖6中之最佳所見）以使夾134形成為一能夠f曲之懸臂。 夹134可進一步包括一伸出到凹部130外部之部分144，如 圖4及6令所見。如下文所解釋，部分144經提供以嚙合一 安裝於基塊102周圍之護罩。 圖中顯示凹部130及ESD接地夾134在信號接地插腳U2 上對準’且顯示夾134在插腳112之一近端處連接至接地插 腳112。然而，在替代實施例中，應瞭解在凹部13〇及夾 134定位於基塊102之層114内之其他位置處之情形下，亦 可將夾134電耦合至信號接地插腳丨丨2。凹部13〇及夾134可 位於一個或多個插腳106 ' 108及11〇上。凹部13〇及夾134 可平行於插腳106至112，亦可不與之平行。此外，儘管將 夾134顯示為一大致直線長度之金屬（當自圖5之頂部觀看 時）’但應瞭解在其他實施例中當自頂部觀看時，凹部1 及夹134可具有f曲或圓形邊緣。 類似地，應瞭解可在除插腳丨12之近端以外的位置處以 實體方式及/或以電方式將夾134耦合至信號接地插腳 112。舉例而έ，如圖7之邊視圖中所示，凹部可透過 1 14 一直延伸至信號接地插腳丨丨2，以使信號接地插腳丨工2 暴露在凹部130之底部處。在此一實施例中，可在基塊1〇2 之層114内沿著信號接地插腳112之長度以實體方式及/或 以電方式將夾134耦合至各種位置。在圖8之邊視圖中所示 之另一實施例中，凹部丨3〇可具有向下延伸穿過層丨14一第 一距離dl之第一部分，及—直延伸穿過層114一第二距離 127830.doc -12- 1343155 d2之第二部分（以使信號接地插腳112暴露在該凹部之該第 二部分處）。在此實施例中，可於插腳i 12在凹部13〇内暴 露處以實體方式及/或以電方式將夾134輕合至信號接地插 腳 1 12。 此外，在圖9之邊視圖中所示之另一實施例中，可完全 省略凹部130。在圖9之實施例中，如上所述，ESD接地爽 134可直接附著至層114之表面上之任何地方，且可耳有一 電耦合至信號接地插腳112之近端之近端。在此一實施例 中，ESD接地夾134可包括一在層Π4之表面上方延伸之伸 出部分150。 現在參照圖10之橫戴面邊視圖，一護罩1 5 6可附著在美 塊102及ESD接地夾136周圍。護罩1 56可係一此項技術中 所習知之保護性金屬蓋’且如此項技術中所習知，可將基 塊102安裝護罩1 56内。在實施例中，失丨36之部分ι46及 150係&供在基塊102之表面以上之一高度處，以便在護罩 1 5 6環繞該基塊滑動時，該護罩可輕微地向下擠塵部分 146 、 150 ° 夾136至基塊102之懸臂式安裝及夾136之彈性性質導致 部分146與漢罩156保持壓力接觸。因此，護罩156中積累 之任何靜電放電自該護罩透過ESD接地夾136行進至信號 接地插腳112，並在此處無害地耗散掉◊儘管上述實施例 中將ESD接地夾136闌釋為懸臂式安裝至基塊1〇2，但在替 代實施例中，夾136無需為懸臂式。 圖11係一附著至一半導體裝置i 70之連接器1〇〇之俯視 127830.doc •13· (s ) 1343155The base block 102 includes a recessed portion 13〇 formed in the layer 114. In an embodiment, the recess 130 can be formed over the signal ground pin and along the length of the signal ground pin. However, in an alternative embodiment explained below, the recess 130 may be formed elsewhere in the layer 114. As best seen in the side view of (d), the recess 13A can extend partially downwardly through the base block 102 a distance d so as not to expose any of the signal ground pins 112 below the recess 130. p knife. As explained below, in an alternative embodiment, the recess 1 3 〇 can extend down to a depth where a portion of the signal ground pin 112 is exposed to the recess.卩13 0. In the embodiment, as shown, the recess 13b can pass to the proximal end 122' of the layer 114 but does not extend to the distal end 12 of the layer ι14. In the alternative embodiment, the recess 13 can extend all the way to the distal end 12 of the layer ι14. In a further alternative embodiment explained below, the recess 丨3〇 can be omitted altogether. An ESD ground clip 134 can be attached to the recess 130. The ground clip 134 can be formed from the name 'copper, other metals and their alloys. The clip 134 may or may not be forged. In one embodiment, the ESD ground clip 134 can include a proximal end 136 that can be physically and electrically coupled to the proximal end of the signal ground pin 112, for example, by solder bumps 38 (see FIGS. 4 and 5). Xin showed). The present invention encompasses other methods of coupling the clip 134 to the proximal end of the signal ground pin 112 in a physical and electrical manner 127830.doc • 11 - 1343155. In an embodiment, the clip 134 can include a fulcrum 14 〇 (as best seen in Figure 6) to form the clip 134 as a cantilevered arm. The clip 134 can further include a portion 144 that projects out of the recess 130 as seen in Figures 4 and 6. As explained below, portion 144 is provided to engage a shroud mounted about base block 102. The recess 130 and the ESD ground clip 134 are shown aligned on the signal ground pin U2 and the display clip 134 is connected to the ground pin 112 at one of the proximal ends of the pin 112. However, in an alternate embodiment, it will be appreciated that the clip 134 can also be electrically coupled to the signal ground pin 2 in the event that the recess 13 and the clip 134 are positioned at other locations within the layer 114 of the block 102. The recess 13 〇 and the clip 134 can be located on one or more of the pins 106 ' 108 and 11 。. The recess 13 〇 and the clip 134 may be parallel to or parallel to the pins 106 to 112. Moreover, although the clip 134 is shown as a substantially linear length of metal (when viewed from the top of FIG. 5), it will be appreciated that in other embodiments the recess 1 and clip 134 may have a f-curve or circle when viewed from the top. Shaped edges. Similarly, it will be appreciated that the clip 134 can be physically and/or electrically coupled to the signal ground pin 112 at a location other than the proximal end of the pin 12. For example, as shown in the side view of FIG. 7, the recess can extend through the first to the signal grounding pin 2 to expose the signal grounding pin 2 to the bottom of the recess 130. In this embodiment, the clip 134 can be physically and/or electrically coupled to various locations along the length of the signal ground pin 112 within the layer 114 of the base block 1〇2. In another embodiment, shown in the side view of FIG. 8, the recess 丨3〇 can have a first portion that extends downwardly through the layer 14 by a first distance dl, and—through the layer 114 and a second The second portion of the distance 127830.doc -12- 1343155 d2 (to expose the signal grounding pin 112 to the second portion of the recess). In this embodiment, the clip 134 can be physically and/or electrically coupled to the signal ground pin 1 12 at the location of the pin i 12 in the recess 13 暴. Further, in another embodiment shown in the side view of Fig. 9, the recess 130 may be omitted entirely. In the embodiment of FIG. 9, as described above, the ESD ground 134 can be attached directly to any location on the surface of layer 114 and can have a proximal end that is electrically coupled to the proximal end of signal ground pin 112. In this embodiment, the ESD ground clip 134 can include a projection portion 150 that extends over the surface of the layer stack 4. Referring now to the cross-sectional side view of Fig. 10, a shield 156 can be attached around the block 102 and the ESD ground clip 136. The shield 1 56 can be a protective metal cover as is known in the art and as is known in the art, the base block 102 can be mounted within the shield 1 56. In an embodiment, portions ι 46 and 150 of the shackle 36 are provided at a height above the surface of the base block 102 so that the shroud can be slightly biased as the shroud 156 slides around the base block. The cantilevered mounting of the lower squeezing portion 146, 150° clip 136 to the base block 102 and the resilient nature of the clip 136 cause the portion 146 to be in pressure contact with the hood 156. Thus, any electrostatic discharge accumulated in the shield 156 travels from the shield through the ESD ground clip 136 to the signal ground pin 112 where it is dissipated harmlessly, although the ESD ground clip 136 is interpreted as The cantilever is mounted to the base block 1〇2, but in an alternative embodiment, the clip 136 need not be cantilevered. Figure 11 is a top view of a connector 1 attached to a semiconductor device i 70 127830.doc • 13· (s ) 1343155
圖。如圖所示，插腳l〇6、108、11〇及112係例如 或其他習知之電耦合方法在其近端處附著至半導體：： 170。如在圖12之橫戴面邊視圖中所見，半導體裝置及 連接器1G0兩者皆可包封在護罩156内。在實施例中，可= 模製化合物封裝半導體裝置17〇，且然後將經封裴之半導 體裝置安裝在護罩156内。在以模製化合物封裝半導體裝 置17〇之情形下，該護罩可僅覆蓋連接器1〇〇。半導體裝置 170之類型及功能對於本發明來說並不重要，但在實施例 中可能係一包括一個或多個快閃記憶體晶粒及一個或多個 控制器晶粒之快閃記憶體裝置，例如一 ASIC。Figure. As shown, pins 106, 108, 11 and 112 are attached to the semiconductor:: 170 at its proximal end, for example, or other conventional electrical coupling methods. As seen in the cross-sectional side view of Fig. 12, both the semiconductor device and the connector 1G0 can be enclosed within the shield 156. In an embodiment, the semiconductor compound can be packaged by the molding compound and then the sealed semiconductor device is mounted within the shield 156. In the case where the semiconductor device 17 is packaged with a molding compound, the shield can cover only the connector 1A. The type and function of the semiconductor device 170 is not critical to the present invention, but in an embodiment may be a flash memory device including one or more flash memory dies and one or more controller dies. , for example an ASIC.
出於例證及說明之目的，上文已對本發明進行了詳細說 明。本文不意欲包羅無遺或將本發明限制於所揭示之精確 形式。根據上文之教示亦可作出許多種修改及改變。所述 各實施例之選擇旨在最佳地解釋本發明之原理及其實際應 用’藉以使其他熟習此項技術者能夠以適合於所構想具體 應用之各種實施例形式及使用各種修改來最佳地利用本發 明。本發明之範疇應由隨附申請專利範圍來界定。 【圖式簡單說明】 圖1係一習用類型A USB插頭之一剖視圖。 圊2係一習用類型a USB插座之一剖視圖。 圖3係一插入一類型a USB插座内之一習用類型A USB插 頭之剖視圖。 圖4係一根據本發明之一實施例之一不具有一護罩之 USB插頭之透視圖。 127830.doc •14· 圖5係一圖4中所示實施例之俯視圖。 圖6係一圖4中所示實施例之邊視圖。 圖7係一根據本發明之一替代性實施例之一不具有一護 罩之USB插頭之邊視圖。 圖8係一根據本發明之另一實施例之一不具有—護罩之 USB插頭之邊視圖。 圖9係一根據本發明之另一替代性實施例之—不具有一 護罩之USB插頭之邊視圖。 圖10係一根據本發明之一實施例之一 USB插頭之橫戴面 邊視圖。 圖11係一根據本發明之一實施例之一不具有一護罩之 USB半導體裝置之俯視圖。 圖12係一根據本發明之一實施例之一 USB半導體裝置之 橫截面邊視圖。 【主要元件符號說明】 20 插頭 22 基座 24 信號電源插腳 26 信號插腳 28 信號插腳 30 信號接地插腳 32 護罩 36 插座 38 基座 127830.doc -15- 1343155 40 插腳 42 插腳 J 44 插腳 • 46 插腳 ' 100 連接器 ‘ 102 基塊 104 第一層 106 信號插腳 • 108 信號插腳 110 信號插腳 112 信號接地插腳 114 第二層 120 遠端 122 近端 124 底部表面 130 凹部 • 1 J Η- 接地夾 136 夾 138 銲料 140 支點 144 部分 146 部分 150 伸出部分 156 護罩 170 半導體裝置 127830.doc -16-The invention has been described in detail above for the purposes of illustration and description. This document is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen to best explain the principles of the invention and its application in the <Desc/Clms Page number> The present invention is utilized. The scope of the invention should be defined by the scope of the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional type A USB plug.圊 2 is a cross-sectional view of a conventional type a USB socket. Figure 3 is a cross-sectional view of a conventional type A USB plug inserted into a type of USB receptacle. Figure 4 is a perspective view of a USB plug without a shield in accordance with one embodiment of the present invention. 127830.doc • 14· Figure 5 is a top plan view of the embodiment shown in Figure 4. Figure 6 is a side elevational view of the embodiment shown in Figure 4. Figure 7 is a side elevational view of a USB plug without a shield in accordance with an alternative embodiment of the present invention. Figure 8 is a side elevational view of a USB plug without a shield, in accordance with another embodiment of the present invention. Figure 9 is a side elevational view of a USB plug without a shield in accordance with another alternative embodiment of the present invention. Figure 10 is a cross-sectional side view of a USB plug in accordance with one embodiment of the present invention. Figure 11 is a top plan view of a USB semiconductor device without a shield in accordance with one embodiment of the present invention. Figure 12 is a cross-sectional side view of a USB semiconductor device in accordance with one embodiment of the present invention. [Main component symbol description] 20 Plug 22 Base 24 Signal power pin 26 Signal pin 28 Signal pin 30 Signal ground pin 32 Shield 36 Socket 38 Base 127830.doc -15- 1343155 40 Pin 42 Pin J 44 Pin • 46 Pin '100 connector' 102 base block 104 first layer 106 signal pin • 108 signal pin 110 signal pin 112 signal ground pin 114 second layer 120 far end 122 proximal end 124 bottom surface 130 recess • 1 J Η- ground clip 136 clip 138 Solder 140 Pivot 144 Part 146 Part 150 Projection 156 Shroud 170 Semiconductor device 127830.doc -16-