1327345 * 九、發明說明： • 【發明所屬之技術領域】 本發明係關於一種無核心層線路直接連接半導體晶片 之結構及製法，更詳言之，指一種無核心層基板之線路直 5 接連接半導體晶片的結構及製法。 【先前技術】1327345 * IX. Description of the Invention: • Technical Field of the Invention The present invention relates to a structure and a method for directly connecting a semiconductor chip without a core layer line, and more particularly to a line 5 connection without a core layer substrate. The structure and manufacturing method of a semiconductor wafer. [Prior Art]
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20 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration)以及微型化（Miniaturization)的封裳要求，提 供多數主 '被動元件及線路連接之電路板（Circuit b〇ard)亦 逐漸由單層板演變成多層板（Multi-layer bord)，俾於有限的 空間下’藉由層間連接技術（Interlayer connection)擴大 電路板上可利用的佈線面積而配合高電子密度之積體電路 (Integrated circuit)需求。 習知之半導體封裝結構，傳統將半導體晶片黏貼於基 板頂面’再進行打線接合（wire bonding)，或者後來所發展 出之覆晶接合（Flipchip)的技術，都藉由在基板的背面植以 錫球以進行電性連接，如此，雖可達到高腳數的目的。但 是在更高頻使用時或高速操作時，其將因導線連接路徑過 長而產生電氣特性之效能無法提昇，而有所限制。另外， 因傳統封裝需要多二欠的連接介© ’相對地增加製程之複雜 度。較先進之覆晶式球狀矩陣（FHp Chlp Ball &id ， FCBGA)封裝結構，如丨所示，提供—主動表面⑽％ 5 1327345 surface)上具有作為訊號輸入及輸出之電極墊IQ〗的半導體 晶片10,於該電極墊101上形成有焊料凸塊n並電性連接 至一具有核心層120之基板12的電性連接墊121a (bump pad)，而該基板12形成有複數個線路層122(wiring 15 20 及絕緣層123(insulation layer)，兩線路層122之間係以導 電盲孔125(conductive via)連接，又該基板12最上層之線 路層122a形成有防焊層13a(s〇lder mask),用以保護該線 路層122並顯露該電性連接墊121。其_ ’該基板12中之 該核心層120具有導電通孔124以導通其兩側之線路層 122。又該基板12之最底層的線路層12沘形成有複數個電 性連接墊121b，且在該線路層122b上形成有一防烊層 13b，用以保護線路層122b並顯露該電性連接墊12化，^ 可於該電性連接墊12lb上形成焊料球14(bali)以電性連接 至印刷電路板（未圖示），俾以完成—覆晶式球柵陣列封裝。 一雖然覆晶之球栅陣列式結構可以使用於更高腳數及更 门頻之產σα，但整體之封裝成本高，且在技術上仍面臨不 少限制，尤其在電性連接部分，因為環保需求，使得電性 連接材料你|J #含錯（Pb)之銲錫材料將禁用，而在選擇使用 替代材料時，尚待克服電性及機械等品質不穩定的問題， 此外’由於習知覆晶封裝結構利用焊料凸塊與半導體晶片 電性連接，在製作細線路的製程中，半導體晶片與封裝基 板間需要填膠，然因膠具有黏滯性，線路愈細則愈不容易 ，、此填入的過私將需愈久的時間，而且部分填勝區合 因具有未被填滿的孔洞，而使封裝結構存在爆板的風險。曰 6 1327345 另方面’上述之具有核心層120之基板12中，係於 一”电層上進行線路製裎以形成該核心層120,之後復於該 核心層120上進行線路增層製程，藉以形成具多層線路之 基板12而該核心層120中形成有多數電鑛導通孔（ρτΗ) 124 ’ 一般電鍍導通孔124之孔徑係約在以上，相 對地‘电目孔之孔徑約在50 # m左右，比較而言該電鍍 導通孔124之存在係不利於細線路佈局之靈活性，而且亦20 With the booming electronics industry, electronic products are gradually entering the direction of multi-functional and high-performance research and development. In order to meet the requirements of high integration and miniaturization of semiconductor packages, most of the main passive components and circuit boards (Circuit B〇ard) have gradually evolved from single-layer boards to multiple layers. Multi-layer bord, in a limited space, expands the wiring area available on the board by Interlayer connection to match the high electron density integrated circuit requirements. The conventional semiconductor package structure, which conventionally adheres a semiconductor wafer to the top surface of the substrate, and then performs wire bonding, or a Flipchip technology developed later, by implanting tin on the back surface of the substrate. The ball is electrically connected, so that the number of feet can be achieved. However, when it is used at a higher frequency or at a high speed, it is limited in the performance of the electrical characteristics due to the long wire connection path. In addition, the complexity of the process is relatively increased due to the need for more than two owing connections from conventional packages. The more advanced flip-chip ball matrix (FHp Chlp Ball & id, FCBGA) package structure, as shown in 丨, provides the active surface (10)% 5 1327345 surface) with the electrode pad IQ as the signal input and output. The semiconductor wafer 10 is formed with a solder bump n on the electrode pad 101 and electrically connected to an electrical connection pad 121a of the substrate 12 having the core layer 120, and the substrate 12 is formed with a plurality of circuit layers. 122 (wiring 15 20 and insulation layer 123 (insulation layer), the two circuit layers 122 are connected by conductive vias 125, and the uppermost layer of the substrate 12 is formed with a solder resist layer 13a (s The erlder mask is used to protect the circuit layer 122 and expose the electrical connection pad 121. The core layer 120 in the substrate 12 has conductive vias 124 to electrically connect the circuit layers 122 on both sides thereof. The bottom layer of the substrate 12 is formed with a plurality of electrical connection pads 121b, and a barrier layer 13b is formed on the circuit layer 122b for protecting the circuit layer 122b and exposing the electrical connection pads. ^ A solder ball 14 can be formed on the electrical connection pad 12lb (bali ) electrically connected to a printed circuit board (not shown), to complete the flip-chip ball grid array package. Although the flip chip ball grid array structure can be used for higher pin count and more gate frequency Σα, but the overall packaging cost is high, and there are still many technical limitations. Especially in the electrical connection part, because of environmental protection requirements, the electrical connection material of your |J #B (Pb) solder material will be disabled, In the choice of using alternative materials, it is still necessary to overcome the problem of unstable quality such as electrical and mechanical, and in addition, [the conventional flip-chip package structure uses solder bumps to electrically connect with semiconductor wafers, in the process of making fine lines, There is a need to fill the gap between the semiconductor wafer and the package substrate. However, because the glue has viscosity, the more detailed the line is, the more difficult it is to fill in, and the part of the filling area will not be filled. The hole is full, and there is a risk of exploding the package structure. 曰6 1327345 In another aspect, the substrate 12 having the core layer 120 described above is lined on an "electric layer" to form the core layer 120, after which complex The core layer 120 is subjected to a line build-up process to form a substrate 12 having a plurality of layers, and a plurality of electrical ore vias (ρτΗ) 124 are formed in the core layer 120. Generally, the aperture of the plated vias 124 is about the above, The hole diameter of the ground hole is about 50 #m. In comparison, the existence of the plated via 124 is not conducive to the flexibility of the fine line layout, and
10 15 局限4基板12縮紐導電路徑的可能性，因此限制了電性品 質的進一步提昇’另-方面，該核心4 120的存在使得： 基板12厚度不易有效降低’若將該核心Μ 120之厚度薄 化’例如降低至6〇_以下，該基板12生産性將面臨苛刻 挑戰’而使該基板12之製程良率大幅降低，因此，該核心 f 120不利於縮減封裝結構之整體高度，而不符合電子產 品輕薄短小的發展趨勢。 丹有 丄返八夕層線路之基板的製程中，需先製備一 =層，接著再於該核^層上堆疊介電層及線路層，方能 其製程步驟複雜度不易簡化，故不易縮短製作時二 同時亦不易減少製作成本。 ,，不上所述，由於習知覆晶式球柵陣列（FCBGA)封$ # 術及具多層電路之基板不可避免製程複雜的缺失，因： :何提供—種電路板結構及其製法，以避免習知技街令對 ;降低基板厚度、增加佈線密度、提高製程良率及 4發展的限制，實已成為業界亟欲解決之課題。β 1 20 【發明内容】 接半導辦曰月^主要目的係在提供一種無核心層線路直接連 導r曰之結構及製法，能同時整合半導體晶片與半 载件之接置與電性連接結構，以簡化製程步驟 亚即4成本。 接4:!:另一目的係在提供一種無核心層線路直接連 體日日片之結構及製法，俾能增加細線路佈局之靈活 亚導電路徑，以提升半導體裝置之電性功能。 、· *月之又目的在於提供一種無核心層線路直接連 構及製法，薄化封裝基板而有利於縮減 ::結構之整體高度，以符合電子產品輕薄短小的 15 =成上述及其他目的’本發明之無核心層線路直接 載：：體：片之製法，包括··提供-具有凹槽之金屬承 20 半導容置於該金屬承載板之凹槽中，該 具有相對之一主動表面及-非主動表面，且該 “日狀主動表面具有複數電極塾；填充—㈣ =該凹槽中以固定該半導體晶片，·於該半導體晶片之 表面及同側之該金屬承载板表面形成一第一防焊 = 方焊層形成有複數第一開孔以顯露出該半導體晶片二 該專電極塾，於第_防搜@ 料層表面及第-開孔中該半導體晶 動表面形成_增層結構，該增層結構具有線路層， =該半導體晶片之電極塾電性連接；以及移除該金^承 載板’以顯露該半導體晶片、包覆該半導體晶片之該點著 8 1327345 材料及該第一防焊層之部份表面。 本發明之製法中係藉該金屬承載板支撐該增層結構， 以避免翹曲的發生。 上述之製法中，在移除金屬承載板之步驟時，係可移 除全部之金屬承載板，或部分之該金屬承載板並未移除， 以作為一金屬支撐框架，俾以增加該增層結構之剛性。 10 15 20 上述之製法，其中該增層結包括有至少一介電層、至 少一疊置於該介電層上之線路層、複數導電盲孔以及複數 電性連接墊，且部份該導電盲孔係穿越第一防焊層之該第 一開孔，以電性連接至該半導體晶片之電極墊。 上述之製法，復包括於該增層結構未與該半導體晶片 同側之另一表面形成一第二防焊層，且該第二防焊層表面 形成複數第二開孔，俾以顯露該增層結構之電性連接墊。 本發明復提供一種無核心層線路直接連接半導體晶片 之製法’包括：提供-具有至少—凹槽之金屬承載板；將 一半導體晶片容置於該金屬承載板之凹槽中，該半導體曰 片具有相對之—主動表面及—非主動表面，且該半導體Γ 片之主動表面具有複數電極塾；填充—黏著材㈣該凹: 固定該半導體晶片；於該半導體晶片之主動表面及同曰 :之該金屬承载板-表面形成—增層結構，該增層結構且 有線路層，並與該半導體晶狀電轉電性連接；ς 金屬承載板，以顯露該半導體晶片、包覆該半導體 " 該黏著材料及部份該增層結構之與該半導體晶片同:的^ 面，以及於顯露之該增層結構之與該半導體晶片同側的^ 9 1327345 面形成一第一防焊層。 本發明之製法中係藉該金屬承載板支撐該增層結構， 以避免輕曲的發生。 上述之製法，其中該增層結包括有至少一介電層至 ^豐置於5咳介電層上之線路層、複數導電盲孔以及複數 電性連接墊，且部份該導電盲孔係電性連接至該半導體晶 片之電極墊。 ΒΒ 上述之製法，復包括於該增層結構未與該半導體晶片 同側^另-表面形成-第二防焊層’且該第二防焊層表面 形成複數第二開孔’俾以顯露該增層結構之電性連接塾。 ^發明復提供-種無心層線路直錢接半導體晶片 — G括.-半導體晶片’該半導體晶片具有相對之 ::動：面及一非主動表面’且該半導體晶片之主動表面 具有设數電極墊；—掸s # 15 S層、，，。構，該增層結構具有相對之第 —表面及第二表面，且肖括古ε丨 人私 矛 於兮人+ 1匕括有至少一介電層、至少一疊置 勢 硬數導電目孔以及複數電性連接 且笛—UK焊層，係形成於該增層結構之第-表面， 第-開孔，其中該辦二，曰片之 極塾具有複數 防焊層之該第 I仍4等电1(孔係穿越弟— 電極墊。 汗，以電性連接至該半導體晶片之該些 上述之結構’復包括—穿一 結構之第-# ^ 弟二防焊層，係形成於該增層 孔，俾以二Sr防焊層表面具有複數第二開 s、·'。構之電性連接墊。 20 1327345 吉構1復包括一金屬支撐框架，係形成於該增 s，’。之第—防烊層上，以增加該增層結構之剛性。 片以：：之結構，復包括一黏著材料，係包覆該半導體晶 ,、°之亦增強该半導體晶片與該增層結構之接合 力’並顯露該半導體晶片之非 ° ㈣4之非主動表面，错以有效逸散該 + ¥體日日片於運作時產生之熱量。 10 15 20 因此，本發明係整合半導體半導體晶片與增層处構， 將t導體晶片直接與基板連接，其取代焊料凸塊連接，能 ㈣整合半導體晶片與半導體晶片承載件之接置與電性連 t結構，以簡化製程步驟並節省成本，同時，能增加細線 路佈局之靈活性並且縮短導電路徑’以提升半導體裝置之 電!·生力此同a’ ’ 4化封裝基板而有利於縮減半導體封 結構之整體高度，以符合電子產品輕薄短小的發展趨勢。、 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細 可基於不賴點與應本發日^精神下 種修飾與變更。 請參閱第2A至第2£圖，係為本發明之無核心層線路 直接連接半導體晶片製法較佳實施例之剖面示意圖。^ 須注意的是，該些圖式均為簡化之示意圖，其僅以示专= 11 1327345 架構’因此其僅顯示與本發明有關之 構成’且㈣示之構成並非以實際實施時之數目 '形狀、 :尺寸比例繪製，其實際實施時之數目、形狀及尺寸比例 r種選擇性之設計，且其構成佈局形態可能更為複雜。 貫施例1 如圖2Α所示，首先，提供—具有凹槽211之金屬承載板 21。5亥金屬承載板21的材料可為：紹、銅、鐵或t合金等， 並且利用触刻的方式形成此凹槽2ιι。然後，將—半導體晶 片31合置於4金屬承載板21之凹槽2ιι中該半導體晶月^ 1〇具有相對之-主動表面…及一非主動表面训，且該半導 體晶片3!之主動表面31a具有複數電㈣3ιι，而該半導體 晶片31係以非主動表面31b正對該金屬承載板^之凹槽川 而接置” Θ其中’係可藉—黏著材料（未圖示），以將該 晶片31之該非主動表面31b暫時固定於該凹槽2ιι之底部表 15面。該半導體晶片31係可為主動元件或被動元件，其中， 被動元件係為電阻、電容、電感及上述所組群組之其中一 鲁 者。 然後，如圖2B所示，在容置有該半導體晶片31之該金 屬承載板21的凹槽21丨中以網版印刷或點膠的方式填充一 20黏著材料22於此凹槽211中以固定該半導體晶月31。該黏著 材料22係可為有機薄膜介電材、液態有機樹脂材料或樹脂 片（Prepreg)所組群組之其中一者。 接著，如圓2C所示，於該半導體晶片31之主動表面3U 及同侧該金屬承載板21之表面形成一第一防焊層45，第一 12 1327345 -防焊層μ並形成有複數第—開孔450以顯露出該半導體晶 . 片3 1之該等電極墊3 11。 Μ 再者，如圖2D及圖2D-1所示，於第一防焊層乜的表面 及該些第-開孔45〇中該半導體晶㈣之主動表面3㈣成 5 一7層結構5 ’該增層結構5包括有至少一介電層51、至少 一疊置於該介電層51上之線路層52以及複數導電盲孔”， 且部份該導電盲孔53係穿越第一防焊層45之該第一開孔 450,以電性連接至該半導體晶片31之電極墊3ιι，並二該 增層結構5表面形成有複數電性連接墊54。復於該增層結構 1〇 5表面係形成__第二防焊層55，且第二防焊㈣表面^有 複數第二開孔55〇，以顯露該增層結構5之該些電性連接墊 54。其中，形成該增層結構5之增層技術係為業界所熟知， 故不贅述。圖2D-1所示為本實施例之另一態樣，其中該增 層結構5係首先在第-防焊層45的表面形成—線路層52 15圖2D所示，則是該增層結構5係首先在第一防焊層45的表面 形成一介電層5 1。 I 本發明之製法中係藉該金屬承載板21支樓該增層結構 5，以避免翹曲的發生。 最後，如圖2E及圖2E-1所示，將該金屬承載板21以蝕 20刻之方式完全移除之，而完成本發明之製作流程。圖2Eq 與圖2E之差異可參考圖2D·〗與圖2〇之說明而得知。 實施例2 如圖3及圖3-1所示，本實施例與實施例丨不同處，係在 於移除該金屬承載板21時，部份之該金屬承載板以並未移 13 1327345 -除，而顯露出部分之第一防焊層45，其未被移除之金屬承 •載板21係作為一金屬支撐框架20,，俾以增加該增層結構5 之剛性。其他步驟則與實施例1相同，故不贅述。圖3-1與 圖3之差異可參考圖2D-1與圖2D之說明而得知。 5 實施例3 如圖4A所示，本實施例係與實施例丨不同處，在於該金 屬承載板21表面及半導體晶片之主動表面直接先形成一增 層結構5 ’然後完全移除該金屬承載板2丨以完成本實施例之 製作/;il %。接著，如圖4B所示，由於一般製作增層結構5 10的介電層51所使用之介電材料可能對環境因素較為敏感， 例如吸濕率較高等特性，復可於與該半導體晶片3 1連接之 該增層結構5之一側表面以網版印刷等方式塗覆形成第一 防焊層45 ’以完成本實施例之製作流程。 本發明復提供一種無核心層線路直接連接半導體晶片 15之結構，如圖2E及圖2E_ 1所示，包括：一半導體晶片31 ’ 該半導體晶片31具有相對之一主動表面31a及一非主動表 • 面31b,且s亥半導體晶片31之主動表面31a具有複數電極墊 311，一增層結構5，該增層結構5具有相對之第一表面“及 第二表面5b，且包括有至少一介電層51、至少一疊置於該 20介電層51上之線路層52、複數導電盲孔53以及複數電性連 接墊54 ;以及一第一防焊層45，係形成於該增層結構之第 一表面5a ’且第一防焊層45對應於該半導體晶片3丨之該些 電極墊3 11具有複數第—開孔45〇，其中該增層結構5之部份 該導電盲孔53係穿越第—防焊層45之該第一開孔45〇，以電 14 1327345 性連接至該半導體晶片31之該些電極墊3U。 上述之結構，復包括一第二防焊層55，係形成於該增 層結構5之第二表面兄上，且該第二防焊層55表面具有複數 第二開孔550，俾以顯露該增層結構5之電性連接墊54。 上述之結構，復包括一黏著材料22，係包覆該半導體 晶片3UX保護之，亦增強該半導體晶片31與該增層結構5之 接合力，並顯露該半導體晶片31之非主動表面Mb,藉以有 效逸政e亥半導體晶片31於運作時產生之熱量。 上述之結構，如圖3所示，復包括一金屬支撐框架21，， 係形成於該增層結構5之第—防焊層45上，明加該增層处 構5之剛性。 曰° 15 20 综上所述，由於本發明之基板結構中不需要核心層， I以簡化製程步驟並節省成本外，也能增加細線路佈^之 f活性並且縮料電㈣，以提升半♦體裝置之電性功 2 ’並薄化封裝基板而有利於縮減半導體封裝結構之整體 N度，以符合電子產品輕薄短小的發展趨勢。再者，本 =之製法減少了習知技術中需要另外製作焊料凸塊以Μ 導體晶片電性連接，而能同時整合半導體晶片與半 二^載件之接置與電性連接結構’此外，習知技術令半導 膠:L與基板間需要填膠’製程往更細線路發展時，其填 ^…目對增加’且要避免產生未被填滿的孔洞 難 高’本發明的製法亦免除填膠製程，又簡化； 成本，此外，半導體晶片僅以其主動表面接 ;“構之表面’其非主動表面得以直接顯露，藉以 15 1327345 有效逸散半導體晶月於運作時產生之熱量。 上述實施例僅係為了方便說明而舉例而已本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非 於上述實施例。 【圖式簡單說明】 圖1係習知之覆晶式球栅矩陣封震結構之剖視圖。 # ®2A至叫係本發明第一實施例之製作流程剖視圖。 圖3及圖3-H系本發明第二實施例之結構剖視圖。 1〇 圖从至4B係本發明第三實施例之製作流程剖視圖。 【主要元件符號說明】 10,31 半導體晶片 11 焊料凸塊 ^4,12113,54電性連接墊 123 絕緣層 125,53 導電盲孔 14 錫球 21 金屬承載板 211 凹槽 31a 主動表面 45 第一防焊層 5 增層結構 5b 第二表面 55 第二防焊層 101,311 電極墊 12 基板 122’122a，122b，52 線路層 124 導電通孔 13a,13b 防焊層 15 核心層 21， 金屬支樓框架 22 黏者材料 31b 非主動表面 450 第—開孔 5a 弟一表面 51 介電層 550 第二開孔 1610 15 Limits the possibility of the substrate 12 shrinking the conductive path, thus limiting the further improvement of the electrical quality. In addition, the presence of the core 4 120 makes it possible that the thickness of the substrate 12 is not effectively reduced. If the thickness is thinned, for example, to be reduced to 6 Å or less, the productivity of the substrate 12 will face a severe challenge, and the process yield of the substrate 12 is greatly reduced. Therefore, the core f 120 is disadvantageous for reducing the overall height of the package structure, and Does not meet the trend of thin and light electronic products. In Dan's process of returning the substrate of the Baxi layer, it is necessary to prepare a layer first, and then stack the dielectric layer and the circuit layer on the core layer, so that the complexity of the process steps is not easy to simplify, so it is not easy to shorten At the same time, it is not easy to reduce the production cost. However, as described above, the conventional flip-chip ball grid array (FCBGA) package and the substrate with multi-layer circuit are inevitably complicated in process, because:: What kind of circuit board structure and its preparation method are provided? In order to avoid the knowledge of the street, reducing the thickness of the substrate, increasing the wiring density, increasing the yield of the process and the limitations of the development of the industry has become an issue that the industry is eager to solve. β 1 20 [Summary of the Invention] The main purpose of the invention is to provide a structure and a method for directly connecting a non-core layer line, which can simultaneously integrate the connection and electrical connection of the semiconductor wafer and the half carrier. Structure to simplify the process steps sub-4 cost. 4:!: Another purpose is to provide a structure and method for directly connecting a day-to-day film without a core layer, and to increase the flexible sub-conducting path of the fine line layout to enhance the electrical function of the semiconductor device. , · * Month is also aimed at providing a direct connection and manufacturing method for the core-free layer, thinning the package substrate and facilitating the reduction: the overall height of the structure to meet the light and short length of the electronic product 15 = into the above and other purposes' The coreless layer of the present invention is directly loaded: body: a method for manufacturing a sheet, comprising: providing - a metal bearing having a groove 20 semi-conductive volume placed in a groove of the metal carrier plate, the opposite one of the active surfaces And an inactive surface, and the "day active surface has a plurality of electrodes"; filling - (4) = the recess to fix the semiconductor wafer, forming a surface on the surface of the semiconductor wafer and the surface of the metal carrier The first solder mask = the square solder layer is formed with a plurality of first openings to expose the semiconductor wafer 2, and the semiconductor crystal surface is formed on the surface of the first anti-search layer and the first opening. a layer structure having a wiring layer, = an electrode of the semiconductor wafer is electrically connected; and removing the gold carrier plate to expose the semiconductor wafer, covering the semiconductor wafer with the point 8 1327345 And a part of the surface of the first solder resist layer. The method of the invention supports the build-up structure by the metal carrier plate to avoid the occurrence of warpage. In the above method, when the metal carrier plate is removed The metal carrier plate may be removed, or part of the metal carrier plate is not removed as a metal support frame to increase the rigidity of the buildup structure. 10 15 20 The above method, wherein the increase The junction includes at least one dielectric layer, at least one circuit layer stacked on the dielectric layer, a plurality of conductive blind vias, and a plurality of electrical connection pads, and a portion of the conductive blind vias pass through the first solder resist layer The first opening is electrically connected to the electrode pad of the semiconductor wafer. The above method comprises forming a second solder resist layer on the other surface of the layered structure not on the same side of the semiconductor wafer, and A plurality of second openings are formed on the surface of the second solder resist layer to expose the electrical connection pads of the build-up structure. The present invention provides a method for directly connecting a semiconductor wafer without a core layer line, including: providing - having at least a concave Slot a metal carrier; a semiconductor wafer is received in the recess of the metal carrier, the semiconductor wafer has a relative active surface and an inactive surface, and the active surface of the semiconductor wafer has a plurality of electrodes; Adhesive (4) the recess: fixing the semiconductor wafer; forming an enhancement surface on the active surface of the semiconductor wafer and the same: the surface of the metal carrier plate is formed by a build-up structure having a wiring layer and the semiconductor crystal Electrically-transferred connection; ς metal carrier plate to expose the semiconductor wafer, to cover the semiconductor < the adhesive material and a portion of the build-up structure of the same as the semiconductor wafer, and to increase the exposure The surface of the layer is formed with a first solder mask on the same side of the semiconductor wafer. The method of the present invention supports the build-up structure by the metal carrier to avoid the occurrence of light curvature. In the above method, the build-up layer includes at least one dielectric layer to the circuit layer on the 5 cough dielectric layer, a plurality of conductive blind vias, and a plurality of electrical connection pads, and the conductive via hole system Electrically connected to the electrode pads of the semiconductor wafer. ΒΒ The above method is further included in the layered structure not forming a second solder mask on the same side of the semiconductor wafer and the second solder mask layer is formed on the surface of the second solder resist layer to expose the The electrical connection of the build-up structure. ^Inventive re-providing - a kind of coreless line straight-wire semiconductor wafer - G-.-Semiconductor wafer 'The semiconductor wafer has opposite:: moving surface and an inactive surface' and the active surface of the semiconductor wafer has a number of electrodes Pad; —掸s # 15 S layer,,,. The layered structure has a relative first surface and a second surface, and the outer layer of the ε 丨 私 私 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + And a plurality of electrical connections and a flute-UK solder layer formed on the first surface of the build-up structure, the first opening, wherein the second electrode has a plurality of solder resist layers. Isoelectric 1 (hole through the electrode-electrode pad. Khan, the above-mentioned structure electrically connected to the semiconductor wafer 'comprising - wearing a structure of the -# ^ brother two solder mask, formed in the The layered hole, the surface of the two Sr solder resist layer has a plurality of second open s, · '. The electrical connection pad. 20 1327345 The structure 1 includes a metal support frame, formed in the increase s, '. The first layer of the anti-mite layer is used to increase the rigidity of the layered structure. The structure of the film comprises: an adhesive material covering the semiconductor crystal, and the semiconductor wafer and the build-up structure are enhanced The bonding force 'and reveals the non-active surface of the semiconductor wafer that is not (4) 4, and the fault effectively escapes the + The heat generated by the daily film during operation. 10 15 20 Therefore, the present invention integrates a semiconductor semiconductor wafer and a build-up structure, and directly connects the t-conductor wafer to the substrate, which replaces the solder bump connection and can (4) integrate the semiconductor wafer with The semiconductor wafer carrier is connected and electrically connected to structure to simplify the process steps and save cost. At the same time, the flexibility of the fine circuit layout can be increased and the conductive path can be shortened to improve the power of the semiconductor device. The invention is advantageous for reducing the overall height of the semiconductor package structure in order to meet the trend of lightness and thinness of electronic products. [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific embodiments. Other advantages and effects of the present invention can be readily understood by those skilled in the art. The present invention may also be embodied or applied by other different embodiments, and the details in the present specification may be based on Modifications and changes should be made in accordance with the spirit of this issue. Please refer to Figures 2A to 2, which are the coreless of the present invention. A schematic cross-sectional view of a preferred embodiment of a layered circuit directly connected to a semiconductor wafer. It should be noted that the figures are simplified schematic diagrams, which are only shown in the specification of 11 11327345. Therefore, it only shows the invention. The composition of the composition 'and the four (4) is not drawn in the actual number of implementations, the shape, the size ratio, the actual number of implementations, the shape and the size ratio, and the design of the layout may be more complicated. As shown in FIG. 2A, firstly, a metal carrier plate 21 having a groove 211 is provided. The material of the 5th metal carrier plate 21 may be: sho, copper, iron or t alloy, etc. Forming the groove 2 ι. Then, the semiconductor wafer 31 is placed in the groove 2 ι of the 4 metal carrier plate 21, the semiconductor crystal lens has a relative active surface and a non-active surface training, and The active surface 31a of the semiconductor wafer 3 has a plurality of electric (four) 3 ιι, and the semiconductor wafer 31 is connected to the metal carrying board by the inactive surface 31b. (Not shown), to the non-active surface 31b of the wafer 31 is temporarily fixed to the bottom of the recess of the table 15 2ιι surface. The semiconductor wafer 31 can be an active component or a passive component, wherein the passive component is a resistor, a capacitor, an inductor, and one of the groups described above. Then, as shown in FIG. 2B, a 20-adhesive material 22 is filled in the recess 211 of the metal carrier plate 21 of the semiconductor wafer 31 by screen printing or dispensing. The semiconductor crystal 31 is fixed. The adhesive material 22 may be one of a group of an organic thin film dielectric material, a liquid organic resin material, or a resin sheet (Prepreg). Then, as shown by the circle 2C, a first solder resist layer 45 is formed on the active surface 3U of the semiconductor wafer 31 and the surface of the metal carrier 21 on the same side, and the first 12 1327345 - the solder resist layer μ is formed with a plurality of An opening 450 for exposing the electrode pads 3 11 of the semiconductor chip 31. Further, as shown in FIG. 2D and FIG. 2D-1, the active surface 3(4) of the semiconductor crystal (4) is formed into a 5-7 layer structure 5' on the surface of the first solder mask layer and the first opening 45〇. The build-up structure 5 includes at least one dielectric layer 51, at least one circuit layer 52 stacked on the dielectric layer 51, and a plurality of conductive blind vias, and a portion of the conductive vias 53 pass through the first solder resist The first opening 450 of the layer 45 is electrically connected to the electrode pad 3 ι of the semiconductor wafer 31, and the surface of the build-up structure 5 is formed with a plurality of electrical connection pads 54. The build-up structure 1 〇 5 The surface is formed with a second solder mask 55, and the second solder resist (4) surface has a plurality of second openings 55A to expose the electrical connection pads 54 of the build-up structure 5. The layering technique of the layer structure 5 is well known in the art and will not be described. Fig. 2D-1 shows another aspect of the embodiment, wherein the layered structure 5 is first on the surface of the first solder resist layer 45. Forming the circuit layer 52 15 as shown in FIG. 2D, the build-up structure 5 first forms a dielectric layer 51 on the surface of the first solder resist layer 45. The metal carrier board 21 supports the build-up structure 5 to avoid the occurrence of warpage. Finally, as shown in FIG. 2E and FIG. 2E-1, the metal carrier board 21 is completely removed by etching. The process of the present invention is completed. The difference between FIG. 2Eq and FIG. 2E can be seen by referring to the description of FIG. 2D and FIG. 2 . Embodiment 2 As shown in FIG. 3 and FIG. 3-1 , the embodiment and the implementation are as shown in FIG. 3 and FIG. The difference is that when the metal carrier 21 is removed, part of the metal carrier is removed by 13 1327345 - and the first solder mask 45 is exposed, which is not removed. The metal carrier plate 21 is used as a metal supporting frame 20 to increase the rigidity of the layered structure 5. The other steps are the same as those in the first embodiment, and therefore will not be described. The difference between FIG. 3-1 and FIG. 3 can be referred to. 2D-1 and FIG. 2D. 5 Embodiment 3 As shown in FIG. 4A, this embodiment differs from the embodiment in that the surface of the metal carrier 21 and the active surface of the semiconductor wafer are directly formed first. A build-up structure 5' then completely removes the metal carrier plate 2' to complete the fabrication of this embodiment / il %. As shown in FIG. 4B, since the dielectric material used for the dielectric layer 51 of the build-up structure 5 10 is generally sensitive to environmental factors, such as high moisture absorption rate, it can be connected to the semiconductor wafer 31. One side surface of the build-up structure 5 is coated with a first solder resist layer 45' by screen printing or the like to complete the fabrication process of the embodiment. The present invention provides a coreless layer directly connected to the semiconductor wafer 15 The structure, as shown in FIG. 2E and FIG. 2E-1, includes: a semiconductor wafer 31'. The semiconductor wafer 31 has a pair of active surfaces 31a and an inactive surface 31b, and the active surface 31a of the semiconductor wafer 31 has a plurality of electrode pads 311, a build-up structure 5 having opposite first and second surfaces 5b, and including at least one dielectric layer 51, at least one of which is disposed on the dielectric layer 51 The upper circuit layer 52, the plurality of conductive blind vias 53 and the plurality of electrical connection pads 54; and a first solder resist layer 45 are formed on the first surface 5a' of the buildup structure and the first solder resist layer 45 corresponds to The semiconductor wafer 3 The pole pad 3 11 has a plurality of first opening 45 〇, wherein a part of the conductive layer 53 of the layered structure 5 traverses the first opening 45 第 of the first solder resist layer 45, and is connected by electricity 14 1327345 To the electrode pads 3U of the semiconductor wafer 31. The structure includes a second solder mask 55 formed on the second surface of the build-up structure 5, and the second solder resist 55 has a plurality of second openings 550 on the surface thereof to expose the The electrical connection pads 54 of the build-up structure 5 are connected. The above structure comprises an adhesive material 22 which is coated to protect the semiconductor wafer 3UX, and also enhances the bonding force between the semiconductor wafer 31 and the build-up structure 5, and exposes the inactive surface Mb of the semiconductor wafer 31. The heat generated by the Yikong e-chip 31 during operation is effective. The above structure, as shown in Fig. 3, further includes a metal supporting frame 21 formed on the first solder resist layer 45 of the build-up structure 5 to increase the rigidity of the build-up structure 5.曰° 15 20 In summary, since the core layer is not required in the substrate structure of the present invention, in order to simplify the process steps and save costs, it is also possible to increase the activity of the fine circuit cloth and reduce the electricity (4) to increase the half. ♦ The electrical work of the body device 2 'and thinning the package substrate is beneficial to reduce the overall N degree of the semiconductor package structure to meet the trend of thin and light electronic products. Furthermore, the method of the present invention reduces the need for additional solder bumps in the prior art to electrically connect the conductor wafers, and simultaneously integrates the connection and electrical connection structures of the semiconductor wafer and the semiconductor carrier. The conventional technology makes the semi-conductive adhesive: need to be filled between the L and the substrate. When the process is developed to a finer line, the filling is increased, and the unfilled hole is difficult to be high. It eliminates the filling process and simplifies; cost, in addition, the semiconductor wafer is only connected by its active surface; the surface of the structure is directly exposed by its non-active surface, so that 15 1327345 effectively dissipates the heat generated by the semiconductor crystal during operation. The above-mentioned embodiments are merely exemplified for the convenience of the description, and the scope of the claims of the present invention is based on the scope of the patent application, and is not the above embodiment. [Simplified description of the drawings] Fig. 1 is a conventional flip-chip type Fig. 3 and Fig. 3-H are cross-sectional views showing the structure of the second embodiment of the present invention. Fig. 3 and Fig. 3H are sectional views showing the structure of the second embodiment of the present invention. 4B is a cross-sectional view showing the manufacturing process of the third embodiment of the present invention. [Main component symbol description] 10, 31 semiconductor wafer 11 solder bumps ^4, 12113, 54 electrical connection pads 123 insulating layer 125, 53 conductive blind holes 14 tin Ball 21 metal carrier plate 211 groove 31a active surface 45 first solder resist layer 5 buildup structure 5b second surface 55 second solder mask layer 101, 311 electrode pad 12 substrate 122'122a, 122b, 52 circuit layer 124 conductive via 13a , 13b solder resist layer 15 core layer 21, metal branch frame 22 adhesive material 31b inactive surface 450 first opening 5a younger surface 51 dielectric layer 550 second opening 16