TWI321836B - Semiconductor chip package and method for manufacturing the same - Google Patents

Description

[Technical Field] The present invention relates to a semiconductor wafer package structure and a method of fabricating the same, and more particularly to a semiconductor wafer package structure having a heat sink and a method of fabricating the same. [Prior Art] With the rapid development of electronic technology, the requirements for the functions of electronic products have increased, and electronic products are required to develop in a light, thin, short, and small direction. However, due to the increase in functionality, such electronic components and integrated circuits consume more energy than previous electronic components, which would result in the waste heat required to be removed from the semiconductor components to avoid such components, circuits, and electronics. The module is damaged due to overheating. Therefore, while developing in this direction, the heat dissipation problem of many components has also arisen, and it needs to be solved urgently. Therefore, in most cases, it is necessary to use a heat sink to dissipate the waste heat generated by the electronic device and the integrated circuit. At present, a general method is to attach a heat dissipating member to the back surface of a semiconductor wafer, so that heat generated by the operation of the semiconductor wafer is quickly conducted to the heat dissipating member, and then the heat dissipating member transmits the heat to the peripheral environment. For example, when a high-power package structure is in operation, a large amount of heat is generated. When a heat sink is used to help dissipate heat of the package structure, the heat sink is generally directly attached to the inactive surface of the semiconductor wafer by using a thermal conductive adhesive. However, thermal conductive adhesives generally have better thermal conductivity, but generally do not have sufficient adhesion, especially at the interface between the semiconductor wafer and the heat sink, which does not form sufficient adhesion. In this way, in the subsequent reliability measurement 3, 忒, it is easy to cause delamination due to heat and cause the heat sink to fall off. Thus, there is a need for a semiconductor wafer package construction and method of fabricating the same that overcomes or at least ameliorates the aforementioned prior art. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a semiconductor wafer package structure having a heat sink disposed thereon. Another object of the present invention is to provide a method for fabricating a semiconductor

The chip package construction ' can be arranged in an array on a plurality of semiconductor wafers simultaneously with a heat sink. In order to achieve the above and other objects, the present invention provides a semiconductor wafer package structure having the present invention, which substantially comprises a semiconductor wafer having a plurality of metal bumps disposed thereon. a plurality of connection pads having opposite upper and lower surfaces, wherein the semiconductor wafer is mechanically and electrically attached to the upper surface of the connection by the metal bumps; the heat sink has

The upper surface and the lower surface of the heat dissipating member have a central transport region and a peripheral region; the adhesive layer is located between the f-plane of the semiconductor wafer and the lower surface of the yellow heat member to attach the heat dissipating member On the semiconductor wafer; and - the encapsulant covers the aforementioned semiconductor wafer, the connection pad, the adhesive shoulder, and the peripheral surface of the upper surface of the heat sink, and the surface of the connection pad and the upper surface of the member The central area is exposed to the sealant. Preferably, the semiconductor 3-day package structure of the watch further comprises a plurality of heat-dissipating fins disposed on the central portion of the upper surface of the heat-dissipating surface to increase the heat-dissipating efficiency. 4: Another semiconductor chip package structure according to the present invention

The semiconductor wafer is located on a wafer holder, wherein the semiconductor germanium: 3 includes a plurality of bonding pads disposed on the front side thereof to J

2::==: 2 periphery; a plurality of connecting wires are electrically connected to S: a surface, the upper surface of the heat dissipating member has a central region and a ::: 2, the adhesive layer is located on the front surface of the semiconductor wafer and the heat sink: The heat dissipating member is attached to the semiconductor wafer; the semiconductor wafer, the connecting port, the connecting wire, and the peripheral portion of the upper surface of the bonding heat member are exposed to the sealing body at a central portion of the surface. The == heat sink includes at least one bump at 苴 别 加上 加上 加上 加上 加上 加上 。 。 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Phelght) u This method is for a method of fabricating a semiconductor wafer chipping structure. The method to V includes the steps of: providing two arrays of cells and a plurality of cuts == some; V111 early 70 is provided with a plurality of connecting arts; a plurality of semiconductor crystals are connected to the upper surface of the lead frame; a plurality of semiconductor wafers are attached to the semiconductor; and a heat sink is adhered to the surface by the adhesive layer In the Japanese film, the heat dissipating plate includes at least a plurality of heat dissipating members corresponding to the half body and the two heat sinks, and a plurality of connecting heat radiating members, the upper surface of the heat dissipating member has a central region and a peripheral region - and a sealant The semiconductor wafer, the bonding pad, the adhesive layer, and the peripheral region of the upper surface of each of the heat dissipating members are coated to form a 1 surface: and a surface of each of the heat dissipating members: the region is exposed to η:. In a specific embodiment, the step of forming the foregoing molded article includes providing a molding die having an upper die and a die, wherein the upper die and the lower die together define a cavity, and: a plurality of a protrusion portion; the close clamping mold is fastened to the upper surface of the corresponding heat sink by the lead frame and the ^ part: a mother: a dog: a gap between the peripheral regions of the upper surface of the heat sink; = , _ant) is injected into the cavity; the adhesive material is hardened; the mold is taken out to remove the molded article. The present invention further provides a method of fabricating a semiconductor wafer package structure. This material is provided first - no (four) foot guide _ 'the unit having a plurality of arrays arranged and a plurality of dicing streets disposed between the units, each unit is provided with a wafer holder and a plurality of connection pads are located around the wafer holder . A plurality of semiconductor wafers are then bonded to the wafer holder of the lead frame. Next, the connection of the aforementioned semiconductor wafer to the lead frame of the lead frame is electrically connected. Subsequently, a plurality of adhesive layers are formed on the aforementioned semiconductor wafer. Next, a heat dissipation plate is attached to the semiconductor wafer by an adhesive layer, wherein the heat dissipation plate includes at least a plurality of heat dissipation phases corresponding to the semiconductor crystal # and a plurality of junctions (four) connecting the heat dissipation components, each of the heat dissipation components The upper surface has one; the central area and the surrounding area. Then, the encapsulant encapsulates the above-mentioned semiconductor: the layer and the periphery of the upper surface of each of the heat dissipating members to form a chess mouth; the pro-sister holds the nr 圭 and connects the lower surface of the crucible and each of the heat dissipation 1321836 The central area of the upper surface is exposed to the molded article. Finally, the above mold is cut, and X is fabricated into individual semiconductor wafer package structures. When electrically connecting the semiconductor chip to the connection pad of the lead frame, it is preferable to use a plurality of connecting wires, and the heat dissipating members at least include a bump portion on the lower surface thereof, and the thickness of the bump portion is spit (4) The thickness is greater than the arc height of the connecting line. The above and other features, advantages and other aspects of the present invention will become more fully understood. In June, a semiconductor wafer package structure 10a according to an embodiment of the present invention is shown in Fig. 6a, which is a flip chip (FC) package structure. The semiconductor chip package structure 10a includes a semiconductor wafer 1〇2 having a plurality of metal bumps 1〇4 disposed on a front surface thereof. A plurality of connection pads 1〇6 have opposite upper and lower surfaces. A plurality of connection pads 1〇6 are disposed under the metal bumps 1〇4 of the semiconductor wafer, and each of the connection pads 1〇6 has a relatively upper surface and a lower surface. The semiconductor wafer 1 2 is mechanically and electrically attached to the upper surface of the connection pads 106 by the metal bumps 104 which it has. The back side of the semiconductor wafer 102 is further coated with an adhesive layer 1 〇 8, preferably a Thermal Interface Material (TIM). The heat dissipating member 11 〇 has a relatively upper surface and a lower surface, and the upper surface of the heat dissipating member 110 has a central portion 112 and a peripheral portion 114, and the peripheral edge of the heat dissipating member 110 further has a connecting portion 116. The heat dissipating member 110 is disposed on the back surface of the semiconductor wafer 1 and the adhesive layer 108 is disposed between the back surface of the semiconductor wafer 102 and the lower surface of the heat dissipating member 110, thereby attaching the heat dissipating member 1 to the conductive conductor wafer 102. . The π-discriminating sheet 102, the connection pad 106, the adhesive layer 108, and the heat dissipating member 110 are on the lower surface of the 莜蛩 莜蛩 〇鄱 〇鄱 层 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及Expose the connection. "The central region m of the upper surface of the mountain 1", refer to FIG. 6b, which is a semi-conductor chip package structure. According to another embodiment of the present invention, the +conductor chip package structure 100b is substantially the same as the first The semiconductor semi-conducting micro 3 ^ ^ . ^ raA Zhao Ri 9-piece package structure 100a the same 'the difference is that the semiconductor wafer is sealed 6 Η j. The structure 1 〇〇 b further includes a plurality of heat-dissipating fins 120 disposed in The heat dissipating member 11 ^ lB , , ^ is on the central region 112 of the upper surface, thereby further enhancing the heat dissipation performance of the semiconductor wafer package s ^ . Ha ^ is the sealing structure i 〇〇 b. Reference is made to FIG. 11A, which illustrates a semiconductor chip package structure according to another embodiment of the present invention, which is a wire bonding ono au package structure 2〇〇a including a semiconductor wafer. 202, which is located on the wafer holder 220, wherein at least a plurality of wafer pads (not shown) are disposed on the front surface of the + conductor wafer 202. A plurality of connections are formed on the periphery of the semiconductor wafer 2G2, wherein each of the ports 206 is further free of a metal coating (not shown) on the upper surface. In the embodiment:, the metal covering layer comprises at least a recording film and a gold film or film on the nickel crucible. A plurality of connecting wires 204 are electrically connected to the upper surface of the wafer pads and the connection pads 2〇6 on the front surface of the semiconductor wafer 2〇2. The back surface of the semiconductor wafer 2〇2 is further coated with an adhesive layer 208, which is preferably made of a thermal interface material. The heat dissipating member 210 has an opposite upper surface and a lower surface, and has an upper surface having a central portion 212 and a peripheral portion 214, and the periphery of the heat dissipating member 210 has a connecting portion 216. The heat sink 210 is disposed on the back surface of the semiconductor wafer 202, and the adhesive layer 208 is located between the back surface of the semiconductor wafer 202 and the lower surface of the heat sink 210, thereby attaching the heat sink 210 to the semiconductor wafer 202. On the back. The encapsulant 218 covers the semiconductor wafer 202, the connection line 204, the connection pad 206, the adhesive layer 208, and the heat sink.

The peripheral region 214 of the upper surface of 210 exposes the surface below the connection pad 206 and the central region 212 of the upper surface of the heat sink 210. In the preferred embodiment, the heat dissipating member 210 includes at least one bump portion 222 on the lower surface thereof, and the thickness of the bump portion 222 plus the thickness of the adhesive layer 208 is greater than the arc of the connecting line 204 (l00p height). ) to avoid the semiconductor wafer 202 contacting the line arc of the connection line 204. Please refer to the lib diagram, which illustrates a semiconductor chip package structure 2GGb according to another embodiment of the present invention. The semiconductor chip package structure is substantially the same as the semiconductor chip package structure a of the second embodiment. The difference is that the semiconductor chip package structure 200b has a plurality of heat dissipation fins 224 disposed on the upper surface of the heat sink 210. On the central area 212, borrow

The heat dissipation area of the heat sink 21 is increased in a stepwise manner, and thereby the heat dissipation performance of the semiconductor package structure 200b is improved. The aforementioned package structure is transmitted in a manner similar to other leadless devices or free boards. The printed circuit board can be connected to the substrate (e.g., the printed circuit board, for example, by the connection/screen printing (SCreenPnnt) at the bottom of the package structure to correspond to (4) (10)). Then use the pattern of the front 塾 (10) or even (4) to reflow. It can be understood that the 9 1321836 connection pad 106 or the connection port 206 exposed on the bottom of the package structure of the water on the printed circuit board may be first printed with a solder paste and then mounted to the substrate. It is worth noting that during the reflow process described above, the adhesive layer 108 or the adhesive layer 208 disposed between the heat sink and the 'semiconductor wafer is susceptible to thermal expansion - resulting in delamination at the heat sink/sealant interface ( Delamination), thus affecting the reliability of the package construction. Therefore, the package structure of the present invention is designed such that the peripheral region 114 of the upper surface of the heat dissipating member 110 is covered by the encapsulant 118, so that the heat dissipating member 110 can be reinforced and fixed in the encapsulant 118, thereby effectively improving the adhesion layer. Question φ caused by thermal expansion. The manufacturing method of the semiconductor wafer package structure 10a according to the present invention will be described below with reference to Figs. 1 to 5. 1 shows an outer lead lead frame 300 comprising a plurality of units 302 arranged in an array and a plurality of dicing streets 304 disposed between the units 302. Each unit 302 is provided with a plurality of connection pads. 106 (not shown in Figure 1). Next, a plurality of semiconductor wafers 102 are provided, wherein a plurality of metal bumps 1 〇 4 are disposed on the front surface of each of the semiconductor wafers 1 〇 2 . These semiconductor wafers 102 are then mechanically and electrically connected to the upper surface of the connection pads 106 on the lead frame 300 using the metal bumps 104 thereon. Next, a plurality of adhesive layers 108 are formed on the back surface of the semiconductor wafers 102 by, for example, coating, as shown in Figs. 2 and 6a. Among them, the material of the adhesive layer 108 is preferably a thermal interface material. After the adhesive layer 108 is disposed, a heat sink 306 is bonded to the semiconductor wafers 1 (32. The heat sinks 306 are at least connected to the plurality of heat sinks 110 of the semiconductor wafers 102. A is connected to the plurality of connecting portions 116 of the heat dissipating members uo, as shown in Fig. 3 and the second block. Further, 'the upper surface of each of the heat dissipating members 110 has a central//, peripheral region 114 (see Fig. 6a). 'Performing the encapsulation process. First, a molding die (unbounded ~) is provided which has an upper die and a lower die, wherein the upper die and the lower die -| die, and the upper die includes a plurality of protrusions The mold is then tightly: clamped onto the lead frame _ so that each of the protrusions of the upper mold closely abuts against the central portion 112 of the upper surface of the corresponding heat sink 11 并且 and the upper mold and the heat sink There is a gap between the peripheral regions U4 of the upper surface of the ιι. Therefore, in the subsequent filling step, the sealing material can cover only the peripheral region of the upper surface of the heat dissipating member 110 by the action of the mold. 114, but can not enter each of the heat sink 110 The central region 112 of the upper surface. After the setting of the mold is completed, the sealing material is injected into the cavity by a conventional plastic molding method, such as transfer molding, and the sealing body 118 is covered. The semiconductor wafer 1 〇 2, the connection 塾 106, the adhesive layer 1 〇 8 and the peripheral region 114 of the upper surface of each of the heat dissipation members 110. Curing the adhesive material to form a molded article 'and the connection pad 106 The lower surface and the central region 112 of the upper surface of each of the heat dissipating members 11 are exposed. In this embodiment, during the hardening process, the molding compound of the sealing material shrinks and the upper surface of the heat dissipating member 110 The peripheral area 114 is subjected to a tension. Therefore, the heat-dissipating member 110 is effectively fixed to the semiconductor wafer by the hardened plastic, and the cutting path between the respective units is made = an individual semiconductor chip package structure is prepared. Hidden, such as the structure of the first. With the heat sink 110, the heat dissipation capability of the structure 100a can be effectively illustrated. _ Japanese chip package semiconductor chip package structure 1 〇〇b described semiconductor day W package structure _ system The method is the same, 1 difference ί = = 10% heat dissipation of the chip package structure (4). The upper surface of the = £ field 112 is provided with a plurality of heat dissipation fins m, so the center of the protrusion of the upper mold of the mold centering has The recess, the second = U0 heat dissipation Korean film 12 〇. The semiconductor chip package structure two ===120 can increase the heat dissipation area 'so can enter -4 liters + conductor aa>; package structure (10) b heat dissipation efficiency. 7 to 1G, which disclose a method of manufacturing the semiconductor wafer package structure 200a of the present invention. Referring to FIG. 7, a plurality of semiconductor wafers 2 2 are made of a conductive paste layer (not shown in FIG. 7). For example, silver paste is adhered to a wafer holder 22G (not shown in Fig. 7) fixed on a lead frame. The lead frame includes a plurality of arrays arranged in an array and a plurality of dicing streets - and between the units 402, wherein each of the units is provided with a wafer holder 220 (not shown in FIG. 7). And a plurality of connection pads 2〇6 (not shown in FIG. 7) are located around the wafer holder 220, wherein each of the semiconductor wafers 202 includes at least a plurality of wafer pads (not shown) disposed therein The front surface and the upper surface of each of the connection pads 206 are further provided with a metal coating layer (not 12 1321836 is not shown in the figure). Preferably, the metal coating layer comprises at least a recording film and a gold film or film on the nickel film. After electrically connecting the wafer pads on the front surface of the semiconductor wafer 2G2 and the upper surface of the connection pad (see the figure) by using a plurality of connecting wires 204 (see FIG. Ua), a plurality of adhesive layers are formed by, for example, coating. 208 are located on the front side of these semiconductor wafers 202, respectively, as shown in FIG. The material of the adhesive layer 208 is preferably a thermal interface material. Next, a heat dissipation plate 406 is provided, and the heat dissipation plate 406 is attached to the semiconductor wafer by the adhesive layer 2〇8, and the heat dissipation plate includes at least a plurality of heat dissipation parts corresponding to the semiconductor wafers. 21〇 and a plurality of connecting portions 216 connecting the heat dissipating members 210, and the upper surface of each of the heat dissipating members 210 has a central portion 212 and a peripheral portion 214, as shown in FIGS. 8 and 11a. In the preferred embodiment, the heat dissipating member includes at least one bump portion 222 (see FIG. 11a) on the lower surface thereof, and the thickness of the bump portion 222 plus the thickness of the adhesive layer 2〇8 is greater than the connecting line 204. The arc 咼 (refers to the distance between the front side of the wafer 2〇2 and the apex of the connecting line 2〇4 line arc) prevents the semiconductor wafer 202 from contacting the line arc of the connecting line 2〇4, as shown in FIG. Subsequently, a mold (not shown) is provided having an upper mold and a lower mold defining a cavity together, wherein the upper mold further includes a plurality of protrusions. The mold is then tightly clamped to the lead frame 4〇〇, so that each protrusion of the upper mold closely abuts against the central portion 212 of the upper surface of the corresponding heat sink 21〇, and the upper mold and the heat dissipation There is a gap between the peripheral regions 214 of the upper surface of the member 21' to prevent the sealing material from entering the central region 212 of the upper surface of one of the heat dissipating members 210 per 1321836, but can enter the upper surface of the heat dissipating member 210. On the edge area 214. Next, the sealant is injected into the cavity by, for example, transfer molding, and the sealant 218 sealant 218 is overlaid on the semi-conductive wafer 202, the connection line 204, the connection pad 206, the adhesive layer 2〇8, and The peripheral region 214 of the upper surface of the heat sink 210 is 'applied to the lower surface of the connection pad 206 and the central region 212 of the upper surface of the heat sink 21〇. The rubber material is then hardened and molded. During the hardening process, the plastic of the sealant material shrinks and exerts a strain on the peripheral region of the upper surface of the heat sink 210. Therefore, the heat dissipating member 210 is fixed to the semiconductor wafer 202 by the hardened plastic. At this time, the mold can be opened to take out the molded article, as shown in Fig. 9 and Fig. lia. The mold article ′ is then cut along the scribe line 404 between the cells 402 to produce an individual semiconductor wafer package construction 200a, such as that shown in Figure Ua. By means of the heat sink 21, the heat dissipation performance of the semiconductor chip package structure 200a can be greatly improved, and the life of the conductor wafer 202 can be increased. The manufacturing method of the semiconductor wafer package structure 200b is substantially the same as the manufacturing method of the semiconductor chip package structure 2a, except that the central region 212 of the upper surface of the heat sink 210 of the semiconductor chip package structure 200b is separately provided. There are a plurality of fins 224, so that there are recesses in the center of the protrusions of the upper mold of the mold used in the encapsulation process, in the valley, the interior, and the fins 224 on the member 210. Similarly, The heat dissipation fins 224 additionally provided on the semiconductor chip package structure 200b can increase the heat dissipation area to effectively improve the heat dissipation efficiency. 1321836 It can be understood that although the semiconductor chip package structure manufacturing method according to the present invention is directed to the use of no external lead wires The rack is discussed in detail as a wafer carrier, however the method of the present invention can also be applied to the design of a substrate (e.g., an organic substrate, a film substrate, or a ceramic substrate) as a wafer carrier. Although the present invention has been It is disclosed in the foregoing preferred embodiments, which are not intended to limit the invention, and anyone skilled in the art Without departing from the spirit and scope of the present invention, it can be made to a variety of modifications and changes, the scope of the present invention so as defined by the following claims and their equivalents of the scope of the appended. Φ

15 1321836 [Simplified illustration of the invention] semiconductor wafer package according to the invention - embodiment structure diagram according to the invention - preferred embodiment of the semiconductor chip package assembly = semiconductor wafer package according to another preferred embodiment of the invention Fig. 7 to Fig. 1G: It is a half (four) W dragon knot method of the disclosed example. Structure L;:: A semiconductor wafer package structure diagram according to another embodiment of the present invention. Semiconductor wafer package main component symbol description according to another embodiment of the invention 100b semiconductor wafer package structure 104 metal bump 108 adhesive layer 112 central region 116 connection portion 120 heat sink fin semiconductor wafer sealing structure 204 metal bump 208 adhesive Layer 102 106 110 114 118 semiconductor wafer package structure... semiconductor wafer connection pad heat sink peripheral region encapsulation body semiconductor wafer sealing structure 202 semiconductor wafer 206 connection pad 1321836 210 heat sink 212 central region 214 peripheral region 216 connection portion 218 sealing knee Body 220 wafer holder 222 bump portion 224 heat sink fin 300 lead frame 302 port 〇 early morning 304 cutting channel 306 heat sink 400 lead frame 402 — early 404 cutting channel 406 heat sink

17

Claims (1)

X. Patent application scope: _ h A semiconductor chip package structure comprising at least a semiconductor wafer located at a 曰/匕. electrically connected to the wafer carrier: 7 a semiconductor device having a heat sink attached to the semiconductor B2 has a -t central area and a peripheral area on the upper surface of the hot part of the heat piece wafer, the wafer is bound and the central area of the scattering 2;:: upper 'and the upper surface of the heat sink Zhao . The heat sink has a connecting portion, and the connecting side is exposed to the sealing compound. The semiconductor chip packaging structure as described in claim hereinafter, wherein: the semiconductor wafer has a plurality of metal bumps (metai bump) Provided on an active surface thereof; the wafer carrier comprises a plurality of connecting ports having opposite upper and lower surfaces; the semiconductor wafer is mechanically and electrically connected by the metal bumps (mechanically and electrically Attached to the upper surface of the connection pad; a heat dissipating member having an opposite upper surface and a lower surface, the upper surface of the heat dissipating member having a central region and a peripheral region; 1321836 the lower surface of the connecting pads is exposed The encapsulant. 3. The semiconductor wafer package structure of claim 2, further comprising a plurality of heat sink fins disposed in the central region of the upper surface of the heat sink. 4. The semiconductor wafer package structure of claim 2, further comprising an adhesive layer between the backside surface of the semiconductor wafer and the lower surface of the heat sink for using the heat sink Attached to the semiconductor wafer. 5. The semiconductor wafer package structure of claim 4, wherein the material of the adhesive layer is a Thermal Interface Material (TIM). 6. The semiconductor wafer package structure of claim 1, wherein: the s-chip carrier comprises a wafer holder and a plurality of connection pads are located around the wafer holder; the semiconductor wafer is attached to the wafer In the socket, the semiconductor wafer includes a plurality of bonding pads disposed on the front surface thereof; a plurality of connecting wires electrically connecting the wafer pads and the upper surfaces of the connecting pads; The upper surface and the lower surface of the heat dissipating member have a central region and a peripheral region; and the lower surfaces of the connecting pads are exposed to the encapsulant. The semiconductor chip package structure 2 of claim 6 further comprising an adhesive layer between the front surface of the semiconductor wafer and the lower surface of the heat sink for attaching the heat sink In the semiconductor wafer: wherein the heat sink comprises at least a bump portion on a surface of the τ, and the thickness of the bump portion plus the thickness of the adhesive layer is greater than an arc height of the connecting lines. The semiconductor wafer package structure of claim 7, wherein the material of the adhesive layer is a thermal interface material. The semiconductor wafer package structure of claim 6, wherein the central portion of the upper surface of the heat sink is further provided with a plurality of heat dissipation tabs. The semiconductor wafer package structure of claim 6, wherein the upper surface of each of the connection pads is further provided with a metal coating layer. 11. The semiconductor wafer package structure of claim 10, wherein the metal cap layer comprises at least a ruthenium film and a gold film or a sharp film is located on the film. The semiconductor wafer sealing structure of the invention of claim 2, wherein the wafer carrier is an outer lead lead frame. 13. The semiconductor wafer package structure of claim 2, wherein the wafer carrier is a substrate. 14. A method of fabricating a semiconductor wafer package structure, comprising: providing a wafer carrier having a plurality of arrayed cells; and providing a plurality of semiconductor wafers to the cell electrical connection of the wafer carrier Mounting the semiconductor wafers to the cells of the wafer carrier. The heat sink is attached to the semiconductor wafers, wherein the heat sink comprises at least a plurality of heat sinks corresponding to the semiconductor wafers and connecting the heat sinks a plurality of money joints, each of which has a central area and a peripheral area; the eight sealant covers the semiconductor wafers, the connection pads, and the upper surface of each of the heat sinks Forming a molded article, and exposing the lower surface of the money 2 and the central region of each of the upper surfaces of the heat dissipating members to the molded article; and cutting the molded article to obtain an individual semiconductor Wafer package construction. The method of manufacturing a semiconductor wafer package structure according to claim 15, wherein the semiconductor wafers are provided on the leadless lead frame in a flip chip bonding manner. 17. The method of manufacturing a semiconductor wafer package structure according to claim 14, wherein the step of forming the molded article comprises at least: providing a molding die having an upper die and a lower die, wherein the upper die And the lower mold defines a cavity together, the upper mold includes a plurality of protrusions, and the mold is clamped on the wafer carrier so that each of the protrusions is fastened against the corresponding heat dissipation member a central portion of the upper surface, and the upper mold and the peripheral portion of the upper surface of the heat dissipating member have a gap; injecting an encapsulant into the cavity; hardening the encapsulant; and opening The mold is to take out the molded article. 18. The method of fabricating a semiconductor wafer package structure according to claim 14, wherein the step of attaching the heat sink to the semiconductor wafers further comprises forming a plurality of adhesive layers on the semiconductor wafers. 19. The method of fabricating a semiconductor wafer package structure according to claim 14, wherein the central portion of the upper surface of the heat dissipating member is further provided with a plurality of heat dissipating fins. The method of manufacturing a semiconductor wafer package structure according to claim 14, wherein the wafer carrier is a substrate. 21. A method of fabricating a semiconductor chip package structure, comprising: providing a lead frame having a plurality of arrayed cells and a plurality of dicing streets disposed between the cells, each of the cells being provided with a wafer carrier And a plurality of connection pads are disposed around the wafer holder; bonding a plurality of semiconductor wafers to the wafer holders of the lead frame; electrically connecting the semiconductor wafers to the connection pads of the lead frame; forming a plurality of Adhesively bonding the semiconductor wafers; attaching a heat sink to the semiconductor wafers, wherein the heat sink comprises at least a plurality of heat sinks corresponding to the semiconductor wafers and a plurality of heat sinks a connecting portion, each of the upper surfaces of the heat dissipating members has a central region and a peripheral region; the encapsulant covers the semiconductor wafer, the connecting pads, and the peripheral region of the upper surface of each of the heat dissipating members Forming a molded article, and exposing the central portion of the lower surface of the connection pads and the upper surface of each of the heat dissipation members to the molded article And cutting the molded article to obtain the individual semiconductor chip package construction. 22. The method of manufacturing a semiconductor wafer package structure according to claim 21, wherein the step of forming the molded article comprises at least: providing a mold having an upper mold and a lower mold, wherein the upper mold and the lower 23 1321836 The molds together define a cavity, the upper mold includes a plurality of protrusions; and the mold is tightly clamped on the lead frame such that each of the protrusions is fastened against the upper surface of the corresponding heat dissipation members a central region, and the upper mold and the peripheral portion of the upper surface of the heat dissipating member have a gap; injecting a sealing material into the cavity to harden the sealing material; and opening the mold to take out the molding . 23. The method of fabricating a semiconductor wafer package according to claim 21, wherein the plurality of connecting lines are electrically connected to the plurality of connecting pads of the lead frame. The heat dissipating members include at least one bump portion on a lower surface thereof, and the thickness of the bump portion plus the thickness of the adhesive layer is greater than an arc height of the connecting lines. 24. The method of fabricating a semiconductor wafer package structure according to claim 21, wherein a surface of each of the connection pads is further provided with a metal coating layer. The method of fabricating a semiconductor wafer package structure according to claim 24, wherein the metal cap layer comprises at least a nickel film and a gold film or a palladium film on the nickel film. 26. The method of fabricating a semiconductor wafer package structure according to claim 21, wherein the step of attaching the heat sink to the semiconductor wafers 24 1321836 further comprises forming a plurality of adhesive layers on the semiconductor wafers. on. 27. The method of fabricating a semiconductor wafer package structure according to claim 21, wherein the central portion of the upper surface of the heat dissipating member is further provided with a plurality of heat dissipating fins. 25