1320939 九、發明說明： : 【發明所屬技術領域】 本發明係有關一種鍵盤，尤指一種可消除鬼鍵之鍵盤。 【先前技術】 鍵盤係被當作輸入訊號與電腦溝通的重要工具之_，而爷如何_叶鍵 盤内與電腦減對之祕即為_鍵盤品質賴鍵1見鋪陳於按二之 電路大多遵循標準的鍵盤協定，鍵盤協定是串列的且鍵盤除了组合按鍵 (Shift、Ctrl、Alt)之外的每個按鍵都分別對應特定的編碼；請參閱"『第工 圖』所示，此鍵盤内部電路係以一微處理器100之複數平行及垂直I/c>線 111a、111b、112a、112b形成-矩p車110並連接有—主準位電阻則，該矩 陣110交錯出複數按鍵120a、120b、120c、120d，當按下—按鍵12〇a的 時候’鍵S即發送此按鍵12〇a所代表的編碼至電腦判讀；當將按下的案鍵 120a回復原狀態時，鍵盤即會發送鬆手的編碼，如此的一次性之往覆作動 在測試鍵盤時會注意到該類利用既定矩陣11〇排列電路所製成之鍵 盤，即使已確定鍵盤之所有元件及配電皆為完好的狀態下，仍會產生一種 衝突現象，該触現紐生在當使用者按τ—按鍵12Qa後，再按下另一按 鍵120b，系統僅會發送後者之信號而不是將二按鍵之信號同時發送，這是 φ 因為彼此鍵盤碼是互斥的，前者的信號會被覆蓋而不會被恢復。 另一個現象，當使用者同時按下鍵盤電路之矩陣11〇矩形角上二個按 鍵120a、120b，再按下按鍵120c(或圆），會造成微處理器1〇〇無法正確 判斷出按壓的按鍵120c(或I20d)信號，該現象稱之為鬼鍵；該問題對於按 壓鍵盤快速的使用者將會有遺失字元的缺失產生；又，對於使用鍵盤之電 腦遊戲玩豕而言，往往須同時按壓複數個按鍵以產生複合鍵訊號，用來施 行不同的職攻略手段，而難產生驗的躲，必會造姐家無法順利 進行遊戲的困擾。 為了防止使用者按下無法顯示有效訊號之鬼鍵卻不自知的問題，中華 民國專利公告第_86661號『以多維電極定義按鍵之輸入裝置及其編碼 方法』係提供一種能夠檢查鬼鍵(亦稱為幽靈鍵)是否被按下，並回傳錯誤 W〇939 訊息之專利。其以多維電極定義按鍵之輸入裝置及其編碼方法，其中係以 N維電極定義輸入裝置的每個按鍵，N為大於2的整數。根據本發明之掃 描按鍵之方法係逐一掃描每一維電極並且記錄其位置資料進行比對，進而 找出被按下之按鍵。 另請參閱中華民國專利公告第00578088號『具有布雷爾輸入功能之 鍵輸入裝置』，此專利揭示一種避免產生幽靈鍵之簡易鍵盤，其配置簡易 的鍵輸入功能和布雷爾輸入功能。鍵盤包含以鍵矩陣形式的鍵輸入電路。 在鍵矩陣巾’鍵盤上沒有兩個被指定為布雷_人功能鍵的預定鍵開關連 接在一條掃描線上。此鍵入裝置在使用布雷爾輸入功能時，在指定以完成1320939 IX. Description of the Invention: [Technical Field] The present invention relates to a keyboard, and more particularly to a keyboard capable of eliminating ghost keys. [Prior Art] The keyboard system is regarded as an important tool for communication between the input signal and the computer, and how the master is _ leaf keyboard and the computer to reduce the secret is _ keyboard quality Lai key 1 see shop in the second circuit mostly follow The standard keyboard protocol, the keyboard protocol is serial and each key of the keyboard except the combination buttons (Shift, Ctrl, Alt) corresponds to a specific code; see the "Figure", this keyboard The internal circuit is formed by a plurality of parallel and vertical I/c> lines 111a, 111b, 112a, 112b of a microprocessor 100, and is connected to a main level resistor 110. The matrix 110 is interleaved with a plurality of keys 120a. , 120b, 120c, 120d, when the - button 12〇a is pressed, the 'key S sends the code represented by the button 12〇a to the computer for interpretation; when the pressed button 120a is returned to the original state, the keyboard is Will send the code of the loose hand, such a one-time action will notice the keyboard made by the circuit of the predetermined matrix 11〇 when testing the keyboard, even if it is determined that all components and power distribution of the keyboard are in perfect condition. Next, still There is a conflict phenomenon. When the user presses τ-key 12Qa and then presses another button 120b, the system will only send the latter signal instead of sending the signals of the two buttons simultaneously. This is φ because The keyboard codes of each other are mutually exclusive, and the former signal will be overwritten without being restored. Another phenomenon, when the user simultaneously presses the two keys 120a, 120b on the rectangular corner of the matrix circuit 11 of the keyboard circuit, and then presses the button 120c (or circle), the microprocessor 1〇〇 cannot correctly determine the pressing. Button 120c (or I20d) signal, this phenomenon is called ghost key; this problem will be caused by the loss of missing characters for the user who presses the keyboard quickly; also, for the computer game playing with the keyboard, it is often necessary At the same time, pressing a plurality of buttons to generate a composite key signal is used to implement different job strategies, and it is difficult to create a hidden game, which will certainly make the sister's home unable to smoothly carry out the game. In order to prevent the user from pressing a ghost key that cannot display a valid signal but does not know it, the Republic of China Patent Publication No. _86661 "Input device for multi-dimensional electrode definition button and its encoding method" provides an ability to check ghost keys ( Also known as the ghost key) is pressed and returns the patent of the W.939 message. The multi-dimensional electrode defines a button input device and an encoding method thereof, wherein each button of the input device is defined by an N-dimensional electrode, and N is an integer greater than 2. The method of scanning a button according to the present invention scans each dimension electrode one by one and records its position data for comparison, thereby finding the pressed button. See also the Republic of China Patent Bulletin No. 00578088, "Key Input Device with Blair Input Function", which discloses a simple keyboard that avoids the generation of ghost keys, with a simple key input function and a Blair input function. The keyboard contains a key input circuit in the form of a key matrix. There are no two predetermined key switches on the keyboard matrix' keyboard that are designated as Bray_person function keys connected to a scan line. This typing device is specified to complete when using the Blair input function
布雷爾輸人功能的六鍵同時操作時之六點式輸人系統_，不會在任何^ 鍵開關上產生幽靈鍵。 曰 【發明内容】 生。的，在於解決上述之缺失，以避免遺失字元的狀況產 i写it ΐ 種可齡鬼鍵之鍵盤，該鍵盤内部電_以一微處 之屮線:誠一鍵盤掃描矩陣，該鍵娜矩陣上以二細線 之乂錯點疋義出複數訊號·，且於該微處理器電性連接有— 阻’並連接有-參轉位電絲欺該些喊開卿通狀態。 各訊號開關更電性連接有至少一與 之副準位電阻，且相鄰平扞Ι/Ω始μ丰位電阻為串聯電性連接狀態 況。 於°玄參考準位電位，進而能免除鬼鍵發生的狀 該垂=平電倾測法或高電位侧法就上述狀況判定 象發生。 之—沒破接通的訊號開關，以有效防止鬼鍵現 【實施方式】 本發明係為—射消除4鍵之鍵盤 有關本發明之詳細說明及技術内 1320939 容’現就配合圖式說明如下： … 請參閱『第2圖』所示，此為本發明之電路示意圖，如圖所示：俩 盤内部電路係以一微處理器測之複數平行1/0線211a、2ub及垂直;/〇 線212a、212b形成一鍵盤掃描矩陣2丨〇，該鍵盤掃描矩陣21〇上以 I/O線211a'211b及垂直I/O線212a、212b之交錯點定義出複數訊號開S 220a、220b ' 220c、220d ’且於該微處理器200電性連接有一主準位電阻 幻，並連接有-參轉位電位Vrcf來判定該些訊號開關22Ga、22此、22〇c、 220d導通狀態。 各訊賴關22Ga、22Gb、22Ge、2施紐連财至少—能主準位電 φ 阻R1為串聯電性連接狀態之副準位電阻把，該相鄰平行I/O線211a、211b .上之副準位電阻R2為並聯狀態。其中，該串聯電性連接狀態可細分為三 種狀態：其一，可於該些訊號開關220a、22〇b、22〇c、22〇d導通點前端連 接有一與該主準位電阻R1為串聯電性連接狀態之副準位電阻^(如『第2 圖』所示）；其二，可於該些訊號開關220a、220b、220c、220d導通點後 端連接有一與該主準位電阻R1為串聯電性連接狀態之副準位電阻Μ (如 『第3圖』所示）；其三，可於該些訊號開關22〇a、22%、22此、22〇d導 通點則端及後端各連接有一與該主準位電阻R1為串聯電性連接狀態之副 準位電阻R2、R3(如『第4圖』所示）。俾當使用者按壓該鍵盤垂直1/〇線 φ 212a、212b及平行I/O線2lla、211b所交錯形成四訊號開關22〇a、22〇b、 220c、220d中之任意三訊號開關220a、220b、220c，以產生複合鍵訊號時， 因主準位電阻R1及副準位電阻R2、R3之連接狀態形成新準位電阻，且 該新準位電阻與流通至該鍵盤掃描矩陣210之電流計算後所得之電位值小 於該參考準位電位Vref，所以能免除鬼鍵發生的狀況。 此外，該微處理器200可以低電位偵測法或高電位偵測法判定該些訊 號開關22〇a、220b、22〇c、220d導通狀態··當微處理器200以低電位偵測 法债測平行I/O線211a、211b之電位值時，在訊號開關220a為ON的狀態， R1及R2分壓必須使平行I/O線2lla、211b電位低於該參考準位電位 Vref，如此微處理器2〇〇就會偵測到訊號開關22〇a為〇N的狀態，反之， 平行I/O線211a、211b電位高於該參考準位電位Vref，則偵測訊號開關220a 7 1320939 為OFF狀態，當祕處理^§ 200之债測法為高電位偵測法時，在訊號開關 220a為ON的狀態，R1及R2分壓必須使平行1/〇線2Ua、2ub電位高於 „亥參考準位電位Vref ’如此微處理器2〇〇就會偵測到訊號開關22〇a為〇N 的狀態’反之，則偵測訊號開關22〇a為OFF狀態。 針對上述狀況判定該垂直I/O線212a、212b及平行1/〇線2Ua ' 2nb 上其一沒被接通的訊號開關220d，在該微處理器200為低電位偵測法時， 主準位電阻R1與副準位f阻R2、R3分壓電路，需使得在掃減訊號開關 22〇d時判斷該平行I/O線2Ub之電位值高於該微處理器2〇〇之參考準位電 位，此時偵測得該訊號開關22〇d為〇FF狀態。又，在該微處理器2〇〇 為高電位積測法時’主準位電阻g與副準位電阻Μ、R3分壓電路需 使得在掃減碱開關時顺平行1/〇線」lb之電減低於該微處理 器2〇〇之參考準位電位Vref，此時偵測得該訊號開_施為〇ff狀態如 此二方法可有效防止鬼鍵現象的發生。 ~综上所述僅為本發明的較佳實施例而已，並非用來限定本發明之實施 範圍。即凡依本發财請專利範圍之内容所為的等效變化與修飾 ，皆應為 本發明之技術範。 1320939 【圖式簡單說明】The six-point input system of the four-button operation of the Blair input function does not generate a ghost key on any of the ^ key switches.曰 【Contents】 Health. In order to solve the above-mentioned shortcomings, in order to avoid the situation of missing characters, i write it. The keyboard of the age-old ghost key, the keyboard internal electricity _ with a slight line: Chengyi keyboard scanning matrix, the key matrix On the second line, the wrong signal is used to make a complex signal, and the microprocessor is electrically connected with a - resistance 'and connected with - the index bit wire to deceive the state. Each of the signal switches is electrically connected to at least one of the sub-level resistances, and the adjacent flat/Ω initial μ-bump resistance is in a series electrical connection state. In the ° Xuan reference level potential, in order to avoid the occurrence of ghost keys, the vertical = flat electric tilt method or high potential side method to determine the above situation. The signal switch is not broken to effectively prevent the ghost key. [Embodiment] The present invention is a keyboard for eliminating the 4 key. The detailed description of the present invention and the technique 1320939 are described as follows: : ... Please refer to the "Figure 2", which is a schematic circuit diagram of the present invention, as shown in the figure: the internal circuit of the two disks is measured by a microprocessor parallel to the parallel 1/0 line 211a, 2ub and vertical; The squall lines 212a, 212b form a keyboard scanning matrix 2A, and the complex scanning signals S 220a, 220b are defined by the interlaced points of the I/O lines 211a' 211b and the vertical I/O lines 212a, 212b on the keyboard scanning matrix 21 '220c, 220d' and the microprocessor 200 is electrically connected to have a main level resistance illusion, and is connected with a -index potential Vrcf to determine the on state of the signal switches 22Ga, 22, 22〇c, 220d. Each of the Xieguan 22Ga, 22Gb, 22Ge, 2 Shinu Liancai at least - the main level of the electric resistance φ R1 is the sub-level resistance of the series electrical connection state, the adjacent parallel I / O lines 211a, 211b. The upper sub-level resistance R2 is in a parallel state. The series electrical connection state can be subdivided into three states: one of them can be connected in series with the main level resistor R1 at the front end of the signal switch 220a, 22〇b, 22〇c, 22〇d. a sub-level resistance ^ of the electrical connection state (as shown in FIG. 2); and second, a connection with the main level resistor R1 may be connected to the back end of the signal switch 220a, 220b, 220c, 220d. The sub-level resistance Μ of the series electrical connection state (as shown in Fig. 3); the third, the signal switch 22〇a, 22%, 22, 22〇d conduction point and Each of the rear ends is connected with a sub-level resistance R2, R3 (shown in FIG. 4) which is electrically connected in series with the main level resistor R1. When the user presses the keyboard vertical 1/〇 line φ 212a, 212b and the parallel I/O lines 2lla, 211b, any three signal switches 220a of the four signal switches 22〇a, 22〇b, 220c, 220d are interleaved, 220b, 220c, in order to generate a composite key signal, a new level resistor is formed due to the connection state of the main level resistor R1 and the sub-level resistors R2, R3, and the new level resistor and the current flowing to the keyboard scanning matrix 210 The potential value obtained after the calculation is smaller than the reference level potential Vref, so that the occurrence of the ghost key can be eliminated. In addition, the microprocessor 200 can determine the on state of the signal switches 22A, 220b, 22〇c, 220d by the low potential detection method or the high potential detection method. When the potential values of the parallel I/O lines 211a and 211b are measured, when the signal switch 220a is turned on, the voltage division of R1 and R2 must make the potential of the parallel I/O lines 2lla and 211b lower than the reference level potential Vref. The microprocessor 2 detects the state of the signal switch 22〇a being 〇N. On the contrary, if the potential of the parallel I/O lines 211a and 211b is higher than the reference level potential Vref, the detection signal switch 220a 7 1320939 In the OFF state, when the debt measurement method of the secret processing method is the high potential detection method, when the signal switch 220a is ON, the voltage division of R1 and R2 must make the parallel 1/〇 line 2Ua, 2ub potential higher than „ The reference level potential Vref ' of the reference level is such that the microprocessor 2 detects the state of the signal switch 22〇a being 〇N. Otherwise, the detection signal switch 22〇a is in the OFF state. The vertical is determined for the above situation. The signal switch 220d on the I/O lines 212a, 212b and the parallel 1/〇 line 2Ua ' 2nb is not turned on, at the micro point When the processor 200 is in the low potential detection method, the main level resistor R1 and the sub level level f are blocked by the R2 and R3 voltage dividing circuits, so that the parallel I/O line 2Ub is determined when the signal switch 22〇d is swept down. The potential value is higher than the reference level potential of the microprocessor 2, and the signal switch 22〇d is detected as the 〇FF state. In addition, when the microprocessor 2 is in the high potential integration method 'The main level resistance g and the sub-level resistance Μ, R3 voltage dividing circuit should be such that the parallel parallel 1/〇 line lb is reduced to the reference level potential of the microprocessor 2〇〇 when sweeping the alkali switch Vref, at this time, the signal is detected to be turned on. The second method can effectively prevent the ghost key phenomenon from occurring. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. That is, the equivalent changes and modifications of the contents of the patent scope of the present invention should be the technical scope of the present invention. 1320939 [Simple description of the map]
第1圖，係習知之電路示意圖 第2圖，係本發明之電路實施例示意圖 第3圖，係本發明之另一電路實施例示意圖 第4圖，係本發明之另一電路實施例示意圖 【主要元件符號說明】 100.............微處理器 110.............矩陣 111a、111b..........平行 I/O 線 112a、112b..........垂直 I/O 線 120a、120b、120c、120d · · . ·按鍵 •微處理器 •鍵盤掃描矩陣 .平行I/O線 .垂直I/O線 •訊號開關 主準位電阻 副準位電阻 副準位電阻 參考準位電位 200 ............ 210............ 211a、211b......... 212a、212b......... 220a ' 220b ' 220c > 220d · · · R1 · R2 · R3 . VrefFIG. 1 is a schematic diagram of a circuit diagram of a second embodiment of the present invention. FIG. 3 is a schematic diagram of another embodiment of the circuit of the present invention. FIG. 4 is a schematic diagram of another circuit embodiment of the present invention. Explanation of main component symbols] 100.............Microprocessor 110.............Matrix 111a, 111b.......... Parallel I/O lines 112a, 112b..........Vertical I/O lines 120a, 120b, 120c, 120d · · · Buttons • Microprocessors • Keyboard scan matrix. Parallel I/O lines. Vertical I/O line • Signal switch main level resistance sub-level resistance sub-level resistance reference level potential 200 ............ 210............ 211a, 211b......... 212a, 212b......... 220a '220b ' 220c > 220d · · · R1 · R2 · R3 . Vref