ΓΙΟ ‘年月‘ ‘Year
1317165 九、發明說明： 【發明所屬之技術領域】 本發明關於一種半導體封裝，尤指一種用於光學應 用之晶片封裝及晶片封裝方法。 【先前技術】 半導體晶片有輸入與輸出電片與外部電路連接以形 成電子系統的一部分。連接媒介通常是金屬導線陣列或 支援電路，或是直接與電路面板連接亦可。數種連接技 術已被廣泛使用。同時，晶片尺寸封裝（CSP)儼然成為 一普遍使用之記憶晶片封裝技術，如靜態隨機存取記憶 體（SRAM)、動態隨機存取記憶體（DRAM)、快閃記憶體以 及其他低接腳數晶片。晶片尺寸封裝（CSP)幾乎不會比 晶片本身來的大。然而，進階邏輯晶片，如微處理機、 數位訊號處理器（DSP)以及特殊應用積體電路（ASIC) 時常需要封裝遠大於晶片，以容納高接腳數及主機板間 距之限制。 此外，隨著較小尺寸的更高1C運作速度需求增加， 將愈多功能整合於單一晶片已蔚為風潮，如系統晶片 (S0C)，或是，將數種不同功能之晶片整合到單一封裝 内，如系統級封裝（SIP)。然而，在整合類比、記憶， 與邏輯功能於單一晶片時，仍有一些整合上的課題尚未 解決。一多晶片堆疊封裝因此揭露。 6 1317165 ,9&~67'(Γ5 平月日修(教正替換頁 請參照圖1 (Α)至1 (Ε)。根據習知技藝，圖1 (Α) 至1 (Ε)說明相機的多晶片模組封裴方法。首先，基板 11裝置如圖1 (Α)所示。第一封装12置於基板心， 如球開陣列封裝（BGA)的數位訊號處理器（DSp);複數 個SMT被動裝置13也置於基板u的同一表面，如圖i (B)所示。此外，成像晶片14黏附於基板丨丨的同一表 面。其中，成像晶片14藉打線接合而具傳導性，如圖1 (c)所示。在封裝成像晶片14與複數個SMT被動裝置 13,以製成第二封裝15後，如圖！（D)所示，鏡頭模組 16更進一步置於第二封裝15上。而撓性電路板17則與 基板11焊接以製成相機’如圖1 (E)所示。 一 如眾所知，有鑒於透過密集陣列封裝以散熱之多方 應用，封裝技術持續日益微小化。然而，習知技藝揭露 置於基板同一表面之兩個晶片封裝的多晶片模組。為達 成微丨、化之目的，應有效利用基板11。若複數個不同封 裝之晶片應佔據基板11的整個表面，則基板的整個表面 應減少。因此，留給複數個被動裝置及晶片的剩餘基板 11表面則變得有限，對於微小化是很不利的。因此，多 晶片模組與複數個封裝間的相容性應被納入考量。本文 所揭露之發明滿足此需求。 雖然晶片封裝用於光學應用在技術上是可行的，但 實際上執行上是有其困難性。上述論及的封裝儘管執行 7 .1317165 p'MT'Ts^''-------—ί I年月日修(於)正替換頁 - ____ . · ...··，.吟 表現良好，但是不利於微小化時使用整個表面。再者， 由於封裝的而價原料與人玉成本’使得封裝過於昂貴並 限制成本削減的努力。現今最亟需的是一簡單的封裝方 法，且有低成本、容易組裝與可靠等優點。因此，本發 明人提出用於光學應用之晶片封農及晶片封裝方法，ς .置於基板的上下兩表面’以有效利用封褒空間並 促，微小化，不僅改正了習知技藝的缺點也解決了 rwi 占自 λ L發明内容】 有馨於f知技藝受制於上述之_，本發明的目的1317165 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package, and more particularly to a chip package and a chip package method for optical applications. [Prior Art] A semiconductor wafer has input and output chips connected to an external circuit to form a part of an electronic system. The connection medium is usually a metal wire array or a support circuit, or it can be directly connected to the circuit panel. Several connection technologies have been widely used. At the same time, the chip size package (CSP) has become a commonly used memory chip packaging technology, such as static random access memory (SRAM), dynamic random access memory (DRAM), flash memory and other low pin counts. Wafer. The chip size package (CSP) is hardly larger than the wafer itself. However, advanced logic chips, such as microprocessors, digital signal processors (DSPs), and special application integrated circuits (ASICs), often require packages that are much larger than the chip to accommodate the high pin count and board spacing limitations. In addition, with the increased demand for higher 1C operating speeds of smaller sizes, the more versatile integration into a single chip has become a trend, such as system silicon (S0C), or the integration of several different functional chips into a single package. Inside, such as system level packaging (SIP). However, there are still some integration issues that remain unresolved when integrating analog, memory, and logic functions on a single die. A multi-wafer stack package is thus disclosed. 6 1317165 , 9 &~67' (Γ5 平月日修 (Teaching the replacement page, please refer to Figure 1 (Α) to 1 (Ε). According to the skill, Figure 1 (Α) to 1 (Ε) explains the camera Multi-chip module sealing method. First, the substrate 11 device is shown in Figure 1 (Α). The first package 12 is placed in the substrate core, such as a ball-on-array package (BGA) digital signal processor (DSp); The SMT passive device 13 is also placed on the same surface of the substrate u as shown in Figure i (B). Further, the imaging wafer 14 is adhered to the same surface of the substrate 。. The imaging wafer 14 is conductive by wire bonding, such as Figure 1 (c) shows the lens module 16 further placed in the second package after the imaging wafer 14 and the plurality of SMT passive devices 13 are packaged to form the second package 15 as shown in Fig. (D). 15 and the flexible circuit board 17 is soldered to the substrate 11 to form a camera as shown in Fig. 1(E). As is known, packaging technology continues to be increasingly in view of the application of heat dissipation through dense array packages. Miniaturization. However, the prior art discloses a multi-wafer module of two wafer packages placed on the same surface of the substrate. The purpose is to effectively utilize the substrate 11. If a plurality of differently packaged wafers should occupy the entire surface of the substrate 11, the entire surface of the substrate should be reduced. Therefore, the surface of the remaining substrate 11 remaining for a plurality of passive devices and wafers becomes limited. Therefore, the miniaturization is very disadvantageous. Therefore, the compatibility between the multi-chip module and the plurality of packages should be taken into account. The invention disclosed herein satisfies this requirement. Although the chip package is technically feasible for optical applications. However, in practice, there are difficulties in its implementation. The above mentioned package is being replaced despite the implementation of 7.1317165 p'MT'Ts^''--------ί I Page - ____ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What is most needed today is a simple packaging method, which has the advantages of low cost, easy assembly, and reliability. Therefore, the inventors have proposed a wafer sealing method and a wafer packaging method for optical applications, and placed on a substrate. The lower two surfaces 'effectively utilize the sealing space and promote and miniaturize, which not only corrects the shortcomings of the conventional techniques but also solves the rwi occupies the content of the λ L invention. The invention is subject to the above-mentioned _, the invention purpose
St 一種用於光學應用之晶片封裝方法，將兩封裝 =基板:上下兩表面，以有效利用封裝空間並促進微 不僅改正了習知技藝的缺點也解決了上述問題。 為達上述目的，本發明之—較 -種用於光學應用之晶片封裝方法，包含以;;，供 ::;:r表*及第二表面之基板二複數個:上 被動裝置與基板第一表面接合· 板第一表面’· d)於吴祐笛Λ 第一晶片黏附於基 哕伴嗲罩孫a # +/土 表面的上方形成一保護罩， 該保4罩料覆蓋魏㈣—被皁 將複數個第二被動裝置與基板第二表面接t ;以） 基板的第二表面;g)提供一蓋座第： 曰具她，而該框架有開口窗與複數個與基板第二表 8 1317165 掌.为〇1修(¾正替換頁: 面連接的支柱；h)將蓋座組合疊於複數個第二被動裝置 與第二晶片上，因此在框架與第二表面邊緣間形成複數 個間隙；i)將填料填入複數個間隙以密封蓋座組合中複 數個第二被動裝置與第二晶片，以獲得一整個密封封裝。 根據本發明之構想，基板包含陶瓷基板與印刷電路 板。 根據本發明之構想，第一晶片與第二晶片利用打線 方式與基板接合。 根據本發明之構想，藉由表面貼裝技術（SMT)執行步 驟b)與步驟e)。 根據本發明之構想，複數個支柱置於框架角落。 根據本發明之構想，填料是由環氧樹脂製成。 根據本發明之構想，蓋座組合更包含置於開口窗的 玻璃片。 根據本發明之構想，第一晶片是數位訊號處理器 (DSP)。 根據本發明之構想’第二晶片是成像晶片。 為達上述目的，本發明另一較廣義實施樣態為提供 用於光學應用之晶片封裝，包含具有第一表面及第二表 面之基板；置於基板第一表面的第一晶片與複數個第一 被動裝置；置於基板第一表面上方的保護罩，用以覆蓋複 數個第一被動裝置與第一晶片；置於第二表面上的第二 晶片與複數個第二被動裝置；蓋座組合，該組合具有框 9 1317165 i)8. 6. ϋ 5 午月曰修廣,)正替換頁 架，該框架有開口窗與複數個支柱，其中，複數個支柱 與基板第二表面邊緣連接使得基板邊緣形成複數個間隙； 置於開口窗之玻璃片用以覆蓋基板；填入基板邊緣的複 數個間隙之填料，以獲得一整個密封封裝。 根據本發明之構想，基板包含陶瓷基板與印刷電路 板。 根據本發明之構想，第一晶片與第二晶片利用打線 方式與基板接合。 根據本發明之構想，以表面貼裝技術將複數個第一 被動裝置及第二被動裝置安置於基板。 根據本發明之構想，填料是由環氧樹脂製成。 根據本發明之構想，複數個支柱置於蓋座組合的角 落。 根據本發明之構想，第一晶片是數位訊號處理器 (DSP)。 根據本發明之構想*第二晶片為成像晶片。 【實施方式】 體現本發明特徵與優點的一些典型實施例將 在後段的說明中詳細敘述。應理解的是本發明能夠 在不同的態樣上具有各種的變化，其皆不脫離本發 明的範圍，且其中的說明及圖式在本質上當作說明 之用，而非用以限制本發明。 圖2(Α)-2(Κ)為依據本發明之用於光學應用之晶 1317165 t 〇i修(®正替換頁 片封裝方法。如圖2(A)-2(Κ)所示，用於光學應用之 晶片封裝方法包含下列步驟：a)提供具有第一表面211 與第二表面212的基板21，如圖2(A);b)將複數個第 一被動裝置22與基板21的第一表面211接合，如圖 2(B); c)將第一晶片23黏附於基板21的第一表面211， 如圖2(C); d)於基板21的第一表面211上方形成保護 罩24，以覆蓋複數個第一被動裝置22與第一晶片23， 如圖2(D); e)將複數個第二被動裝置25與基板21的 第二表面212接合，如圖2(E); f)將第二晶片26黏附 於基板21之第二表面212 ; g)提供蓋座組合27，該 組合具有框架271，該框架有開口窗272與複數個與基板 21的第二表面212連接的支柱273，如圖2(F)，其中， 複數個支柱273裝置於框架271的角落，蓋座組合27 更包含置於開口窗272的玻璃片274，以製成蓋座組合 27; h)將蓋座組合27疊於複數個第二被動裝置25與第 二晶片26上，如圖2(H)(合併圖2(F)與圖2(G)的結 構），使得框架271與基板21的第二表面212邊緣間形 成複數個間隙275; i)將填料28填入複數個間隙275 以密封在蓋座組合27中的複數個第二被動裝置25與第 二晶片26，以獲得一整個密封封裝，如圖2(1)。 實際上，晶片封裝方法可用來製作相機的光學應 用。獲得一整個密封封裝後，如圖2(1)，晶片封裝方法 更包含以下步驟：j)將撓性電路板29焊接於基板21; k) 11St A chip packaging method for optical applications that solves the above problems by using two packages = substrate: upper and lower surfaces to effectively utilize the package space and promote micro--not only correcting the shortcomings of the prior art. In order to achieve the above object, the present invention relates to a wafer packaging method for optical applications, comprising:;, for:::r table* and a substrate of a second surface: a plurality of upper passive devices and substrates A surface joint · the first surface of the plate '· d) in Wu Youdi Λ The first wafer is adhered to the top of the surface of the base 哕 嗲 a sun a # + / soil to form a protective cover, the cover 4 cover Wei (four) - quilt Connecting a plurality of second passive devices to the second surface of the substrate; the second surface of the substrate; g) providing a cover seat: the cooker, and the frame having the open window and the plurality of substrates and the second table 8 1317165 掌. For 〇1 repair (3⁄4 positive replacement page: face-connected struts; h) stacking the cover seat on a plurality of second passive devices and the second wafer, thus forming a plurality of frames between the frame and the second surface edge The gap; i) filling the filler into a plurality of gaps to seal the plurality of second passive devices and the second wafer in the cover assembly to obtain an entire sealed package. In accordance with the teachings of the present invention, a substrate comprises a ceramic substrate and a printed circuit board. According to the concept of the present invention, the first wafer and the second wafer are bonded to the substrate by wire bonding. In accordance with the teachings of the present invention, step b) and step e) are performed by surface mount technology (SMT). In accordance with the teachings of the present invention, a plurality of struts are placed at the corners of the frame. According to the concept of the invention, the filler is made of epoxy resin. According to the concept of the invention, the cover assembly further comprises a glass sheet placed in the open window. In accordance with the teachings of the present invention, the first wafer is a digital signal processor (DSP). According to the concept of the invention, the second wafer is an imaging wafer. In order to achieve the above object, another broad aspect of the present invention provides a wafer package for optical applications, comprising: a substrate having a first surface and a second surface; and a first wafer and a plurality of layers disposed on the first surface of the substrate a passive device; a protective cover disposed above the first surface of the substrate for covering the plurality of first passive devices and the first wafer; a second wafer disposed on the second surface and the plurality of second passive devices; , the combination has a frame 9 1317165 i) 8. 6. ϋ 5 午月曰修,) is replacing the page frame, the frame has an opening window and a plurality of struts, wherein the plurality of struts are connected to the second surface edge of the substrate such that the substrate The edge forms a plurality of gaps; the glass sheet placed in the opening window is used to cover the substrate; and a plurality of gap fillers are filled in the edge of the substrate to obtain an entire sealed package. In accordance with the teachings of the present invention, a substrate comprises a ceramic substrate and a printed circuit board. According to the concept of the present invention, the first wafer and the second wafer are bonded to the substrate by wire bonding. In accordance with the teachings of the present invention, a plurality of first passive devices and second passive devices are disposed on a substrate by surface mount technology. According to the concept of the invention, the filler is made of epoxy resin. In accordance with the teachings of the present invention, a plurality of struts are placed in the corners of the cover assembly. In accordance with the teachings of the present invention, the first wafer is a digital signal processor (DSP). According to the concept of the invention * the second wafer is an imaging wafer. [Embodiment] Some exemplary embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It is to be understood that the invention is not limited by the scope of the invention. 2(Α)-2(Κ) is a crystal 1317165 t 〇i repair (® positive replacement sheet encapsulation method for optical applications according to the present invention. As shown in FIG. 2(A)-2(Κ), The wafer packaging method for optical applications comprises the steps of: a) providing a substrate 21 having a first surface 211 and a second surface 212, as shown in FIG. 2(A); b) a plurality of first passive devices 22 and a substrate 21 A surface 211 is bonded, as shown in FIG. 2(B); c) the first wafer 23 is adhered to the first surface 211 of the substrate 21, as shown in FIG. 2(C); d) a protective cover is formed over the first surface 211 of the substrate 21. 24, to cover a plurality of first passive devices 22 and the first wafer 23, as shown in Figure 2 (D); e) a plurality of second passive devices 25 and the second surface 212 of the substrate 21, as shown in Figure 2 (E) f) adhering the second wafer 26 to the second surface 212 of the substrate 21; g) providing a cover assembly 27 having a frame 271 having an opening window 272 coupled to a plurality of second surfaces 212 of the substrate 21. The struts 273, as shown in Fig. 2(F), wherein a plurality of struts 273 are disposed at the corners of the frame 271, and the cover assembly 27 further includes a glass piece 274 placed in the opening window 272 to form the cover assembly 27; will The cover assembly 27 is stacked on the plurality of second passive devices 25 and the second wafer 26, as shown in FIG. 2(H) (combining the structures of FIG. 2(F) and FIG. 2(G)), so that the frame 271 and the substrate 21 are A plurality of gaps 275 are formed between the edges of the second surface 212; i) filling the filler 28 into the plurality of gaps 275 to seal the plurality of second passive devices 25 and the second wafer 26 in the cover assembly 27 to obtain an entire seal Package, as shown in Figure 2 (1). In fact, the chip packaging method can be used to make optical applications for cameras. After obtaining a whole sealed package, as shown in FIG. 2(1), the chip packaging method further comprises the following steps: j) soldering the flexible circuit board 29 to the substrate 21; k) 11
1替換I 1317165 將鏡頭模組30置於整個密封封裝，以達到光學應用之目 的°第-晶片23與第二晶片26可透過打線方式接合於 基板21。另一方面，利用表面貼裝技術（SMT)將複數個第 一被動裝置22與複數個第二被動裝置25置於基板 21。根據本發明之構想，基板21最好是陶瓷基板與印刷 電路板。此外’填料28是由環氧樹脂製成。因此，本晶 片封裝方法將兩個封裴置於基板的上下兩表面，以有效 利用封裝空間並促進微小化。 根據上述方法，本發明亦揭露一晶片封裝，請參照 圖2(A)-2(K)°用於光學應用之晶片封裝包含：具有第一 表面211與第二表面212的基板21;置於第一表面 211上的複數個第一被動裝置22與第一晶片23;置於 基板21的第一表面211上方的保護罩24,用以覆蓋複 數個第一被動裳置22與第一晶片23;複數個第二被動 裝置25與一第二晶片26被置於第二表面212;蓋座組合 27具有框架271，該框架有開口窗272與複數個支柱 273 ’其中’複數個支柱273置於蓋座組合27的角落， 並與基板21的第二表面212的邊緣連接，在基板21邊 緣形，複數個間隙275;置於開口窗272的玻璃片274， 以覆蓋基板21 ;填入基板21邊緣的複數個間隙275的 填料28，以獲得一整個密封封裝。 相同地，基板21可以是陶瓷基板與印刷電路板。同 12 -1317165 正替換頁 時，第一晶片23與第二晶片26都以打線方式接合於基 板，且複數個第一被動裝置22與第二被動裝置25利用 表面貼裝技術（SMT)以置於基板。此外，填料28是由 環氧樹脂製成。由於晶片封裝可用來製成相機的光學應 用，晶片封裝更包含焊接於基板21的撓性電路板29,以 及置於整個密封封裝的鏡頭模組30，以達成光學應用之 目的。再者，第一晶片23可以是數位訊號處理器（DSP)， 而第二晶片26則為成像晶片。在本實施例中，晶片封裝 將兩封裝置於基板的上下兩表面，而不僅是如習知技藝 般佔據基板的一表面。因此，本發明之封裝能更密集有 效地利用封裝空間並促進微小化。 總而言之，本發明提出用於光學應用之晶片封裝及 晶片封裝方法，提出將兩封裝置於基板的上下兩表面， 以有效地利用封裝空間並促進微小化。顯然地，利用本 發明之構想能充分利用基板表面。而本發明的晶片封裝 更提出蓋座組合，該組合具有與環氧樹脂填料結合的四 個支柱，以促進微小化。但習知技藝並未揭露此。所以 本發明具有相當多的優點，可以有效克服習知技藝在實 際應用時的缺點。 縱使本發明已由上述之實施例詳細敘述而可 由熟悉本技藝之人士任施匠思而為諸般修飾，然皆 不脫如附申請專利範圍所欲保護者。 131 Replacement I 1317165 The lens module 30 is placed over the entire sealed package for optical purposes. The first wafer 23 and the second wafer 26 can be bonded to the substrate 21 by wire bonding. On the other hand, a plurality of first passive devices 22 and a plurality of second passive devices 25 are placed on the substrate 21 by surface mount technology (SMT). In accordance with the teachings of the present invention, substrate 21 is preferably a ceramic substrate and a printed circuit board. Further, the filler 28 is made of an epoxy resin. Therefore, the wafer encapsulation method places two packages on the upper and lower surfaces of the substrate to effectively utilize the package space and promote miniaturization. According to the above method, the present invention also discloses a chip package, please refer to FIG. 2(A)-2(K). The wafer package for optical application comprises: a substrate 21 having a first surface 211 and a second surface 212; a plurality of first passive devices 22 and a first wafer 23 on the first surface 211; a protective cover 24 disposed above the first surface 211 of the substrate 21 for covering the plurality of first passive skirts 22 and the first wafer 23 a plurality of second passive devices 25 and a second wafer 26 are placed on the second surface 212; the cover assembly 27 has a frame 271 having an opening window 272 and a plurality of struts 273 'where a plurality of struts 273 are placed The corner of the cover assembly 27 is connected to the edge of the second surface 212 of the substrate 21, at the edge of the substrate 21, a plurality of gaps 275; the glass sheet 274 placed in the opening window 272 to cover the substrate 21; and the substrate 21 is filled A plurality of gaps 275 of filler 28 are formed at the edges to obtain an entire sealed package. Similarly, the substrate 21 may be a ceramic substrate and a printed circuit board. When the page is replaced by 12-1317165, the first wafer 23 and the second wafer 26 are wire bonded to the substrate, and the plurality of first passive devices 22 and the second passive device 25 are disposed by surface mount technology (SMT). On the substrate. Further, the filler 28 is made of an epoxy resin. Since the chip package can be used to make an optical application for the camera, the chip package further includes a flexible circuit board 29 soldered to the substrate 21, and a lens module 30 placed over the entire sealed package for optical applications. Furthermore, the first wafer 23 can be a digital signal processor (DSP) and the second wafer 26 is an imaging wafer. In this embodiment, the wafer package places the two packages on the upper and lower surfaces of the substrate, not only occupying a surface of the substrate as is conventional in the art. Therefore, the package of the present invention can utilize the package space more densely and efficiently and promote miniaturization. In summary, the present invention proposes a wafer package and a wafer package method for optical applications, and proposes to place two packages on the upper and lower surfaces of the substrate to effectively utilize the package space and promote miniaturization. Obviously, the substrate surface can be fully utilized with the concept of the present invention. The wafer package of the present invention further proposes a cover assembly having four pillars combined with an epoxy resin filler to promote miniaturization. However, the prior art does not disclose this. Therefore, the present invention has considerable advantages and can effectively overcome the shortcomings of the prior art in practical applications. The present invention has been described in detail by the above-described embodiments, and may be modified by those skilled in the art, without departing from the scope of the appended claims. 13
多晶片模組方法之 l3l7l65 【圖式簡單說明】 圖UA)-l(E)為習知相機之封裝 不意圖。 圖2(A)-2(K)為依據本發明之用於光學應用之 封裝方法之示意圖 " 【主要元件符號說明】 11 基板 12 第一封裝 13 表面貼裝技術被動裝置 14 成像晶片 15 第二封裝 16 鏡頭模組 17 撓性電路板 21 基板 211第一表面 212第二表面 22 第一被動裝置 23 第一晶片 24 保護罩 25 第二被動裝置 26 第二晶片 27 蓋座組合 ,1317165 271 框架 272 開口窗 273 支柱 274 玻璃片 275. 間隙 28 填料 29 撓性電路板 30 鏡頭模組 "98. 6. 〇 F" 1 年月日修(E)正替換頁1Multi-chip module method l3l7l65 [Simple diagram of the diagram] Figure UA)-l (E) is the packaging of the conventional camera. 2(A)-2(K) are schematic views of a packaging method for optical applications according to the present invention" [Major component symbol description] 11 substrate 12 first package 13 surface mount technology passive device 14 imaging wafer 15 2 package 16 lens module 17 flexible circuit board 21 substrate 211 first surface 212 second surface 22 first passive device 23 first wafer 24 protective cover 25 second passive device 26 second wafer 27 cover combination, 1317165 271 frame 272 opening window 273 pillar 274 glass piece 275. gap 28 packing 29 flexible circuit board 30 lens module "98. 6. 〇F" 1 year and month (E) is replacing page 1