1317157 96-12-27 〇9252twf2.doc/d 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種元件隔離結構之製造方法，且特別是 有關於一種淺溝渠隔離結構(shallow trench isolation，簡稱 STI)之製造方法，以降低製造成本(cost)。 【先前技術】 在積體電路蓬勃發展的今日’元件縮小化與積集化是必然 之趨勢’也是各界積極發展的重要課題。當元件尺寸逐漸縮 小’積集度(integration)逐漸提高，元件間用以防止如漏電流 (current leakage)或受鄰近元件干擾(cross-talk)等情形發生的 隔離結構也必須縮小’因此元件隔離技術困難度也逐漸增高。 習知形成元件隔離結構的方法以區域氧化法（丨〇ca丨 oxidation ’簡稱LOCOS)為主，其製程係在半導體基底的非主 動區域(non-active region)中成長場氧化物(field 0Xjde)，以作 為兀件的隔離結構.然而，利用區域氧化法形成的場氧化物在 其邊緣會發生成長不完全(undergrowth)如鳥嘴(bird beak)的 氧化物，而難以縮小其尺寸。因此，局部氧化法之製程在積體 電路製造中的有效元件最大數量將被限制。而且，場氧化物也 會垂直延伸，而在主動與非主動區域間形成非平面地形 (=〇n-planart〇p〇graphy)。這個非平面地形將導致後續微影製 耘中的困難度，譬如影像的解析問題等。由於上述這些限制， 將使局部氧化法會無法應用於譬如〇_35微米以下的小元件尺 寸之半導體製程内。 ^有鑒於此，已有其他元件隔離方法持續被發展出來，其中 最廣泛應用的方法係淺溝渠隔離製程，尤其是將其應用於次半 1317157 09252twf2.doc/d 96-12-27 微米(Sub-halfM丨cron)的積體電路製程中。習知的淺 結構之製造方法是先於基底上形成墊氧化層（pad 〇χ丨de)與氮 化矽罩幕層’再利用非等向性乾蝕刻法(anis〇tr〇p丨c dry 於基底中姓刻出陡靖的溝渠。接著，再利用化學氣相沉積製程 (chemical vapor deposition ’簡稱CVD)於基底上形成」層絕 緣層’並填滿溝渠。隨後，利用化學機械研磨製程(chem^ mechanical P〇丨ish，簡稱CMP)去除罩幕層上多餘的絕緣層。 最後，去除氮化矽罩幕層與墊氧化層。 一因為淺溝渠隔離法在半導體基底上所需之面積很小，而使 兀件能更密集分布’所以其已成為超大積體電路的較佳隔離方 法。而較密集的分布能在電路製造上增進其速度與功率。淺溝 渠隔離結構也具有相當平的地形，可幫助後續微影製程並減少 失誤。 、然而，習知的淺溝渠隔離製程在利用化學氣相沉積製程形 成絕緣層之後，需要利用化學機械研磨製程去除罩幕層上的絕 緣層，因而導致大量的絕緣層被去除，造成無謂的浪費。另外， 亚且化學機械研磨製程所需消耗的研磨用的奈米級研磨粒 (nano-sized abrasive)數量極大。因此，於習知的淺溝渠隔離 結構之製造上需花費很多之成本。 〃 【發明内容】 、因此’本發明之目的是提供一種淺溝渠隔離結構之製造方 法’以省略習知製程中用來去除罩幕層上多餘的絕緣層之化學 機械研磨製程。 、本發明之另一目的是提供一種淺溝渠隔離結構之製造方 法，能夠不消耗大量用於化學機械研磨製程中的研磨粒。 本發明之再—目的是提供一種淺溝渠隔離結構之製造方 1317157 9642-27 09252twC.doc/d 法，可避免習知消耗大量絕緣層之缺點。 本發明之又一目的是提供一種淺溝渠隔離結構之製造方 法，以降低製造成本。 根據上述與其它目的’本發明提供一種淺溝渠隔離結構之 製造方法’包括於形成有一墊氧化層的一基底中形成一溝渠， 這些溝渠穿過墊氧化層。接著，利用電泳沉積製程 (electrophoresis deposition process，簡稱 EDP)於墊氧化層 以外的溝渠中形成一絕緣層。隨後，施行一燒結製程(Sjnter丨ng process) ’以增加絕緣層的密度。 其中，電泳沉積製程係一種利用電場將帶電荷的粒子沉積 於基底上的技術，而本發明利用電泳沉積製程形成薄膜的方法 包括在一電泳槽中加入懸浮液(SUSpensj〇n)，其中於懸浮液中 含有帶電荷的奈米級微粒（partjc|e)。然後，將一電極板 (electrode plate)與一相反電極板互相平行放置於懸浮液中。 ，著，把一個半導體基底放置於其中一個電極板上，且欲形 4膜的那一面需朝向另一電極板並暴露出來。隨後，於半 基底加-偏塵(bias) ’以於兩電極板之間產生電流，使 =微粒往放置基底的電極板移動，並沉積於基底上可導電二 本發明之優點係藉由電泳沉積製程進行絕緣 於電泳沉積製缺於兩電極板之間產 ^儿積他由 因此，帶i Γ 粒沉積於基底μ溝渠内。 二故磨層上的絕緣層； 中所消耗的研練， 1317157 09252twf2.doc/d 96-12-27 能大幅降低製造成本。 ^為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 【實施方式】 第1A圖至第ic圖是依照本發明一較佳實施例一種淺溝 渠隔離結構(shallow trench isolation，簡稱STI)之製作流程剖 面示意圖。 °月參照第1A圖，於一基底1〇〇上依序形成一塾氧化層 (padoxide) 102 與一罩幕層（mask 丨ayer)1〇4,其中基底 1〇〇 包括石夕基底；墊氧化層1Q2是絲保護基底免於遭受後 續製=的破壞的’其形成方式例如熱氧化法；而罩幕層104 的材貝例如是氮化矽、形成方式例如化學氣相沉積法。然後， 利用微影蝕刻技術，圖案化罩幕層104與墊氧化層102,以形 成數個預定形成溝渠的圖案。接著，以罩幕層104為钱刻罩 幕’對基底100進行蝕刻，以形成溝渠106。 接著，明參照第1B圖，施行一電泳沉積製程 (electrophoresis deposition process ’ 簡稱 EDp)，以便於溝 渠106中填入一層絕緣層1〇8，此絕緣層108的材質例如^ 二氧化矽(Si〇2)或是其他合適的介電材質。 疋 _而在參照第1C圖之前’先以第2圖為例，說明本發明在 施行電泳沉積製料的詳細情形，其中所形成的 材質例如是二氧化矽。 U〇 第2圖所示係根據第1Β圖十施行電泳沉積製程 意圖’請參照第2目，在一電泳槽咖中加入 (suSpensi〇n)202,而於懸浮液2〇2中含有純水與帶負^的卉 1317157 〇9252twf2.doc/d 96-12-27 米級(nano-sized):氧化石夕微粒(part|_de)2〇4，其中帶負電的 -氧化賴粒2G4譬如是研絲(abmsive)，且其平均粒徑可 以是26奈米；而此時的懸浮液2〇4之州值為4且其成= •導電率範_為1Q~8() ms/cm。然後，將-陽極板2〇6與一 陰極板208互相平行放入懸浮液202卜接著，把基底^j〇〇 放^於陽極板206上’或者於陽極板2Q6被置人懸浮液2〇2 之前’就先在陽極板206上放置基底100，並且無論基底1〇〇 是在陽極板206被放入懸浮液2〇2之前或之後放置的，其中 欲〒積形成薄膜的那-面需朝向陰極板2〇8暴露出來。然^， 於陽極板2〇6加-正偏壓(positjve bjas)，以於陽極板咖盥 陰極板208之間產生電流，其中在半導電基板側電極與相對/電 極間的所施加的電場強度範圍約為1〇〜1〇〇〇V/cm，以便使帶 ^電的二氧切微粒2Q4往陽極板挪方向移動(第2圖中= 箭號就是微粒204的移動方向），並沉積於基底1〇 溝渠106部位(請見第iB圖）。 、 之後，請參照第1C圖，施行一燒結製程㈤加㈣ process)’以緻密化絕緣層1〇8;也就是使絕緣層1〇8的密产 (density)在施行燒結製程後大於未施行燒結製程之前。其中， 可以根據絕緣層108的材質選取適當的燒結製程參數，以獲致 品質較佳的絕緣層1〇8a ,譬如當絕緣層1〇8的材質是二£化 矽時，其燒結溫度約小於攝氏1150度。 最後，於本實施例中，更包括將罩幕層1〇4與墊氧化芦 1〇2去除之步驟，其中當罩幕層1〇4的材質為氮化石夕時，移^ 罩幕層104的方法是使用熱碟酸溶液；而去除塾氧化層 的方法例如使用氫氟酸(HF) 0 θ 綜上所述，本發明之_在於_電泳沉賴軸行絕緣 •1317157 09252twC.doc/d 96-12-27 ^的沉積。由於電泳沉積製程是於兩電極板之間產生電流，使 帶電荷的微粒往其中一個電極板移動，藉以使微粒沉積於基底 上可導電的部位。因此，微粒會集中於矽基底内之溝渠，而不 會沉積在基底上屬於絕賴之罩幕層與純化層表面，故可省 略習知製程中用來去除罩幕層上的絕緣層的化學機械研磨製 程；也就是㉟’本發明可大幅減少化學機械研磨製程 ^ 粒，並且統習知消耗大量二氧切麟狀 而能夠降低製造成本。 ^ 1 ^ Ϊ本發明已以—較佳實施例揭露如上，然其並非用以限 何熟習此技藝者，在视離本發日狀精神和範圍 附之^專^^更Ϊ與潤飾’因此本發明之保護範圍當視後 附之申5月專利乾圍所界定者為準。 【圖式簡單說明】 丁人丨土X她例一種淺 乐I八圖至第…_疋佤照^ 渠隔離結構之製作流程剖面示意圖；以及 意圖 第2圖所讀根據第1Β圖中施行電枚積製程的製. 【主要元件符號說明】 100 .基底 102 :墊氧化層 104 :罩幕層 1〇6 :溝渠 108 ’ 1〇8a :絕緣層 20〇 :電泳槽 202 I懸浮液 204 :二氧化矽微粒 1317157 09252twf2.doc/d 96-12-27 206 :陽極板 208 :陰極板1317157 96-12-27 〇9252twf2.doc/d IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating an element isolation structure, and more particularly to a shallow trench isolation structure (shallow trench) The manufacturing method of isolation (STI) is referred to to reduce the manufacturing cost. [Prior Art] In today's boom in the development of integrated circuits, 'component downsizing and accumulating is an inevitable trend' is also an important issue for the active development of all walks of life. As component sizes shrink, 'integration gradually increases, and isolation structures between components to prevent situations such as current leakage or cross-talk must also shrink. 'So component isolation Technical difficulties have also gradually increased. Conventionally, a method of forming an element isolation structure is mainly a regional oxidation method (LOCOS), and a process is a field oxide (field 0Xjde) in a non-active region of a semiconductor substrate. As an isolation structure of the element. However, the field oxide formed by the area oxidation method may grow undergrowth such as an oxide of a bird beak, and it is difficult to reduce the size thereof. Therefore, the maximum number of effective components in the manufacturing process of the integrated circuit will be limited. Moreover, the field oxides also extend vertically, forming a non-planar topography between the active and inactive regions (=〇n-planart〇p〇graphy). This non-planar terrain will lead to difficulties in subsequent lithography, such as image resolution problems. Due to these limitations, local oxidation methods will not be applicable to semiconductor processes such as small component sizes below 〇35 microns. In view of this, other component isolation methods have been developed, and the most widely used method is the shallow trench isolation process, especially for the second half 1317157 09252twf2.doc/d 96-12-27 micron (Sub -halfM丨cron) In the integrated circuit process. The conventional shallow structure is manufactured by forming a pad oxide layer and a tantalum nitride mask layer on the substrate to reuse an anisotropic dry etching method (anis〇tr〇p丨c dry). A steep ditch is formed in the base of the substrate. Then, a chemical vapor deposition (CVD) is used to form a "layer insulating layer" on the substrate and fill the ditch. Subsequently, a chemical mechanical polishing process is utilized ( Chem^ mechanical P〇丨ish (CMP) removes the excess insulating layer on the mask layer. Finally, the tantalum nitride mask layer and the pad oxide layer are removed. The shallow trench isolation method requires a large area on the semiconductor substrate. Small, and the components can be more densely distributed' so it has become a better isolation method for ultra-large integrated circuits. The denser distribution can increase its speed and power in circuit manufacturing. The shallow trench isolation structure is also quite flat. Terrain can help the subsequent lithography process and reduce errors. However, the conventional shallow trench isolation process requires the use of a chemical mechanical polishing process to remove the hood after the chemical vapor deposition process is used to form the insulating layer. The insulating layer on the layer causes a large amount of insulating layer to be removed, resulting in unnecessary waste. In addition, the number of nano-sized abrasives used for polishing in the sub-chemical mechanical polishing process is extremely large. In the manufacture of the conventional shallow trench isolation structure, it takes a lot of cost. 〃 [Summary] Therefore, the object of the present invention is to provide a method for manufacturing a shallow trench isolation structure to omit the conventional process for removing A chemical mechanical polishing process for excess insulating layer on the mask layer. Another object of the present invention is to provide a method for manufacturing a shallow trench isolation structure that can consume a large amount of abrasive particles used in a chemical mechanical polishing process. Further, the object of the present invention is to provide a shallow trench isolation structure manufacturer 1317157 9642-27 09252twC.doc/d method, which can avoid the disadvantages of consuming a large number of insulating layers. Another object of the present invention is to provide a shallow trench isolation structure. Method to reduce manufacturing cost. According to the above and other purposes, the present invention provides a manufacturer of shallow trench isolation structures The method includes forming a trench in a substrate on which a pad oxide layer is formed, and the trenches pass through the pad oxide layer. Then, an electrophoresis deposition process (EDP) is used to form an insulating layer in the trench other than the pad oxide layer. Subsequently, a sintering process is performed to increase the density of the insulating layer. Among them, the electrophoretic deposition process is a technique of depositing charged particles on a substrate by using an electric field, and the present invention utilizes an electrophoretic deposition process. The method of forming a film comprises adding a suspension (SUSpensj〇n) in an electrophoresis tank, wherein the suspension contains charged nano-sized particles (partjc|e). Then, an electrode plate and an opposite electrode plate are placed in parallel with each other in the suspension. Then, a semiconductor substrate is placed on one of the electrode plates, and the side of the film to be formed is directed toward the other electrode plate and exposed. Subsequently, a semi-substrate is added-bias to generate a current between the two electrode plates, so that the particles are moved toward the electrode plate placed on the substrate, and deposited on the substrate to conduct electricity. The advantage of the invention is by electrophoresis. The deposition process is insulated by electrophoretic deposition and is missing between the two electrode plates. Therefore, the i-particles are deposited in the substrate μ-ditch. The insulation layer on the second wear layer; the training consumed in 1317157 09252twf2.doc/d 96-12-27 can greatly reduce the manufacturing cost. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The ic diagram is a schematic cross-sectional view showing a manufacturing process of a shallow trench isolation (STI) according to a preferred embodiment of the present invention. Referring to FIG. 1A, a pad oxide 102 and a mask 丨ayer 1〇4 are sequentially formed on a substrate 1 , wherein the substrate 1 includes a stone base; The oxide layer 1Q2 is a method of forming a wire protection substrate from subsequent destruction, such as thermal oxidation; and the material of the mask layer 104 is, for example, tantalum nitride, a formation method such as chemical vapor deposition. Then, the mask layer 104 and the pad oxide layer 102 are patterned by photolithography to form a plurality of patterns that are intended to form trenches. Next, the substrate 100 is etched with the mask layer 104 as a mask to form the trench 106. Next, referring to FIG. 1B, an electrophoresis deposition process (EDp) is performed to fill the trench 106 with an insulating layer 1〇8. The material of the insulating layer 108 is, for example, cerium oxide (Si〇). 2) Or other suitable dielectric materials. _ _ Before referring to FIG. 1C, the second embodiment is taken as an example to illustrate the details of the present invention in performing electrophoretic deposition, wherein the material formed is, for example, cerium oxide. U〇Fig. 2 shows the electrophoretic deposition process according to Fig. 10, 'Please refer to item 2, add (suSpensi〇n) 202 to an electrophoresis tank, and contain pure water in the suspension 2〇2. With the negative ^ ^ 1317157 〇 9252twf2.doc / d 96-12-27 nano-sized: oxidized stone particles (part | _de) 2 〇 4, which negatively charged - oxidized granules 2G4 譬Absive, and its average particle size can be 26 nm; at this time, the state of the suspension 2〇4 is 4 and its formation = • conductivity range _ is 1Q~8() ms/cm. Then, the anode plate 2〇6 and a cathode plate 208 are placed in parallel with each other in the suspension 202. Then, the substrate is placed on the anode plate 206 or the suspension is placed on the anode plate 2Q6. 2 Before 'the substrate 100 is placed on the anode plate 206 first, and the substrate 1 is placed before or after the anode plate 206 is placed in the suspension 2〇2, wherein the surface to be formed by the film is required to be accumulated. It is exposed toward the cathode plate 2〇8. Then, a positive bias (positjve bjas) is applied to the anode plate 2 to generate a current between the anode plate and the cathode plate 208, wherein the applied electric field between the side electrode of the semiconductive substrate and the opposite electrode The intensity range is about 1 〇~1 〇〇〇V/cm, so that the charged dioxo prior particles 2Q4 are moved toward the anode plate (Fig. 2 = arrow is the moving direction of the particles 204), and deposited At the base of the trench 1 (see Figure iB). Then, referring to FIG. 1C, a sintering process (5) plus (4) process) is performed to densify the insulating layer 1〇8; that is, the density of the insulating layer 1〇8 is greater than that of the non-execution after the sintering process is performed. Before the sintering process. Wherein, the appropriate sintering process parameters can be selected according to the material of the insulating layer 108 to obtain the insulating layer 1〇8a with better quality. For example, when the material of the insulating layer 1〇8 is £, the sintering temperature is about less than Celsius. 1150 degrees. Finally, in the embodiment, the step of removing the mask layer 1〇4 and the pad oxide ruthenium 1 2 is further included, wherein when the material of the mask layer 1〇4 is nitrided, the mask layer 104 is moved. The method is to use a hot-disc acid solution; and the method for removing the antimony oxide layer, for example, using hydrofluoric acid (HF) 0 θ. In summary, the present invention is based on the electrophoresis of the axis of insulation. 1317157 09252twC.doc/d 96-12-27 ^ deposition. Since the electrophoretic deposition process generates a current between the two electrode plates, the charged particles are moved toward one of the electrode plates, thereby depositing the particles on the conductive portion of the substrate. Therefore, the particles will be concentrated in the trenches in the crucible substrate, and will not deposit on the substrate and belong to the surface of the mask layer and the purification layer. Therefore, the chemistry for removing the insulating layer on the mask layer in the conventional process can be omitted. The mechanical polishing process; that is, 35', the invention can greatly reduce the chemical mechanical polishing process, and it is known that a large amount of dioxin is consumed and the manufacturing cost can be reduced. The invention has been disclosed above in the preferred embodiment, but it is not intended to limit the skill and scope of the present invention. The scope of protection of the present invention is subject to the definition of the patent application in May. [Simple description of the schema] Ding people 丨 soil X her example of a light music I eight figure to the first ... _ 疋佤 ^ ^ channel isolation structure of the production process profile; and the intention of the second figure read according to the first Β diagram [Production of main component symbol] 100. Substrate 102: pad oxide layer 104: mask layer 1〇6: trench 108' 1〇8a: insulating layer 20〇: electrophoresis tank 202 I suspension 204: two Cerium oxide particles 1317157 09252twf2.doc/d 96-12-27 206 : anode plate 208: cathode plate
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