TWI313065B - Thin film transistor array substrate and method of fabricating the same - Google Patents

Description

1313065 0610052ITW 19662twf.doc/006 IX. Description of the invention: • [Technical field of the invention] The present invention relates to a thin film transistor array substrate and a method for fabricating the same, and in particular to a method using a four-layer mask ( Four-photomask ) v* granulated thin film transistor array substrate and its fabrication method. [Prior Art] A thin film of a thin liquid crystal display (thin transist〇r liquid crystal dlspiay, TFT_LCD) is mainly composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer, wherein the thin film transistor array base is a plurality of thin film transistors arranged in an array pattern, and a pixel electrode corresponding to each of the thin film transistors, wherein the thin film transistor comprises a gate, a channel layer, and a secret layer The source, the crystal and the pixel electrode constitute a halogen structure. Among them, a thin film electric circuit is used as a switching element of a liquid crystal display unit. In the process of basin-specific film transistor, the more common one is the five-mask process. The Lu 2 first photomask process is used to define the first conductive layer to form the wiper =, ,, f and the gate of the thin film transistor. The second mask process is the channel layer of the membrane transistor and the ohmic contact layer. The third reticle is used to define a second conductive layer to form a data wiring and a thin film IGBT. The fourth fresh process is that silk will protect I v and turn. The fifth mask process is used to pattern the transparent conductive layer to form a halogen electrode. Gj and - slave film transistor LCD display to the large size of the hair", the production of thin film transistor array substrate will face many problems 1313065 0610052rrw 19662twf.doc / 006 and challenges, such as yield reduction and capacity decline and many more. Therefore, if the number of masks for the thin film transistor process can be reduced, that is, the number of exposure processes for thin film transistor elements can be reduced, the manufacturing time can be reduced, the throughput can be increased, the manufacturing cost can be reduced, and the yield can be improved.

Various methods have been proposed in the industry to reduce the number of masks. One way is to use a half tone mask (HTM) or a gray tone mask (GTM) to reduce the number of masks. This method is mainly used as a half-tone or gray-tone mask as two masks. After half-tone exposure and development, the gate region is etched, and then the source and the immersion region are etched. However, such a mask is expensive, and although the mask can be reduced, it is necessary to add a process for etching the photoresist, so that the cost cannot be reduced too much. In addition, it is not easy to use a half-tone or gray-tone reticle to control the pattern, which in turn causes problems such as alignment errors and lowers the yield.

. Therefore, how to reduce the number of masks and apply them to the current general process to reduce costs is one of the major problems to be solved. SUMMARY OF THE INVENTION The object of the present invention is to provide a thin film transistor array substrate which has a low manufacturing cost and a high process yield. The purpose of the other is to provide a thin film transistor array substrate to reduce the number of optical transistors used in the process of reducing the thickness of the thin film transistor, and then to provide a thin film transistor array substrate coating. In order to provide a thin film electro-crystal 1313065 0610052ITW 19662twf.doc/006 different from the conventional four-mask. A further object of the present invention is to provide a method for fabricating a thin film transistor array which uses a conventional reticle design to match part of the soil to achieve four reticle. For the above or other purposes, the present invention proposes a thin-film array substrate comprising a substrate, a patterned insulating gate insulating layer, a patterned second conductive layer, and a patterning guide. ^, a w-patterned first-conducting layer is disposed in

/ Β Most _ poles and most scan lines, and each pole is connected. The inter-insulating layer is disposed above the edge layer of the substrate I: t === The two conductive layers are located on the closed line. Its towel 'scanning and material matching area; each pole is located in it - the primed J on the f knife out of the majority of the painting is located above the corresponding pole, ^ two sources and the pole is the conductive sound m The layer is disposed between the closed insulating layer and the patterned first-charged layer, wherein the patterned Mm%-first conductive layer and the patterned first conductive region are patterned on the substrate to cover the layer Collection place. The protective layer is provided with a second conductive layer, and is accompanied by a build-up of the body layer and patterning the above-mentioned drain. A plurality of contact windows are respectively exposed to expose the electrodes through the layers 4, wherein each of the electrodes is in the present invention: t should be electrically connected. In the consistent application of the slave, the layer disposed on the interlayer insulating layer and the patterned second conductive layer is comprehensively 1313065 0610052ITW 19662twf.doc/006. In the embodiment of the present invention, the electrical layer is further included. The plurality of common wirings 'the common wirings are arranged in a large row and alternately on the substrate, and the gate insulating layer covers the common wiring. For the above or other purposes, the present invention further provides a method for fabricating a thin film array substrate, comprising the following steps. First, a substrate is provided which has a plurality of halogen regions. Next, the macro: on the board, wherein the patterned first-conducting layer package: a plurality of gates and a plurality of scan lines, and each of the closed electrodes forms an insulating layer with the Τ Τ, - semi-conductive Figure 图案 Patterning the first conductive layer. Thereafter, a photoresist layer is formed on the second conductive layer by patterning: patterning the second conductive layer 'to form a plurality of source and drain dipole:: lines, wherein the source and the drain are Located on the corresponding heart - the second and the - the data wiring is electrically connected. Next, forming a first: photoresist layer covering the semiconductor layer and the patterned first photoresist layer, which is exposed and ps, and the second photoresist layer is sandwiched by the substrate side to form a patterned second light. a resist layer, wherein the 円 layer is: 为 is a patterned first conductive layer and the second conductive second photoresist layer is a mask second-photo resist layer and a pattern is connected ί 2 corresponds to each _ Out-channel "Continue to the end, remove the first photoresist layer and the second photoresist layer. After == 丄1313065 0610052ITW 19662twf.d〇c/〇〇6, protect the 4 layers' ϋ secret system to form a majority = =: Pole. Finally, on the protective layer in each pixel area = the sex is far from the 6 poles' and each pixel electrode is electrically connected to its corresponding drain via its contact window. In the embodiment, the 'semiconductor layer includes a channel layer and an ohmic contact layer on the germanium layer. Body 2!! - In the embodiment, 'part of the semi-light guided above each gate is removed; The step of removing the ohmic contact layer that is violently ejected by the first-most layer at each of the poles is in the form of a pattern - the photo-resist layer is - Strip =: Real = 'patterned first - conductive layer more includes multi-body array for his purpose, this hair is made of a thin film electro-crystal beauty cup, r plate clothing method, including the following steps. First, provide - ί The guide plate has a plurality of halogen regions. After that, a picture is formed to form a dummy pole and a plurality of brooms. The conductive layer includes a majority connection. ΐ 且 各 且 且 且 且 且 且 且 且 且 各 各 各 各 各 各 各 各 各 各 各 r r r r r r r r r Forming a free insulating layer, - semiconductor formation - Figure H to cover the patterned first conductive layer. Thereafter, - a photoresist layer; an antilayer layer on the second conductive layer, by patterning the first and a plurality of times (four) one v electric layer to form a plurality of sources and bungee to the wood bellows wiring 'where the source and the secret are located corresponding to the closed 1313065 0610052ITW 19662twf.d〇c/〇〇6 '=Γΐ and its - data wiring Electrically connected. Thereafter, a photoresist layer is formed on the substrate to cover the semiconductor layer pattern: the photoresist layer. Further, (4)-guided; guide;; curtain, from the substrate side Performing a two-first patterning of the second photoresist layer on the second optical layer, and then forming a second photoresist layer to form a second photoresist layer. FIG place =; area of union of the conductive layer. Next, remove the second photoresist layer by removing the exposure from the pattern-plant layer light curtain. To pattern the first light = layer: conductor layer, so that the semiconductor layer == upper -, = layer, and in the Lai (four) shape several contacts. Finally, the protective layer in each of the halogen regions is electrically connected to the three-dimensional electrode via its corresponding one on the channel layer: the semiconductor layer includes a channel layer and a value-based conduction, ΐ In the embodiment, the step of removing a portion of the channel region above each of the idle electrodes is to remove the ohmic contact layer exposed by the photoresist layer above each gate. Type light == - In the embodiment, The patterned first photoresist layer is formed by patterning a plurality of common wirings of the first conductive layer in the embodiment of the present invention, and the wirings are arranged on the substrate alternately with the scanning wirings. τ订1313065 0610052ITW 19662twf.doc/006 ......, " π 1 w, π-% limit layer method includes an Ashing process. To achieve the above or other purposes, the present invention further proposes a film The method for fabricating a bulk array substrate comprises the following steps. Firstly, a substrate is provided, wherein the substrate has a plurality of halogen regions. Thereafter, a patterned first conductive layer is formed on the substrate, wherein the patterned first conductive layer comprises Multiple, inter-pole and majority scan wiring And each of the open electrodes is connected with the female-like matching. Then, an insulating layer, a guiding layer and a second conductive layer are sequentially formed on the substrate to cover the patterned first conductive layer:=== The first and most pieces of data are wired, in which the source and the 汲' are extremely thin, so that the semi-coupling = privately divides the partial semi-conducting field above each pole. After that, the second-light-resistance is formed.疋 出 出 这 这 这 这 这 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案After the conductive layer and the second conductive photoresist layer, the second photoresist is electrically formed and the region of the layer is formed. Next, the removal of the patterned removal removes the formed semiconductor substrate to form a protective layer. And in the protection of the if and the second photoresist layer. In order to expose the above-mentioned immersed. Finally 'in the == domain into the number of the number = layer touches the window 1313065 0610052ITW 19662twf.doc / 006 do not form a halogen electrode And each element is electrically connected to its corresponding drain. In one embodiment of the invention, one ohm on the channel layer . Via its corresponding electrode contact layer of the semiconductor layer comprises a contact window - a channel layer and the bit

In one embodiment of the invention, the step of migrating the layer to define the channel region, the ohmic contact layer exposed by the photoresist layer. In an embodiment of the invention, the P layer is composed of a positive photoresist, except for a portion of the semi-conducting layer above each gate, and the first patterned first photoresist layer and the second light are removed above each gate. In the embodiment of the present invention, the patterned first conductive layer further shares the wiring, and the common wiring and the scanning wiring are arranged substantially flush with each other on the substrate. In summary, the present invention utilizes a technique in which two layers of photoresist layers are combined to define a semiconductor layer and a channel, which can be applied to the current process of a thin film transistor array substrate.

However, the reticle is omitted, and the four masks are achieved, so that the fabricated thin film transistor array substrate has high process yield and low manufacturing cost. The above and other objects, features and advantages of the present invention will become more <RTIgt; 1 is a top view of a thin film transistor array substrate according to a preferred embodiment of the present invention; FIG. 2 is shown in FIG. 2; is shown as according to the present invention = 12 &lt; S ) 1313065 0610052ITW 19662twf .d〇c/006 - preferably complemented by - (iv) _ crystal transfer substrate substrate schematic flow diagram, this cross-sectional schematic is along the U in Figure i, the line of the line. Referring to FIG. 1 and FIG. 2A simultaneously, a substrate 110 is provided, and the substrate 11 is divided into a plurality of halogen regions u〇a. The substrate 11 can be a glass plate or a transparent plate of other materials. Next, a first electric layer 120 is formed on the wire board 110, and the first conductive layer 12 is patterned to form a plurality of gates 122 and a plurality of scanning lines m, wherein each of the scanning lines 124 is phase-to-phase The corresponding gate 122 is electrically connected. In the present embodiment, the material of the -V electrical layer 120 may be a network (9), a town (five), a crucible (10), a titanium (Ti), a can (A1) or an alloy thereof. It is worth mentioning that when the first conductive layer 120 is patterned, a plurality of common wirings 126 can be formed on the substrate. These wirings 126 and the wirings 124 are arranged substantially in parallel and alternately on the substrate 11A. Next, referring to FIG. 2B, a germanium layer 13 and a semiconductor layer 14 are sequentially formed on the substrate 110. And - the second conductive layer 150, the second box of the first: conductive please. In this embodiment, the material of the gate insulating layer may be nitride rock, oxidized stone or nitrogen oxynitride. In addition, the conductor layer 14G may include a channel layer 142 and an ohmic contact layer (4), and the material of the middle channel layer 142 may be amorphous, and the ohmic doped amorphous stone. Furthermore, the second conductive layer 15; 4 may be chromium (Cr), tungsten (%), butyl, and

Or its alloy. ) 1 (Ta) Titanium (Tl), Molybdenum (M〇), Shao (AD Figure%, forming a patterned first photoresist layer; brothers on the private layer 150, and by patterning the first - The photoresist layer 13 1313065 0610052ITW 19662twf.doc/006 patterns the second conductive layer 15A to form a plurality of source 152 and drain 154 and a plurality of data lines 156. The source 152 and each of the immersions I54 is located above the corresponding gate 122, and each source 152 is electrically connected to the corresponding data wiring 156. Next, please refer to ® 2D to form a comprehensive pattern on the substrate 110. a second photoresist layer 170 to cover the semiconductor layer 140 and the patterned first photoresist layer 160, the second photoresist layer 17 is composed of a negative photoresist. • In addition, the second photoresist layer 170 The thickness is thinner than the thickness of the first photoresist layer (10). Thereafter, referring to FIG. 2E, the patterned first conductive layer 12 and the first 'electric layer 150 are masked, and the second photoresist is from the substrate no side. Layer 1 仃 仃 = surface exposure and development process to form a patterned second photoresist layer 17 如图 as shown in Figure 2F. Since the second photoresist layer m is negative The type of photoresist, which is exposed after development, will remain, and the area where no light is exposed will be removed. Therefore, the portion of the second photoresist layer 17 that remains is patterned to the first conductive layer. 12G and the second conductive layer 15G are combined with a region other than the second conductive layer 15G. Referring to FIG. 2G, the patterned first photoresist layer "o and the first photoresist layer 170 are used as a mask to recite the back channel. A portion of the semiconductor layer (10) above each of the gates 122 is removed in a manner of 8 espresso oil (4), E), and a channel 142a is defined corresponding to each of the gates m by the semiconductor layer MG pads. In this embodiment, The gate contact layer 144 of the patterned first photoresist layer 160 is removed to define the channel region Ca. Thus, the source 152 and the drain 154 and the corresponding gate η] are 14 1313065 0610052ITW 19662twf.doc/006 and channel layer 142 constitute a thin film transistor and can be driven with data wiring 156. Receiver's picture 2H, remove all the first photoresist layer 16 to two - photoresist Layer 17. After that, please refer to Figure 21, on the _ ιι〇 upper layer 18 〇. The protective layer (10) covers the semiconductor layer] And patterning the first conductive layer 15〇, and the protective layer 18〇 plurality of contact holes are formed

Check 82 to expose the corresponding No. 154. Finally, referring to the figure, a pixel electrode 190 is formed on the protective layer (10) in each of the pixel regions l1Ga, and each of the pixel electrodes 19 is electrically connected to the corresponding drain 154 via its corresponding contact window. . In the present embodiment, the halogen electrode 19 is made of indium tin oxide (ITO) or other transparent conductive material. At this point, the thin film transistor array substrate 1 完成 process is completed. ^

In the process of the thin film transistor array substrate disclosed in FIGS. 2A to 2J, the step of patterning the second conductive layer 15 is patterned by using the patterned first photoresist layer 160, and then reused. The second photoresist layer 170 composed of the negative photoresist is coupled with a back exposure technique, so that the patterned second photoresist layer I% is located outside the first conductive layer 12 and the second conductive layer 15 Area. Then, the first photoresist layer 160 and the second photoresist layer 17 are used as masks to remove a portion of the semiconductor layer 14 恭 to define a channel region 142a of the thin film transistor. Therefore, the semiconductor layer 140 is still entirely overlaid on the substrate 110. In addition, in this embodiment, the present invention utilizes a two-layer photoresist layer in combination with an upper back exposure to define the position of the channel region, and thus can be omitted in the process of the thin film transistor array substrate - the light 15 1313065 0610052ITW 19662twf.doc/006 hood 'and thus reduce production costs. 3A to 3L are schematic cross-sectional views showing a manufacturing process of a _ transistor array substrate according to another preferred embodiment of the present invention, and the cross-sectional schematic view is also along the ι_[, hatching in FIG. Drawn. · I. First, please refer to FIG. 3A' to provide a substrate U, which is divided into a plurality of halogen regions 11Ga. The substrate m can be a transparent substrate of a glass substrate or other material. Next, a first conductive layer 120 is formed on the substrate 110, and the first conductive layer 120 is patterned to form a plurality of gates 122 and a plurality of scan lines 124, wherein each of the scan lines 124 is The corresponding gate 122 is electrically connected. In this embodiment, the material of the first conductive layer 120 may be road (Cr), tungsten (W), group (Ta), titanium (Ti), key _), s (A1) or an alloy thereof. It is worth mentioning that the present invention can form a plurality of shared wirings 126 on the substrate n〇 when the first conductive layer 12 is patterned. These common wirings 126 and the scanning wirings 124 are substantially parallel and alternately arranged on the substrate 11A. Next, referring to FIG. 3B, a dummy, edge layer 130, a semiconductor layer 14A, and a second conductive layer 15A are sequentially formed over the substrate 11A, and the first conductive layer 12 is patterned by the complex orphan. . In this embodiment, the material of the interlayer insulating layer 130 may be nitrogen cut, oxygen cut or oxynitride. In addition, the semiconductor layer 140 may include a channel layer M2 and an ohmic contact layer ,4, and the material of the middle channel layer 142 may be amorphous, and the ohmic contact layer 144 may be doped amorphous. Hey. In an embodiment of the present invention, the material of the first V pen layer 150 may be chromium (Cr), iron (w), group (ding &), titanium (Ti), molybdenum (Mo), aluminum (A1). Or its alloy. 16 1313065 0610052ITW 19662twf.doc/006 After that, please use the pattern of the first photoresist layer to pattern the first conductive layer 150 on the second conductive layer 150. Two conductive layers 150 are formed to form a plurality of source electrodes 152; 154 and a plurality of data lines 156. The source 152 and the electrode are located above the corresponding gate U2, and the source 152 and the data line 156 are electrically connected. 〃/, γ Next, please refer to ® 3D to form a second photoresist layer 〇7 〇 亡 , to cover the semiconductor layer U0 and the patterned first photoresist layer 2. In this embodiment, after the second photoresist layer 17 is formed by - please refer to FIG. 3A, the first conductive layer is patterned: the electric layer 150 is a mask, and the second layer is from the substrate 11 () side. The photoresist layer is exposed and developed to form the resist layer 172 shown in FIG. 3F. In this embodiment, since the patterned second photoresist diode is a positive photoresist, its characteristic is that it is exposed after development: a region which is wide without exposure to light is retained, and therefore, the resist layer 保留2 remains. The portion is a region where the second first conductive layer 150 is patterned. a 〇,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, An ashing process removes all of the _2 in the ^^, and can be modified as shown in Fig. 31, and the patterned first photoresist is moved to the mask by the back channel etching, Μ The field is divided by a semiconductor layer 17 &lt;S &gt; 1313065 0610052ITW 19662 twf.doc/006 14 部分 in the upper portion of each of the interpoles 122, so that a channel region 142a is defined in each of the semiconductor layers 140 corresponding to each of the gates 122. In this embodiment, the ohmic contact layer 144 exposed by the first photoresist layer 16 is removed to define the channel region 142a. Thus, the source 152 and the drain 154 and the corresponding gate and channel layer 142 constitute a thin film transistor, and can be driven by the scan wiring to be connected to the data wiring 156. Thereafter, please refer to FIG. 3J, the first photoresist layer 160. Θ Next, as shown in FIG. 3A, a protective layer iso is formed on the substrate 11A. The protective layer (10) covers the semiconductor layer 4'' and the patterned second conductive layer 150, and a plurality of contact windows 182 are formed in the protective layer (10) to expose the corresponding drains 154. Finally, referring to FIG. 3L, a halogen electrode (10) is respectively formed on the protective layer 180 in each of the domains 11a, and the pixel electrode 190 corresponds to the corresponding (f) corresponding to the contact f 18 . In this embodiment, the halogen electrode ^ tin oxide (Indi (tetra) tin Qxide, ΙΤ〇) or other transparent conductive material. So far, the thin film transistor array substrate 1 is completed, and the fabrication flow is as follows: the thin film transistor array substrate disclosed in FIGS. 3A to 3L "==the first photoresist layer 160 is subjected to the second conductive (four) and then reused] The second photoresist layer 170$ composed of a positive photoresist is provided with a (four) light technique 1724 located at the first conductive layer, a first resist layer, a second photoresist layer, and a second photoresist layer 17 The mask is defined as a pattern of the semiconductor layer 140. Therefore, the thin body = the cow body layer Μ 0 疋 is located in the brother - conductive layer (four) and the second conductive

18 1313065 0610052ITW 19662twf.doc/006 Layer 150 collection. 4A to FIG. 4A are schematic cross-sectional views showing a fabrication process of a transistor array substrate according to still another preferred embodiment of the present invention, and the cross-sectional schematic view is also taken along the line R of FIG. First, please refer to phase 4A to provide a substrate 11G on which a plurality of halogen regions 11〇a are formed. The substrate 110 can be a glass substrate or a transparent substrate of other materials. Next, a -first conductive layer 120' is formed on the domain plate m and the first conductive layer (4) is patterned to form a plurality of poles 122 of a plurality of scan lines 124, wherein each of the scan lines 124 疋-, The corresponding gate 122 is electrically connected. In this embodiment, the material of the first conductive layer 120 may be chromium (Cr), tungsten, or an alloy thereof. It is worth mentioning that, in the present day, when the conductive layer 12G is used, a plurality of sharing devices 126 can be formed on the substrate 110. These common wirings 126 and the scanning wirings are arranged substantially in parallel and alternately on the substrate 110. Next, referring to the item 4B, a gate, an edge layer 130, and a semiconductor layer 14 are sequentially formed over the substrate 11A. And a second conductive layer 15. To cover the patterned first conductive I 12G. In this embodiment, the material of the idle insulating layer =0 may be nitride rock, oxidized stone or gas oxidized stone. In addition, the semiconductor layer 140 may include a channel layer 142 and an ohmic contact layer 144, wherein the material of the enamel layer 142 may be amorphous, and the ohmic contact layer 144 may be doped amorphous. broken. In an embodiment of the present invention, the material of the first conductive layer 15G may be chromium (9), tungsten (w), tantalum (Ta), chin, molybdenum (Mo), aluminum (A1) or an alloy thereof. 19 1313065 0610052ITW 19662twf.doc/006

After that, please refer to FIG. 4C to form a patterned pattern, "one, ~ π cloth 7 〇 I) and 160 on the second conductive layer 15G, and patterned by the patterned _ photoresist layer _ The second conductive layer 15 is formed to form a plurality of source electrodes 152 and 154 and a plurality of data lines 156. The source electrodes 152 are respectively located above the corresponding gates 122, and the source electrodes 152 are electrically connected to the corresponding data lines 156, respectively. Next, referring to FIG. 4D, the patterned first photoresist layer 16 is used as a mask to remove the semiconductor layer 14A above the gates 122, so as to correspond to the gates 122 in the semiconductor layer 140. Do not define a channel area 1仏. In this embodiment, the ohmic contact layer 144 exposed by the patterned first photoresist layer pair is removed to define the channel region 142 &amp; Thereafter, referring to FIG. 4E, a second photoresist layer m is formed on the substrate 11A to cover the channel layer 142 and the bribed first light_(10). In this embodiment, the second photoresist layer 174 is composed of a positive-type photoresist. After the photoresist layer 174 is formed, the patterned first conductive layer 12 (the second conductive layer 12) and the second = electrical layer 150 are used as a mask to polish and develop the second photoresist layer 174 from the side of the substrate 11 . To form the patterned second layer 176 shown in Figure 4F. In this case, the second photoresist layer μ = wood positive photoresist is characterized by the fact that the exposed region after development is removed and the H region without exposure to light is retained. Therefore, the portion where the patterned photoresist layer m remains is the region where the patterned first conductive layer m is electrically combined (10). Thereafter, the second photoresist (6) is patterned as a mask to remove the exposed channel layer Μ] to define the pattern of the channel layer 142. 20 1313065 0610052ITW 19662twf.doc/006 Again, please refer to circle 4G, removing all and patterning the second photoresist layer 176. Thereafter, the width 160 (10) covers the channel layer U2 and the patterned first layer: a plurality of contact windows - 180 knives form a halogen electrode 9 〇, and the corresponding contact window 182 is electrically connected to the electrode 190 via The priests of the priests are connected to their corresponding bungee. In the crystal array === material. At this point, the process of completing the thin film transistor array substrate disclosed by _Lee, the step of sputum formation; after that, using the method of positive-type photoresist; == layer 17: with the technique of upper back exposure, The patterned tin is placed on the first conductive layer 12G and the second conductive layer 150. The pattern of the semi-idesis 140 is defined by the first photoresist layer 160 and the patterned second photoresist (four). Therefore, the semiconductor layer 140 in the thin layer 曰=:?: is located where the first conductive θ =0 is combined with the second conductive layer 150. The present invention utilizes a two-layer photoresist layer in combination with an upper backside exposure such that the pattern of the semiconductor layer and the location of the channel region. The four existing masks with the previous part of the process change to achieve the purpose of the cover 'making the thin film transistor array substrate 21 (S)' 1313065 0610052ITW 19662twf.doc/006 has a higher process Rate and lower production costs. The present invention has been disclosed in the above preferred embodiments, and it is not intended to limit the invention to any of ordinary skill in the art, and may be modified without departing from the spirit and scope of the invention. Retouching, therefore, the scope of the invention is defined by the scope of the towel. [Simple description of the map]

曰1', a is a top view of a thin film electrical raft array substrate in accordance with a preferred embodiment of the present invention. 2A to 2J are schematic cross-sectional views showing a fabrication process of a film transistor array substrate according to a preferred embodiment of the present invention: Thin - Figs. 3A to 3U are shown as another method according to the present invention. The production process section shows the meal, the meal - Fig. 4A to 41! It will be shown that the production process of the 溥 film transistor array substrate according to the present invention is _, the meal [main component symbol description] n 1 〇〇: thin film electricity Crystal Array Substrate 1 〇〇 ': Thin Film Transistor Array Substrate 100 ′′: Thin Film Transistor Array Substrate 110: Substrate 110a: Alizarin Region 120: First Conductive Layer 122 • Gate 124: Scan Wiring 22 1313065 0610052ITW 19662twf.doc /006 126: common wiring 130: gate insulating layer. 140: semiconductor layer - * 142: channel layer: 142a: channel region 144: ohmic contact layer 150: second conductive layer I 152: source 154: drain 156: Data wiring 160: patterned first photoresist layer 170: second photoresist layer 172: patterned second photoresist layer 174: second photoresist layer 176: patterned second photoresist layer 180: protective layer • 182: Contact window 190: halogen electrode 23

Claims (1)

1313065 0610052ITW 19662twf.doc/0〇6 X. Patent application scope: 1 - A thin film transistor array substrate, comprising: a substrate; first, an electric layer 'bit_substrate' in which the patterned pole and the ^ The wiring layer 'and each of the free conductive layers; the image layer' is disposed on the substrate, and covers the patterned first pattern, and the second conductive shore spoon s s, 'is located in the gate insulating layer Above, the pattern material wiring, \ a number of sources and a plurality of bungee poles and a plurality of resources to define a number of nrr lines and one of the data wiring on the substrate, each: "Knowledge, Each of the gates is located above the halogen regions, and each of the corresponding gates of the gate-patterned semiconductor c-wire is electrically connected; between the two conductive layers, the drum is placed on the gate insulating layer And the region where the patterned first patterned conductive-patterned semiconductor layer is located is where the second conductive layer is combined; the patterned semi-conductive plate is used to cover the pass-through electrode On the protective layer, wherein each of the two is as follows: application: profit = corresponding to The electro-polar connection is the first item of the 靶 键 key f board 'where the patterned semi-conducting crystal array base cow body layer 疋 is comprehensively arranged in the idle insulation 24 1313065 0610052ITW 19662twf.doc/0〇6 And the patterned second conductive layer. 3. The board of claim i, wherein the patterned first conductive type is further packaged, the common wiring of the body array and the scan wiring are substantially Parallel and = ^ The gate insulating layer covers the common wiring on the substrate: ''Year 4. - Thin film transistor array substrate fabrication, providing - substrate, wherein the substrate has a majority formation - patterned first - conductive Layered on the substrate; sequentially forming an insulating sound, a second conductive layer on the substrate to cover the patterned first conductive layer and a patterned first photoresist The first photoresist layer is patterned on the "two electric layer" by the pole and the drain and the plurality of data ^ are formed by a plurality of corresponding gates; the source and the drain are Among the bits - electrical connection; each of the source and the The data wiring forms a second photoresist layer, wherein the second photoresist layer 2: the patterned second base layer: (9) and the second conductive layer 厶 mask, from the patterned second photoresist layer, The light and development process is formed to form a --conducting layer - the second layer of the second layer - the layer is used for the figure: ° second; two electric two, the outer layer and the second pattern The photoresist layer is 1313065 0610052ITW 19662twf.doc/006, and the mask is removed, and the semiconductor layer corresponding to each of the gates is removed in the body layer to remove the first light in the semiconductor layer. a resist layer and a channel region are formed on the substrate; a resist layer; a contact window to expose the germanium respectively, and a plurality of _^' poles in each of the pixel regions are formed in the protective layer And each of the halogen electrodes is formed by the pair of electrodes on the pair 12b. The contact window of '%' is electrically connected to 5. The method for fabricating the fourth panel of the patent application, wherein the semiconductor layer comprises an ohmic contact layer on the monolayer-based array. The layer and the thin film transistor array substrate described in the item of the board, '', the portion of the semiconductor I#f that is removed from the upper portion of the gate, the step of removing the channel region is removed The ohmic contact layer exposed by the first photoresist layer above each of the open electrodes. 7. The method of fabricating a thin film transistor array substrate according to claim 4, wherein the patterned first photoresist layer comprises a positive-type photoresist ITS 〇 26 1 as described in claim 4 In the method of fabricating a thin film transistor array substrate, the patterned first conductive layer further includes a plurality of common wirings, and the common wiring lines are disposed substantially parallel to the scanning wirings and alternately disposed on the substrate. 2 9. A method for fabricating a thin film transistor array substrate, comprising: providing a substrate in which the substrate has a plurality of halogen regions; 1313065 06 J 0052 ΓΤ W 】 9662 twf! doc/006 forming a pattern of tiring On the substrate, the direct-distribution-conductive layer includes a plurality of inter-poles, and the pattern gates and the scan lines are electrically connected to the field wiring, and each of the #=the substrate is sequentially formed. An insulating layer, a second conductive layer covering the patterned first conductive layer h body layer and a patterned first photoresist layer patterned on the second patterned first photoresist layer, stomach, hunting The pole, the plurality of drains, and the plurality of strips; the pole is located above the corresponding pole, and the ^^ pole is electrically connected to each of the data wirings; a second photoresist layer on the substrate, the patterned first photoresist layer; the +-conductor layer and the patterned first conductive strip as a substrate side, the second photoresist layer is a mask, From the case of the second light exposure ^ development process to form a patterned first - conductive Disk ^Fig. 2 = where the photoresist layer is located, where the pattern is added, where the conductive layer is combined; the body layer is masked by the patterned second photoresist layer, and the exposed half is removed Deducting the second photoresist layer; a portion of the first photoresist layer is a mask "removing each of the gates above the other definition of the semiconductor layer corresponding to each of the interrogation points on the substrate sub-removing the patterning a first photoresist layer; a contact window to protect the layer, and a plurality of drains are formed in the protective layer; and 27 1313065 0610052ITW 19662twf.doc/006 poles, and each of the halogen electrodes The element is the corresponding pole. The contact S is electrically connected to 10. The method of fabricating the substrate of claim 9 wherein the semiconductor layer comprises an ohmic contact layer on the transistor array read channel layer. The channel layer and the method for manufacturing the substrate of the tenth substrate according to the patent application, wherein the step of removing the gates of each of the gates: 曰曰, body array layer &gt; to define the channel region is The ohmic contact layer exposed by the semi-conductive read-first photoresist layer: δ Λ above is 12. The method of manufacturing the substrate according to claim 9 of the invention, wherein the _ light, the transistor array photoresist. The first layer of the mouth system includes a positive type. 13. The method for fabricating the substrate of the ninth application of the patent scope, wherein the film has a common line of wiring, and the common lines are used for the line === The layers further include a plurality of and are alternately arranged on the wire. Some of the "wirings are substantially parallel". For example, the ninth application of the patent scope, +, the substrate manufacturer I #. The 溥 film transistor array gray method described] the method of removing the second photoresist layer includes The method for fabricating an integrated array substrate comprises: a prism substrate, wherein the substrate has a plurality of halogen regions; and the first conductive layer is formed on the substrate. The layer includes a plurality of scans and a plurality of scans. 28 1313065 0610052ITW 19662twf .d〇c/〇〇6 The idle pole is connected to one of the scan wires; a second conductive layer is sequentially formed on the substrate to cover the patterned first layer; the semiconductor layer and a Forming and patterning the first photoresist layer on the second conductive layer of the second conductive layer by patterning the first photoresist layer by using the pole and the plurality of data wirings Above the corresponding pole, each of the source is electrically connected to one of the poles; the source and the data wiring are patterned by the first photoresist layer to the semiconductor layer Semi-conducting = defining a channel area except for each of the closed poles ; 1 should form a second photoresist layer on each of the gates to form a patterned first photoresist layer; 〜' to cover the semiconductor layer and to pattern the first guide μ μ substrate The second photoresist is a mask, from where the first conductive layer is located, where the layer is, the pattern is formed, and the second layer of the conductive layer is patterned to form a second photoresist layer; Removing the exposed semiconductor to remove the patterned portion - for the resist layer and the second photoresist layer; contact windows to expose the non-polar; A plurality of the protective layers are formed in each of the pixel regions, and each of the pixel electrodes is electrically connected to the drain via the corresponding window: 29 1313065 0610052ITW 19662twf.doc/006. A thin film transistor array according to claim 15 wherein the semiconductor layer comprises an ohmic contact layer on the via layer. Day and place The method of fabricating a thin film transistor array according to claim 16, wherein the step of removing the portion above the gate is defined by the step of defining the channel region, The ohmic contact layer exposed by the photoresist layer above the gate. The method of fabricating a thin film transistor array according to claim 15 wherein the pattern photoresist layer and the second photo layer comprise a positive photoresist. The method of fabricating a thin film transistor array according to claim 15, wherein the patterned first conductive layer further comprises a plurality of 'shared wirings, and the common wiring lines are substantially parallel to the scan lines and Alternately disposed on the substrate. 30