TWI309043B - Apparauts and method for memory and apparauts and method for reduce pin - Google Patents

Description

1309043 * IX. Description of the Invention: [Technical Field] The present invention relates to a memory device and a test method, and more particularly to a memory chip and a device and test method for reducing test pins. [Prior Art] Due to the increase in the size and design complexity of memory chips and the unsatisfactory demand, the speed and accuracy of wafer testing has become the key to determining the productivity of memory chips. This has led to changes in wafer testing technology, such as the development of Design F〇r Testability (DFT) technology, which means increasing the circuit design during the wafer design phase to achieve effective reduction of wafer test time and improved error coverage. Improve product quality and production speed. In addition, the built-in self-tester (Bui]t_in sdf Test, BIST) can be used to reduce the test time of the wafer. The memory chip has a plurality of memory cells (cells, meaning the smallest unit constituting the memory). Some of the memory cells may be defective during the manufacturing process, and the solution to the defective memory cells is to prepare redundant memory cells. When a defective memory cell is found, the laser fuse is used to replace the defective memory cell with the excess memory cell to ensure that the operation of the memory chip is normal ‘and there is no doubt that the data is wrong. This stage is called the Fuse stage. The process of finding defective memory cells in memory before the high-fuse phase is called the high-fuse pre-fuse test phase. After the high fuse phase, it is necessary to verify again whether the memory chip is still

Client’s Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Final/Horowitz/Edward/O6Decl5 ;1309043 Cell “This process is called high-melting wire (PQSt-fuse) II! Test techniques for memory chips that have been developed, such as some techniques, in the test phase of the (10) pre-wire test, each of the memory chips is tested to find the lack of memory and then the high-solving action; In the silk stage, the shrinkage device (4) material square wire is used to check the memory crystal = no repair is completed. This technique is recorded in the pre-high wire test step = it takes a long time to find the defective memory cells in the wafer. In addition, the machine of the = class technology also needs to use more test pins to input the test data into the memory chip. x AL & Other techniques use BIST to find the defective memory cells of the memory chip and verify the defective memory cells before the high fuse and the high fuse. Such techniques reduce the time and excess of the above

The test pin problem, however, the high performance (fast and correct verification) BIST: the area of the wafer is large and the wiring of the circuit is too complicated, making the wafer clothing too expensive. SUMMARY OF THE INVENTION In view of the above, the present invention proposes a memory device and a reduced test pin device that achieve these and other objects by operating the devices. Embodiments of the present invention provide a memory device including a memory to be tested, a Reduce Pin Count (RPC) device, and a BI ST. The RPC device is used to find an erroneous address of the memory to be tested during the high pre-fuse test phase. The RPC device includes a solution multiplex cry and a validator. The multiplexer controls a plurality of wheel-in ends of the memory to be tested, and is configured to:

Client's Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Final/Horowitz/Edward/O6Decl 5 1309043 Enter a test data. The verifier 用以 is used to verify the plurality of outputs of the wheel memory of the memory to be tested, and after the 0-) test phase, the high-melting filament embodiment of the present invention further proposes whether the (four)^(10) body has an error. Out of the validator as well as - counter. The round 'includes a number of losers, and records the #pass-pass signal than the female. If at least one is different, then the two's are the same, then the one transmits the failure signal through the validator. . When the input means (4) the memory to be tested has an error indication signal, set. $ _ _ - (4) where the verification === caster method. First pass a (_) signal if at least one distinct = signal. When receiving the failure signal, the output is - error 2 ^ defeat wave 11) out of the output of the memory to be tested with an error data; : two '. It is intended to mean the above and other objects of the present invention. It is easy to understand, and the following is a better implementation; ^ ^ point can be more clearly explained as follows. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to make the objects, features, and aspects of the present invention preferred, the embodiments are described in detail. , Miaoyue " more obvious and easy to understand, the next range. It is not intended to limit its memory according to an embodiment of the present invention, and in the high-filament pre-test stage, it can be:

Client's Docket No.: 95-012 Quickly and accurately find TT's Docket No:0492-A40895-TW/Finaim〇rowitz/Edward/O6Decl5 1309043 • Defective memory cell in this memory chip to be tested ( The error address if any. Usually, a memory cell to be tested contains a plurality of memory cells (cel 1 ), which are arranged in a matrix and can be regarded as a memory array. The memory device in the embodiment of the present invention includes a memory to be tested, a Reduce Pin Count (RPC) device, and a BuiId-In Self Testing (BIST). When performing a high fuse pre-test, the RPC device finds possible error addresses in the memory to be tested. Then, in the high-fuse phase, the memory cells corresponding to the wrong address are replaced by the memory cells reserved in the memory. In the post-high fuse test phase, a BIST is used to verify that there is still an incorrect address in the memory. Please refer to Figure 1. Fig. 1 is a block diagram showing a memory device of a first embodiment of the present invention. The memory device can be a standard memory chip including a memory to be tested 130, a demultiplexer 110, a verifier 120, a pair of self testers 140, and a plurality of selectors 150. The above-mentioned memory to be tested is, for example, a DRAM array, an #array, or a Flash Memory array, and does not limit the range of the memory. The demultiplexer 110 and the verifier 120 can be regarded as each of the RPC devices because the demultiplexer 11 reduces the number of input pins, and the verifier 120 reduces the number of pins to be output. The above selector ι5〇 is used to determine whether the output of the memory to be tested 130 is rotated through its own position, or to the verifier 120 or the self-tester 140 for verification. This selector 150 is constructed, for example, of at least one transistor. The multiplexer 11 〇 is used to control the number of inputs of the memory array 13 0 to be tested,

Client's Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Final/Horowitz/Edward/O6Decl5 1309043 - Test data is entered; and the verifier 120 is coupled to the several outputs of the memory 130 to be tested. It is used to verify the output of this memory to be tested 13〇. When entering the high fuse pre-test phase, the RPC device is selected to accurately and quickly find the wrong address. In addition, the RPC unit reduces the use of test pins, saving the cost of test equipment. With the same probe card in the same number of test pins - the touch down, you can measure more memory devices like this one, which saves test memory chips. The average time. In the post-high fuse test phase, the _ shou can use either the RPC device or the self-tester 140 to verify that an error has occurred in the memory device. Fig. 2 is an embodiment of the verifier 12A in Fig. 1. As previously described, the verifier 120 is also a reduced test pin device. In Figure 2, the verifier 12 reduces the 16 outputs (A_p) to the remaining two outputs, thus reducing the test pins. The verifier 12{) includes an output verifier 210 and a counter 220. The output verifier 21 is used to receive a plurality of outputs of the memory 13 to be tested, and compare whether the outputs are the same. If the output is the same, a pass ## is transmitted through pin 242; conversely, if there is at least one distinct output, a fail signal is transmitted through pin 242. The fail signal on pin 242 also enables counter 220, so when output verifier 210 transmits a failure signal, counter 220 outputs an error indication signal 'to indicate the memory to be tested. The location of the output of an error data (ie, which of the output APs is the problematic memory cell in the memory to be tested). In the embodiment, the above error

Client's Docket No,: 95-012 TTss Docket No:0492-A40895-TW/Final/Horowitz/Edward/O6Decl5 /1309043 The ## indicates a wrong unit position (fai 1 ed ce 1 1 p〇sit i(10)) Timing diagram. The output verifier 210 described above includes a plurality of comparators 212K8 and an output combiner 214. The comparators are composed, for example, of logic gates, and each of the comparators 212n (n is an integer of 1·8) is used to receive a part of the outputs of the plurality of outputs of the memory 130 to be tested, thereby comparing the outputs of the parts. Is it the same? If it is the same, a temporary pass signal is transmitted. Conversely, if there is at least one different input, a temporary failure burst (1) letter ® is transmitted. In a preferred embodiment, a memory to be tested 13 has 16 outputs (outputs 〜A to P) that use eight comparators to receive these outputs. Each of the comparators 212 has three inputs for receiving the output, and the comparator 212 _8 (from top to bottom) receives the output of the memory 13 to be tested, which is ABC, BCD, EFG, FGH, IJK, JKL, ΜΝ0, and Ν0Ρ. Each of the comparators 212 n determines whether to output a temporary pass signal or a temporary fail signal in such a manner that the inputs are all the same. In some embodiments, fewer comparators may be used to compare whether the input from the output of the memory to be tested 130 is the same, and the scope is not limited herein. When the comparator 212 is compared to the data input from the output of the memory to be tested 130, each of the comparators 212 n outputs a temporary signal (temporary pass/temporary failure), and these temporary signals are input to an output merge. 2 Η. The output combiner 214 (which may be constructed of a plurality of logic gates) combines the temporary signals transmitted by the comparators 212p8 to determine whether or not the comparators 212U8 output a temporary pass signal. If the comparators 212K8 all output a temporary pass signal, it means that all the outputs 阜A~P are output.

Client's Docket No.: 95-012 TT^ Docket No:0492-A40895-TW/Fmal/Horowitz/Edward/O6Decl5 10 1309043 - so the round-out combiner 214 outputs a pass signal through pin 242; There is an output temporary failure signal in the device 212m, indicating that at least one output 阜A~P has an output different from the output of the other output ( (as an error), so the output combiner 214 outputs a failure nick through the pin 242, The B Guard Enable Counter 220 triggers all of the comparators 8, and the comparator 212m begins to recognize which output port has an error message and informs the counter 220. The counter 22 outputs an error indication signal indicating the position of the output of an erroneous data in the memory to be tested. • Figure 3 shows a possible timing diagram of the error indication signal output by counter 220 in Figure 2. The upper part of the figure is the reference working clock Clock, and the lower part is the error indication signal 302. After initiation section 304, error indication signal 302 can be sliced into segments 306i 8, wherein each segment 306n corresponds to a comparator 212n, wherein the waveform change can be used to determine a plurality of input data for comparator 212n. The correctness. First, it is seen that the waveforms 306^ corresponding to the first three comparators 212 are horizontal waveforms, and the representative of the waveforms is that the data of the input comparators 212ι_3 are correct. Then, it is seen that the waveform 3Ο64 corresponding to the comparison state 2124 is a rising waveform (p〇wer Up), indicating that the data transmitted by the output of the comparator 2124 is correct, but the output is transmitted. The information coming is wrong. Finally, the waveform 3066 corresponding to the comparator 2126 is a falling waveform (p〇wer D〇wn), which represents the data from the output 阜L of the input comparator 2126 'data misranked by the output 阜κ' correct. In other words, through the error indication signal timing diagram, the output of the above-mentioned memory to be tested can be found (output 阜Α~Ρ), and the problematic data is output 阜η and output 阜κ

Client's Docket No.: 95-012 TT^ Docket No:0492-A40895-TW/Final/Horowitz/Edward/,06Decl 5 11 .1309043 The outgoing data was normal. The relative meaning of the waveforms represented by the skilled person is self-defining and does not limit its scope here. Figure 4 is a flow chart of a memory test method in accordance with an embodiment of the present invention. First, an error address of the memory to be tested is found by an RPC device (step S410). This error address refers to the address of the defective memory cell in a memory to be tested. Before the high-fuse repair is performed, it is necessary to find out the address of these defective memory cells' subsequent repair operations in the high-fuse stage. Next, a defective memory cell is replaced by a redundant memory cell (step S420). Finally, it is again verified whether there is at least one error in the memory to be tested (step S430). The user can choose to verify with an rPc device or with a self tester (BIST). Take the memory device in Fig. 1 as an example. Before the high-fuse repair, an rPC device consisting of the multiplexer 11〇 and the verifier 12〇 can be used to input data and compare the outputs to find the wrong position of the defective memory cell. At the high-fuse stage, the missing memory is replaced by the excess memory cell. After the high fuse stage, the demultiplexer 110 can be used together with the verifier 120, or the pair of self testers 14 can be used to confirm whether the memory 130 to be tested is still defective. Figure 5 is a flow chart of the test pin reduction test method of the present invention. Please refer to Fig. 2 and Fig. 1 at the same time. The output verifier 210 verifies whether the number of rounds of the object to be tested 130 are identical (step S510), and if so, transmits a pass signal (step S520) 'If at least one of the differences is transmitted, a failure is transmitted ( Fail) signal (step S530). Then, when the output verifier 21〇

Client's Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Fmal/Hor〇witz/Edward/O6Decl5 12 •1309043 2 When this failure signal is issued, the round-out verifier 21G enables the counter 22〇 to k feet Bit 244 outputs an error indication signal (step s54〇) for indicating the location of the output of the black female seedling h in the memory 130 to be tested. Fig. 6 is a flow chart for the comparator 212i of Fig. 2, for which the error tribute is issued from which rounds, which is also equivalent to indicating the wrong position of the defective cell. A similar flow chart can be applied to the other comparator comparator 212n, which is not described here. • Assume that the outputs of outputs 阜A, B, and c are data a, b, and c, respectively. Step S602 first compares whether the data & is the same as b. If so, a temporary pass signal is output (step S_); if not, a temporary fail signal is output (step S606). When the data & is different from 1), in order to find out which of the data a and b is wrong, the data c is used as a reference. If the materials a are the same as c (YES in step S608), it is confirmed that the material b is erroneous (step S612). If the materials a and c are not the same (NO in the step s6 to 8), meaning that the data b is the same as c, then the confirmation data & is wrong (step S61). • Simply put, it is a majority decision. If the same information is more than one copy, it is correct. A relatively small amount of data is wrong. Thus, the comparator 212i can output a relative signal to the counter 220' and the counter 220 can generate an error indication signal similar to that in Fig. 3 to tell the external tester that the error location of the memory cell is missing. In summary, the memory device of the present invention quickly finds the wrong address in the RPC device of the present invention before the high-strength wire for repair in the high-fuse phase. Thus, embodiments of the present invention are compared to conventional memory devices

Client's Docket No.: 95-012 TT!s Docket No:0492-A40895-TW/Final/Horowitz/Edward/O6Decl5 13 The memory device in 1309043 can reduce the test pins required for the test machine. From another point of view, a probe card with the same number of pins can test more units of memory devices in one touch down. This can reduce the average test time of the memory device. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. * BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a memory device according to a first embodiment of the present invention. Figure 2 is a block diagram of a reduced test pin device of a second embodiment of the present invention. Figure 3 is a timing diagram for reducing the error unit address output of the counter in the test pin device. $ Fig. 4 is a flow chart of the memory test method of the present invention. Figure 5 is a flow chart of the test method for reducing the test stitch of the present invention. Figure 6 is a flow chart showing the output of the memory to be tested with error data in Fig. 5. [Description of main component symbols] 110: Demultiplexer; 120: Validator; 130: Memory to be tested; 140: Self tester; 150: Selector; 210: Output validator; 212: Comparator; 214: Output Combiner

Client's Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Final/Horowitz/Edward/,06Decl5 14 1309043 220: Counter; 242, 244: Pin; 302: Error indication signal; 304: Start zone Section; 306: small section.

Client’s Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Final/Horowitz/Edward/O6Decl5 15

Claims (1)

1309043 X. Patent application scope: 1. A memory device, including: a memory to be tested; a Reduce Pin Count (RPC) device for pre-fuse The test phase finds an error address of the memory to be tested, and includes: - a solution of 4, a plurality of input terminals of the control memory for rotating a test data; and a verification device, And coupling a plurality of outputs of the memory to be tested to verify an output of the memory to be tested; and a Buiit-in Self Test (BIST) for after the high fuse (post-f Use ) The test phase checks if the memory to be tested has an error. 2. The memory device of claim 2, wherein the memory device further comprises a selector </ RTI> for selecting the Rpc device or the self tester to detect the memory to be tested. 3. The memory device according to claim 1, wherein the memory to be tested is a Dynamic Random Access Memory (DRAM) array, and a static random access memory (static Rand〇). m Access Memory, SRAM) array, or flash memory (Flash Mem〇ry) array. 4. A device for reducing test pins, comprising: an output validator for receiving a plurality of outputs of a memory to be tested, and comparing a "half output" is the same, and a right pass transmits a pass signal. If at least one is different, a fail signal is transmitted; and Client's Docket No.: 95-012 TT's Docket No: 0492-A40895-TW/Fmal/Horowitz/Edward/O6Decl5 16 13〇9〇43 'When the w, the error--, the verification 11 transmits the failure signal, the output is in a wrong position. One of the erroneous data is stored in the memory to be tested. 5. For example, the error indication signal is the reduced test pin device described in the item. ', failed cell position (failed cell position) 6 as in the patent application Fan Lulu output test, including the reduced test pin device described in the item, wherein several comparators, of which several parts of the output towel If the face is the same, then if it is the same, then it will be transmitted - temporarily, if the parts are the same, the fail signal; if the coffee field is at least - the difference is transmitted - an output combiner is used to break Whether the comparators are all; the temporary signals transmitted by the device, 7. such as the patent application; the first = temporary signal. Read some comparisons at least 1 group of gates = slaves to reduce the needle "set, then 8. If the scope of patent application is 6th, the round-up merger consists of several logical idles", the test pin device, its bow 9. The test pin method includes: verification - the number of outputs of the memory to be tested is a send-through (clear) signal, if at least the king is the same as the number; and - the field (fail) # when the failure signal is transmitted, the output An error indicates that the memory to be tested (4) m material - the output is located ^ indicates driving or〇wuz/Edward/O6Dec 15 Client's Docket No.: 95-012 TT's Docket No:0492-A40895-TW/Final/Hi 17