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TWI301649B - Bga package and manufacturing method thereof - Google Patents

Bga package and manufacturing method thereof Download PDF

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Publication number
TWI301649B
TWI301649B TW094108391A TW94108391A TWI301649B TW I301649 B TWI301649 B TW I301649B TW 094108391 A TW094108391 A TW 094108391A TW 94108391 A TW94108391 A TW 94108391A TW I301649 B TWI301649 B TW I301649B
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Taiwan
Prior art keywords
pad
insulating layer
region
substrate
bga package
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TW094108391A
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Chinese (zh)
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TW200603302A (en
Inventor
Hyo Soo Lee
Tae Gon Lee
Sung Eun Park
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Samsung Electro Mech
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Publication of TWI301649B publication Critical patent/TWI301649B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1301649 九、發明說明： 【發明所屬之技術領域】 本發明是有關於球栅陣列封裝（BGA)的晶片封裝及其 ，造的方法；尤指一種具有更優越之可靠性，並有：佳的 ，面性質及墜落測試結果之BGA封裝法；界面同時，本發 ::也有關於一種BGA封裝的製造方法，其將接墊的開放心 —刻至防焊罩下方，以在底部中央形成—平面餘刻區盘 外緣形成傾斜㈣區，而提供了焊料更大的搭接區域。 10 151301649 IX. Description of the Invention: [Technical Field] The present invention relates to a chip package of a ball grid array package (BGA) and a method of fabricating the same, and more particularly to a superior reliability and a good BGA encapsulation method for surface properties and fall test results; interface, at the same time, this: There is also a manufacturing method for a BGA package, which engraves the open core of the pad under the solder mask to form a plane at the center of the bottom The outer edge of the remnant disc forms a slanted (four) region, providing a larger overlap area for the solder. 10 15

【先前技術】 雖然積體電路朝向輕薄細小而發展，但是積體電路封 衣所擴張的導線數目是有增無減；針腳陣列封襄法（ΜΑ) 的發展，是為了解決在-個小小的封裝載體内須要大量的 導線數目㈣題’而為能在小小的面積巾擁有大量的導 線，PGA載體因針腳及導線太脆弱而容易斷裂，故積體密 度因此而受限。 、 為了克服PGA封裝上的缺點，有一種方式便是使用近 來愈來愈普遍的BGA封裳基板。嶋封裝基板使用的焊球 車父針腳更纖細，因此使得基板上可有高積體密度。通常遍 封裝基板是用以嵌置半導體晶片。 為了更進V 了解此項發明的背景，以下將對於一般 B G A封裝基板做一番介紹。 參考圖卜為-般組襄有半導體晶片之謝封裝橫截面 視圖，其中以焊球60代替針腳。 20 1301649 最初，準備一些銅箔基板（CCL)1〇，每個銅箔基板⑺ 都#工過心準的光照钱刻（photolithographic)製程以預先在基 板上形成電路圖案。[Prior Art] Although the integrated circuit is developed toward thinness and thinness, the number of wires expanded by the integrated circuit seal is increasing; the development of the stitch array sealing method (ΜΑ) is to solve the problem. In the package carrier, a large number of wires (four) are required. In order to have a large number of wires in a small area towel, the PGA carrier is easily broken due to the pin and the wire being too weak, so the density of the body is limited. In order to overcome the shortcomings of the PGA package, one way is to use the BGA sealing substrate which is more and more popular recently.焊The solder balls used in the package substrate are more slim, so that the substrate can have a high density. Typically, the package substrate is used to embed a semiconductor wafer. In order to further understand the background of the invention, the following will introduce the general B G A package substrate. Referring to the drawings, there is a cross-sectional view of a semiconductor wafer in which a solder ball 60 is used instead of a pin. 20 1301649 Initially, some copper foil substrates (CCL) were prepared, and each copper foil substrate (7) was subjected to a photolithographic process to form a circuit pattern on the substrate in advance.

10 1510 15

然後’將每個帶有電路圖案的銅箔基板1〇彼此擠壓形 成一個薄板狀的結構，接著加工以形成引洞（via hole) 20, 再以銅箔30電鍍於引洞（via h〇ie) 2〇，使每個銅箔基板1〇上 的電路圖案可導電連接。 在薄片狀的銅箔基板上的一側所形成的銅箔3〇上，可 藉由光蝕刻形成一個半導體晶片嵌合用之接墊的電路圖 案，如·接線針腳50。同樣地，接墊電路圖加上焊料6〇， 即焊墊電路圖70,亦形成於銅箔基板結構的另一側之銅箔 30上。 在銅箔基板10的銅箔30上形成了接墊50及7〇的電路圖 案之後，使用光感應成像防焊罩（PSR)墨水以形成防焊光 罩，目的是為了保護在銅箔30上的電路圖案，以及在焊接 過程中預防電路圖之間彼此形成焊橋連接。 接著，藉著在電路圖上形成偶氮化合物膜，使接觸到 焊墊，接著以一固化步驟移除附著在線腳5〇或將形成焊墊 70位置的防焊光罩80。 在形成了接墊如線腳50和焊墊70後，接著進行一防止 接墊氧化的表面處理步驟，即藉由無電電鍵金而形成一層 鎳/金鍍層。 θ 更詳細地說，接墊如線腳5〇或焊墊7〇都將會被鍍上 鎳，形成一鎳鍍層91到一預設高度，如3_5//m。 1301649Then, each of the copper foil substrates 1 having the circuit pattern is extruded to each other to form a thin plate-like structure, which is then processed to form a via hole 20, and then plated with copper foil 30 in the via hole (via h〇). Ie) 2〇, the circuit pattern on each copper foil substrate 1 can be electrically connected. On the copper foil 3 formed on one side of the sheet-like copper foil substrate, a circuit pattern of a pad for semiconductor wafer fitting, such as the wiring pin 50, can be formed by photolithography. Similarly, the pad circuit pattern plus solder 6 〇, i.e., the pad circuit pattern 70, is also formed on the copper foil 30 on the other side of the copper foil substrate structure. After the circuit patterns of the pads 50 and 7 are formed on the copper foil 30 of the copper foil substrate 10, a photo-sensitive imaging solder mask (PSR) ink is used to form a solder mask for the purpose of protecting the copper foil 30. The circuit pattern and the preventive circuit diagrams form a solder bridge connection between each other during the soldering process. Next, by forming an azo compound film on the circuit pattern, the pad is brought into contact, and then the solder mask 80 attached to the wire leg 5 or the position of the pad 70 is removed in a curing step. After the pads such as the legs 50 and the pads 70 are formed, a surface treatment step for preventing oxidation of the pads is then performed, i.e., a layer of nickel/gold plating is formed by electroless gold bonding. θ In more detail, the pads such as the wire 5 turns or the pads 7 will be plated with nickel to form a nickel plating 91 to a predetermined height, such as 3_5//m. 1301649

^金應用於未電㈣接墊观7叫，金會擴散進 墊的銅結構中，而無法於此層上進行表面處理步驟。 因此，先鍍一層鎳後再鍍上金，可防止 入銅的結構中。 H —擴散進 …接著，在鎳鑛層上面形成—具有預設高度如G.03-0.07 微米的金鍍層92，以增加焊料6〇的親合性。因此，完成一 具有可組裝半導體裝置的腳針及用來貼附焊料之焊 BGA封裝。 10 15^Gold is applied to the un-electric (four) pad view, the gold will diffuse into the copper structure of the pad, and the surface treatment step cannot be performed on this layer. Therefore, plating a layer of nickel and then plating gold can prevent it from entering the copper structure. H - diffusion into ... Next, a gold plating layer 92 having a predetermined height such as G.03 - 0.07 μm is formed on the nickel ore layer to increase the affinity of the solder 6 。. Thus, a foot pin having an assemblyable semiconductor device and a solder BGA package for attaching solder are completed. 10 15

4在此類傳統BGA封裝中，鎳/金鍍層的形成不單只是保 護由導電金屬如銅製得的焊墊7〇以防其氧化，更可以提供 丈干料60更大的親合性，然而，因為鍍層卯中的鎳與焊料⑼ 中的錫產生反應’故會產生金屬間化合物（intemetaiiic compounds) 〇 個咼速衝擊測試如墜落試驗顯示，在焊料及鎳/金鑛 層9〇兩者的界面容易發生斷裂，因為在鎳/金鍍層間的金原 子/、知料產生了反應而有了易碎的金屬化合物的出現。 曰這也因此使得焊料60與焊墊容易分開。為了解決此問 題，在BGA封裝製程，完成半導體晶片組裝的接墊或焊墊 中’使用有機焊料保護膜（OSP)來替代鎳/金鍍層90。 在加上焊料的焊墊上形成鎳/金鍍層90的狀況下，有機 烊料保護膜（〇SP)會在焊墊上成膜並使開放的焊墊之塗層 導電。 其後’經過有機焊料保護膜（OSP)處理的BGA封裝基 板，遇須再經一線上（in_iine)製程，其包括預烤（prebake)， 20 13016494 In such a conventional BGA package, the formation of the nickel/gold plating not only protects the pad 7 made of a conductive metal such as copper to prevent oxidation thereof, but also provides a greater affinity for the dry material 60, however, Because the nickel in the coating 产生 reacts with the tin in the solder (9), it will produce intertemetaiiic compounds. An idling impact test, such as the drop test, shows the interface between the solder and the nickel/gold layer. It is prone to breakage because the gold atoms/, between the nickel/gold plating layers, reacted and a fragile metal compound appeared. This also makes it easy to separate the solder 60 from the pads. In order to solve this problem, an organic solder resist film (OSP) is used instead of the nickel/gold plating layer 90 in the BGA packaging process to complete the pad or pad of the semiconductor wafer assembly. In the case where a nickel/gold plating layer 90 is formed on the solder pad, the organic germanium protective film (〇SP) forms a film on the pad and conducts the coating of the open pad. Subsequent 'BGA package substrates treated with an organic solder mask (OSP) are subjected to an in-line process, including prebake, 20 1301649

10 1510 15

晶元接著（die attach)，晶元接著固化（die attach curing)，電 漿處理（plasma)及打線接合（wire bonding)，才將導體元件接 合在形成於BGA封裝基板一側的焊墊上。 將半導體元件接著於接墊上之線上製程（in_line process)’還須經過一後段封裝製程（back-end process)，包 括預烤（prebake)、電聚處理（piasma)、封膜前固化（pre-m〇ld curing)、封膜後固化（p〇st_m〇id curing)、焊料接著（solder attach)及紅外線迴焊（ir refi〇wer)，以使焊料接著於連接在 BGA封裝基材另一侧的焊墊上。 然而經由圖3顯示BGA封裝製程中使用有機焊料保護 膜是有缺點的’因為使用有機焊料保護膜在焊墊的鍍層上 會受到線上製程（in-line process)或後段封裝製程（back-end process)的熱損傷’尤其是在後段封裝時的封膜前固化處理 達到175°C或更高’這會造成有機焊料保護膜的破壞。 參考圖4,焊點剪力測試顯示在bgA封裝基板上形成搭 接針腳及焊墊的鍍層上的有機焊料保護膜，會在線上製程 (in-line process)及後段封裝製程（back-end process)中受到 熱破壞。 由圖5顯示’當焊料與沒有達到預定蝕刻深度的平面鍍 2〇 層170接合時，有機焊料保護膜200將被熱破壞，而所剩下 之有機焊料保護暝200則使得鍍層170和焊料600間的搭接 面積減少’亦防止了鍍層170中的銅與焊料600中的錫發生 作用，抑制產生金屬間化合物7〇〇。The die attach, the die attach curing, the plasma and the wire bonding, and the conductor elements are bonded to the pads formed on the side of the BGA package substrate. The in_line process of the semiconductor component on the pad must also undergo a back-end process, including prebake, piasma, and pre-film curing (pre- M〇ld curing), post-film curing (p〇st_m〇id curing), solder attach and infrared reflow (ir refi〇), so that the solder is then attached to the other side of the BGA package substrate On the solder pad. However, the use of an organic solder protective film in a BGA packaging process is disadvantageous by means of FIG. 3 because the use of an organic solder protective film may be subjected to an in-line process or a back-end process on the plating of the pad. The thermal damage 'especially the pre-sealing curing treatment at the end of the package reaches 175 ° C or higher' which causes damage to the organic solder protective film. Referring to Figure 4, the solder joint shear test shows an organic solder protective film on the plating layer of the bonding pins and pads on the bgA package substrate, which will be in-line process and back-end process. ) was damaged by heat. It is shown by Fig. 5 that when the solder is bonded to the planar plating layer 170 which does not reach the predetermined etching depth, the organic solder resist film 200 will be thermally destroyed, and the remaining organic solder resist 200 will cause the plating layer 170 and the solder 600. The reduction in the overlap area between the two also prevents the copper in the plating layer 170 from acting on the tin in the solder 600, suppressing the generation of the intermetallic compound 7〇〇.

Claims (1)

l3〇l649L3〇l649 刻步驟後於該餘刻區進行一 一表面處理步驟。After the engraving step, a surface treatment step is performed in the residual region. 十、申請專利範圍·· 1. 一種製造BGA封裝基板的方法，包含了下列步驟： 準備一具有接墊之BGA封裝基板； 塗覆一絕緣層於該BGA封裝基板上，並形成一缺口以 露出該接墊，該缺口直徑小於該接塾；以及 蝕刻自該接墊之該外露表面到該絕緣層塗覆區域的一 部份，以形成一具有凹槽構形之蝕刻區。 2·如申請專利範圍第1項所述之方法，其中該準備步 驟包含： 處理一銅箔層板以形成複數個引洞，以使該基板上之 層與層間導電連結； 以銅電鍍該銅箔層板與該等引洞以形成一鍍層；以及 於該鍍層上進行一光蝕刻程序，以形成電路與接墊之 電路圖案。 、3 ·如申喷專利範圍第1項所述之方法，其中該蝕刻區 為底部中央平面，以及一傾斜之周邊。 ▲ 4.如中請專利範圍第i項所述之方法，其中該缺口與 该钮刻區同樣形成—具有閃的磨益形結構。 5.如申請專利範圍第i項所述之方法，其更包含在钱 6. 步驟後3 口間以幵 18. 1301649 7·如申請專利範圍第6項所述 驟包含：X. Patent Application Range 1. A method for manufacturing a BGA package substrate, comprising the steps of: preparing a BGA package substrate having a pad; coating an insulating layer on the BGA package substrate, and forming a gap to expose The pad has a diameter smaller than the contact; and etches from the exposed surface of the pad to a portion of the insulating layer coating region to form an etched region having a groove configuration. 2. The method of claim 1, wherein the preparing step comprises: processing a copper foil laminate to form a plurality of via holes to electrically connect the layers on the substrate to the layers; and plating the copper with copper a foil laminate and the via holes are formed to form a plating layer; and a photolithography process is performed on the plating layer to form a circuit pattern of the circuit and the pad. 3. The method of claim 1, wherein the etched region is a bottom central plane and a slanted perimeter. ▲ 4. The method of claim i, wherein the notch is formed in the same manner as the button engraving region - having a flash-shaped structure. 5. The method described in claim i, which is further included in the three paragraphs after the step of money 6. 幵 18. 1301649 7 · as described in item 6 of the scope of the patent application: 之方法，其中該沉積步 ，覆-黏性防焊劑（post_flux)於該餘刻區上； . #由該防焊劑貼上傳導連接材料於該接墊上；以及 .5 料接墊上之該傳導連接材㈣彳卜紅外線迴焊以 ^金屬間化合物，使該傳導連接物質結合於該餘刻區。 8Ht專利範圍第7項所述之方法，其中在該姓刻 =與該傳導連接物質間之該金屬間化合物，係形成於已覆 蓋該絕緣體的該蝕刻區之周圍。 1〇 9·如中請專利範圍第6項所述之方法，其中該傳導接 合物質為一焊料。 10*種製造BGA封裝基板之方法，包含下列步驟： 準備一具有接墊之BGA封裝基板； 塗覆一絕緣層於該BGA封裝基板上，並形成一缺口以 15 露出該接塾，該缺口直徑小於該接墊； 蝕刻自该接墊之該外露表面到該絕緣層塗覆區域的一 瞻部份，以形成一具有凹槽構形之蝕刻區；以及 礙置一半導體晶片於該BGA封裝基板中，進行該半導 體晶片之封膠。 20 1丨·如申請專利範圍第10項所述之方法，其中該準備 步驟包含： 處理一銅箔層板以形成複數個引洞，以使該基板上之 層與層間導電連結； 以銅電鍍該銅箔層板與該等引洞以形成一鍍層；以及 19 1301649 G 於該鑛層上進行-光敍刻程序，以形成電路 電路圖案。 一女公 12·如巾請專利範圍第1G項所壤之方法，其中該㈣ 區為底部中央平面，以及一傾斜之周邊。 13·如申請專利範圍第10項所述之方法，其更包含在 蝕刻步驟後於該蝕刻區進行一表面處理步驟。 匕各The method, wherein the deposition step, a tack-type solder resist (post_flux) is on the ruthenium region; # affixing a conductive connection material to the pad by the solder resist; and the conductive connection on the .5 material pad The material (4) is infrared reflowed with an intermetallic compound to bond the conductive linking substance to the residual region. The method of claim 7 wherein the intermetallic compound between the surname and the conductive linking material is formed around the etched region that has covered the insulator. The method of claim 6, wherein the conductive bonding material is a solder. 10* method for manufacturing a BGA package substrate, comprising the steps of: preparing a BGA package substrate having a pad; coating an insulating layer on the BGA package substrate, and forming a notch to expose the interface, the notch diameter Less than the pad; etching from the exposed surface of the pad to a portion of the insulating layer coating region to form an etched region having a recessed configuration; and occluding a semiconductor wafer on the BGA package substrate The sealing of the semiconductor wafer is performed. The method of claim 10, wherein the preparing step comprises: processing a copper foil laminate to form a plurality of via holes to electrically connect the layers on the substrate to the layers; The copper foil laminate and the lead holes form a plating layer; and 19 1301649 G performs a light characterization process on the deposit layer to form a circuit circuit pattern. A female public 12, such as the towel, please refer to the method of the 1G item of the patent scope, wherein the (four) zone is the bottom central plane, and a sloped periphery. 13. The method of claim 10, further comprising performing a surface treatment step in the etched region after the etching step.匕 匕 10 1510 15 20 14.如申請專利範圍第10項所述之方法，其在表面處 理步驟後，更包含了沉積-傳導連接物質於該_區與該 缺口間以形成一外部端子，該蝕刻區比該缺口之截面積更 寬。 、 15·如申請專利範圍第14項所述之方法，其中配置步 驟包含： _ 塗覆一黏性防焊劑（P〇St-flUX)於該蝕刻區上； 藉由該防焊劑貼上傳導連接材料於該接墊上；以及 於該接塾上之該傳導連接材料進行一紅外線迴焊，以 形成一金屬間化合物，使該傳導連接物質結合於該蝕刻區。 16·如申請專利範圍第15項所述之方法，其中在該蝕 刻區與該傳導連接物質間之該金屬間化合物，係形成於已 覆蓋該絕緣體的該蝕刻區之周圍。 17 ·如申凊專利範圍第14項所述之方法，其中該傳導 連接物質為一焊料。 18· — BGA封裝基板，包含： 一外部電路層，該外部電路層含有一經蝕刻而具有凹 形表面之接塾；以及 20 1301649The method according to claim 10, further comprising, after the surface treatment step, a deposition-conducting connection substance between the _ region and the gap to form an external terminal, the etched area being smaller than the gap The cross-sectional area is wider. The method of claim 14, wherein the configuring step comprises: _ coating a viscous solder resist (P〇St-flUX) on the etched region; and attaching the conductive connection by the solder resist The material is on the pad; and the conductive connecting material on the interface is subjected to an infrared reflow to form an intermetallic compound, and the conductive connecting substance is bonded to the etching region. The method of claim 15, wherein the intermetallic compound between the etched region and the conductive linking material is formed around the etched region that covers the insulator. The method of claim 14, wherein the conductive connecting substance is a solder. 18· — a BGA package substrate comprising: an external circuit layer comprising an etched interface having a concave surface; and 20 1301649 一絕緣層，形成於該外·部電路層上，該絕緣層具有一 锋暴路.亥接墊，該缺口之直捏小於該接塾，以顯露部分 ^凹形表面，且該凹形表面之周圍被該絕緣層覆蓋，並於 该絕緣層之下表面及該凹形表面之間產生一間隙。 19·如申請專利範圍第18項所述之基板，其更包含一 連接材料層，形成於該絕緣層與該接墊上之凹形表 間隙與該缺口之内外。An insulating layer is formed on the outer circuit layer, the insulating layer has a front storm road. The ground pad is smaller than the joint to expose a portion of the concave surface, and the concave surface The periphery is covered by the insulating layer, and a gap is formed between the lower surface of the insulating layer and the concave surface. The substrate of claim 18, further comprising a layer of a bonding material formed on the insulating layer and the concave surface of the pad and the inside and outside of the notch. 10 20. 如申請專利範圍第18項所述之基板，其更包含在 钮刻步驟後於該姓刻區進行一表面處理步驟。 21. 如申請專利範圍第18項所述之基板，其中該蚀刻 區為底部中央平面，以及一傾斜之周邊。 22· —種BGA封裝，包含： 一基材； 一第一外部電路層，形成於該基材之第一表面上，其 包含打線接合用的第一接墊，且該第一接塾係為平面；-斤一第二外部電路層，形成於該基材相對該第一表面之 -第二表面上，其包含一經蝕刻而具有凹形表面的第二接 20 一絕緣層，形成於該第一與該第二外部電路層上方， 其具有開口暴露該第一與該第二接塾，而暴露該二二接塾 之開口直徑係小於該第二接墊，以顯露部分該凹形表面， 且該凹形表面之周圍被該絕緣層，並於該絕緣層之下表面 及該凹形表面之間產生一間隙； -晶片’嵌合於該第-外部電路層上方的該絕緣層 21 1301649 G -' ..·-_.r. 上，並打線接合至該第一接墊；以及 一連接材料，形成於間隙中，以及形成於該第二外部 電路層上方的該絕緣層之該缺口内外。 23.如申請專利範圍第22項所述之BGA封裝，其更包 5 含在餘刻步驟後於該姓刻區進行一表面處理步驟。 24·如申請專利範圍第22項所述之封裝，其中該 餘刻區為底部中央平面，以及一傾斜之周邊。10. The substrate of claim 18, further comprising performing a surface treatment step in the surname area after the buttoning step. 21. The substrate of claim 18, wherein the etched region is a bottom central plane and a sloped perimeter. A BGA package comprising: a substrate; a first external circuit layer formed on the first surface of the substrate, comprising a first pad for wire bonding, and the first interface is a second external circuit layer formed on the second surface of the substrate opposite to the first surface, comprising a second contact 20-insulating layer having a concave surface after etching, formed in the plane Above the second outer circuit layer, having an opening exposing the first and second contacts, and exposing the two openings to a diameter smaller than the second pad to expose a portion of the concave surface, And the periphery of the concave surface is surrounded by the insulating layer, and a gap is formed between the lower surface of the insulating layer and the concave surface; the insulating layer 21 1301649 is mounted on the first external circuit layer. G-'..--.r., and wire bonding to the first pad; and a connecting material formed in the gap, and the gap of the insulating layer formed over the second outer circuit layer inside and outside. 23. The BGA package of claim 22, further comprising a surface treatment step in the surname area after the remaining step. 24. The package of claim 22, wherein the residual region is a bottom central plane and a sloped perimeter. 22 130164922 1301649 1301649 」.f …y...j ί /////// / /~Ζ ////////////1301649 ”.f ...y...j ί /////// / /~Ζ ///////////// 圖8GFigure 8G i- 圖8HI- Figure 8H 圖81 1301649Figure 81 1301649 圖8K 1301649Figure 8K 1301649 13016491301649 圖80 · 1301649Figure 80 · 1301649 圖8PFigure 8P
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