1292383 九、發明說明： 【發明所屬之技術領域】 本發明提供一種晶圓包裝，尤指一種避免污染以及節省空間之 晶圓包裝。 【先前技術】 積體電路(integrated circuits)從製作至完成，至少包含有數十個 φ 繁複的半導體製程步驟。而由於目前半導體業界的分工精細，在 半導體晶圓(wafer)表面製作電晶體等元件的製程與後續封裝 (package)通常由不同廠商或不同地區的廠區來進行。所以在製作 廠商欲出貨至封裝廠商時，製作完成的晶圓常必須成批收納於匣 盒或晶圓搬運裝置中，再運送至封裝廠。 凊參考第1 ®，第1圖為習知晶圓包裝1〇之示意圖。晶圓包 裝10包含有一匣盒12用來容置複數個晶圓14，並利用靜電紙16 籲置於鄰近晶圓14之間來隔開各晶圓14，以防止各晶圓14互相接 觸磨擦以及運輸過程中因晃動與碰撞而造成晶圓14損壞，另外， 習知技術會再使職數贿、纟帛18平均配置紐盒12 以及上蓋U下方，用以保護晶圓14避免其触盒12之間的接觸 或碰撞損壞。-般而言，其操作步驟係先將海錦18放置於心η 之底層^上方，再依序放置-靜電紙16以及一晶圓Μ於海；J Μ 上，接者再重複放置另-靜電紙16於晶圓14上以及另—晶圓Μ 於靜電紙16上，在重複放置數十片晶圓Η後，然後於最上層之 1292383 晶圓14上再覆蓋靜電紙16以及海綿18後蓋上匣盒12之上蓋 以完成一批晶圓包裝10。最後，再將一批批晶圓包裝1〇放入大紙 箱或小紙箱中，以便運輸。但是，由於靜電紙16係直接與晶圓14 之表面接觸，故容易有污染或刮傷晶圓14表面的危險與困擾，因 此發展出其他晶圓包裝方法。 請參考第2圖，第2圖為另一習知晶圓包裝3〇之示意圖。如 φ 苐2圖所示’美國專利公開號US 6,581,264係揭露一種前開式運 送盒(front opening shipping box, FOSB)之晶圓包裝方式。f〇sb 晶 圓包裝30包含有一匣盒32，匣盒32之内部有複數個溝槽支柱36， 且各相鄰溝槽支柱36會形成一溝槽(圖未示）。接著將晶圓34放置 於溝槽中，並利用溝槽支柱36將各晶圓34固定並隔開，其中匿 盒32是由許多結構所組成，在此未詳細說明。如前所述，為了避 免靜電紙污染，因此業界發展出FOSB之晶圓包裝30,但目前12 鲁 忖晶圓若利用FOSB之晶圓包裝30來運送，反而不利成本，因為 溝槽支柱36以及匣盒32之結構，反而使一批晶圓包裝30的體積 非常龐大，造成一個紙箱所能容納之晶圓包裝30減少，因而提高 空運成本，所以為解決污染以及體積龐大等問題，故業界又發展 另一晶圓包裝來解決。 請參考第3圖，第3圖為另一習知晶圓包裝50之示意圖。如 第3圖所示，美國專利公開號us 2004/0149623之晶圓包裂5〇包 含有一匣盒52，並於匣盒52内依序放置一泡棉58、一墊片56用 -1292383 来區隔各晶圓54，其放罟 ^ 、方式類似於第1圖之晶圓14與靜電紙 6的方法。其中，墊片56之結構包含有一上表面6G、一第一凹 6:二及一第二凹處64’當晶圓54放置於墊片％之第一凹處 、、⑹，日刪上表面6G與第—凹處62之階梯結構來蚊晶圓54 P 曰圓54,月動，而第二凹處64則是用來容置晶圓％之錫焊 :、66,其他阳圓構件，其深度可轉於或大於晶圓％之錫焊球 6的高度。軸晶圓54之料球66或其他晶嶋件沒有處碰到 片56 ’但疋晶圓54之上表面仍然直接接觸到塾片％，另外整 片56需要上表面60與第一凹處幻之階梯結構來固定晶圓54，而 且又需要第二喊64來容置晶圓54之錫焊球的 ，如果晶圓54 ^固定於第一凹處62與第二凹處64則會導致晶圓％破片。而且 a曰圓包褒50利用塾片56來防止晶圓54之底部的錫焊球的或其 他晶圓構件因接觸而損壞之問題，但塾片56的第—凹處62卻會 導致晶圓54取出時’卡住晶® 54而造成作業的困擾。 【發明内容】 因此本發明之主要目的在於提供一種避免污染以及節省空間 之晶圓包裝，以解決上述習知的問題。 根據本發明之申請專利範圍，係揭露一種晶圓包裝包含有一匣 盒、至少二海綿放置於匣盒内之底層及上蓋、至少二中空支撐墊 片置於海綿之間以及複數個晶圓，其中各晶圓設置於相鄰二中空 支撐墊片之間，且各晶圓之邊界非完整晶粒區與相鄰二中空支標 1292383 墊片接觸。 由於本發明採用中空支撐墊片設置於晶圓包裝中各晶圓間，以 分離堆疊之各晶圓，可以避免習知技術中之使用靜電紙直接接觸 各晶圓造成晶圓表面污染或刮傷等問題，而且還可減少習知技術 中使用FOSB包裝時，因FOSB體積龐大造成空運成本太高等問 題，更進一步降低運送時，因不小心碰撞造成晶圓損壞之問題， 來減少成本。 【實施方式】 相較於習知晶圓包裝，本發明之晶圓包裝利用中空支撐墊片來 分離包裝晶圓具有免污染以及省空間等優點。 請參考第4圖，第4圖為本發明晶圓包裝7〇之示意圖。本發 明之晶圓包裝7G包含有-E盒72、至少二海綿78、以及複數個 • 中空支撐塾片76，用以容置複數個晶圓74。首先，將至少一海綿 78放置於匣盒72之底層80上，再依序放置至少一 以及_節4，獅㈣上方，趣序m 塾片76與晶圓74’迨放置共二十五片晶圓74後，覆蓋上至少一 中空支樓墊片76以及至少-_ 78，接著再蓋上£盒？！之上蓋 82，此稱之為-批關包裝7G ’然後將—批批晶圓包㈣放置於 紙箱（圖未示）中，以便進行運輸。其中，中空支撐塾片％盘晶 圓74之接觸僅在於晶圓74之邊界非完整晶粒區與中空支撐墊片 1292383 == 於中空支撐塾片76僅與晶圓74之邊界接觸，因此 而〜晶粒區域不會受附空域塾片接觸污染或刮傷晶 ^執t危險。另外’若擔心晶圓74產生靜電，則可以在各中空 牙76與各晶圓74之下表面間選擇性放置—靜電紙（圖未 不），來避免靜電產生。1292383 IX. Description of the Invention: [Technical Field] The present invention provides a wafer package, and more particularly, a wafer package that avoids contamination and saves space. [Prior Art] From the fabrication to the completion of integrated circuits, there are at least tens of φ complicated semiconductor process steps. Due to the current fine division of labor in the semiconductor industry, the manufacturing process and subsequent packaging of components such as transistors on the surface of semiconductor wafers are usually carried out by different manufacturers or factories in different regions. Therefore, when the manufacturer wants to ship to the package manufacturer, the completed wafers must often be stored in bulk in a cassette or wafer handling device and transported to the packaging factory.凊 Refer to Chapter 1 and Figure 1 is a schematic diagram of a conventional wafer package. The wafer package 10 includes a cassette 12 for accommodating a plurality of wafers 14 and is placed between adjacent wafers 14 by electrostatic paper 16 to separate the wafers 14 to prevent the wafers 14 from contacting each other. And the wafer 14 is damaged due to shaking and collision during transportation. In addition, the prior art will make the job bribe, the 纟帛18 average configuration button 12 and the upper cover U to protect the wafer 14 from the touch box. 12 contact or collision damage. In general, the operation steps are to place the Haijin 18 on top of the bottom layer of the heart η, and then place it in sequence - the electrostatic paper 16 and a wafer are placed on the sea; on the J Μ, the receiver is repeatedly placed again - The electrostatic paper 16 is placed on the wafer 14 and the other wafer is placed on the electrostatic paper 16. After the tens of wafer rafts are repeatedly placed, and then the electrostatic paper 16 and the sponge 18 are overlaid on the uppermost 1292383 wafer 14. The upper cover of the cassette 12 is covered to complete a batch of wafer packages 10. Finally, a batch of batch wafer packages are placed in a large or small carton for transport. However, since the electrostatic paper 16 is directly in contact with the surface of the wafer 14, there is a risk of contamination or scratching of the surface of the wafer 14, and other wafer packaging methods have been developed. Please refer to FIG. 2, which is a schematic diagram of another conventional wafer package. U.S. Patent Publication No. 6,581,264, the entire disclosure of which is incorporated herein by reference. The f〇sb wafer package 30 includes a cassette 32 having a plurality of trench posts 36 therein, and adjacent trench posts 36 define a trench (not shown). Wafer 34 is then placed in the trenches and wafer 34 is secured and separated by trench posts 36, which are comprised of a number of structures, not described in detail herein. As mentioned above, in order to avoid electrostatic paper contamination, the industry has developed FOSB's wafer packaging 30, but currently 12 reckless wafers are shipped using FOSB's wafer package 30, which is not cost effective because of the trench pillars 36 and The structure of the cassette 32, on the other hand, makes the volume of a batch of wafer packages 30 very large, resulting in a reduction in the number of wafer packages 30 that can be accommodated in one carton, thereby increasing the cost of air transportation, so that in order to solve the problems of pollution and bulkiness, the industry has Develop another wafer package to solve. Please refer to FIG. 3, which is a schematic diagram of another conventional wafer package 50. As shown in FIG. 3, the wafer cladding 5 of US Patent Publication No. 2004/0149623 includes a cassette 52, and a foam 58 and a spacer 56 are sequentially placed in the cassette 52 with -1292383. Each of the wafers 54 is spaced apart from the wafer 14 and the electrostatic paper 6 in a manner similar to that of FIG. The structure of the spacer 56 includes an upper surface 6G, a first recess 6: two and a second recess 64'. When the wafer 54 is placed in the first recess of the spacer, (6), the surface is deleted. 6G and the recessed portion 62 of the stepped structure of the mosquito wafer 54 P 曰 round 54, monthly movement, and the second recess 64 is used to accommodate the wafer% of the solder: 66, other male members, The depth can be turned to or greater than the height of the solder balls 6 of the wafer %. The ball 66 or other wafer member of the shaft wafer 54 does not touch the sheet 56' but the upper surface of the wafer 54 is still in direct contact with the wafer %, and the entire sheet 56 requires the upper surface 60 and the first recess. The stepped structure is used to fix the wafer 54, and a second shunt 64 is needed to accommodate the solder balls of the wafer 54. If the wafer 54 is fixed to the first recess 62 and the second recess 64, the crystal is caused. Round % fragment. Moreover, the crucible 50 utilizes the cymbal 56 to prevent the solder balls or other wafer members at the bottom of the wafer 54 from being damaged by contact, but the first recess 62 of the cymbal 56 causes the wafer 54 When you take it out, you get stuck in Crystal® 54 and cause troubles in your work. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a wafer package that avoids contamination and saves space to solve the above-mentioned problems. According to the patent application scope of the present invention, a wafer package includes a cassette, at least two sponges placed in the bottom layer and the upper cover of the cassette, at least two hollow support spacers disposed between the sponges, and a plurality of wafers, wherein Each wafer is disposed between adjacent two hollow support pads, and the non-complete grain regions of the boundaries of the respective wafers are in contact with the adjacent two hollow pins 1292383. Since the present invention uses a hollow support spacer disposed between the wafers in the wafer package to separate the stacked wafers, it can avoid the surface contamination or scratch of the wafer caused by the direct contact of the electrostatic paper with the electrostatic paper in the prior art. Such problems can also reduce the problem of high cost of air transportation due to the large volume of FOSB when using FOSB packaging in the prior art, and further reduce the problem of wafer damage caused by accidental collision during transportation, thereby reducing the cost. [Embodiment] Compared with the conventional wafer package, the wafer package of the present invention utilizes a hollow support spacer to separate the package wafer from the advantages of pollution-free and space saving. Please refer to FIG. 4, which is a schematic diagram of a wafer package of the present invention. The wafer package 7G of the present invention comprises an -E box 72, at least two sponges 78, and a plurality of hollow support cymbals 76 for accommodating a plurality of wafers 74. First, at least one sponge 78 is placed on the bottom layer 80 of the cassette 72, and at least one and _ section 4 are placed in sequence, above the lion (four), and the fun m 塾 piece 76 and the wafer 74 迨 are placed in a total of twenty-five pieces. After the wafer 74, it is covered with at least one hollow branch gasket 76 and at least -_78, and then covered with a box? ! The upper cover 82, which is referred to as a "batch package 7G", is then placed in a carton (not shown) for transport. The hollow support wafer % disk wafer 74 is only in contact with the boundary of the wafer 74 and the hollow support spacer 1292383 == the hollow support blade 76 is only in contact with the boundary of the wafer 74, thus ~ The grain area will not be contaminated by contact with the airborne slabs or scratching the crystal. Further, if it is feared that the wafer 74 generates static electricity, it is possible to selectively place an electrostatic paper (not shown) between the hollow teeth 76 and the lower surface of each wafer 74 to avoid static electricity generation.
第5圖至第1G圖，第5圖至第⑴圖為本發明中 j按墊片76之形狀示意圖。本發明之中空支樓墊片76可以為 ^祿所構成，例如環_像—個〇型環⑼_、C 片、=圓形環狀抑或至少二弧形墊片所構成之中空支撐塾片 5圖至及第7圖所示，環狀中空支撐墊片76之_周9〇 =卜Γ/2可以其中之一内外圓周為齒狀結構、二内外圓周皆 2狀4或者二内外圓周皆為平滑之結構。或者如第8圖所示， ^撐墊片76為- C字形墊片’其c字形中空支擇墊片％之 八:大於180度。上述墊片76之形狀，以能使晶圓重量均勻 /刀布的形狀為佳’在此僅用以說明本發明而不限於此。盆中 ΓΓ=6之撕喻卿、導爾、或是磁性材料 ^而其殊度大於1毫米㈣，且寬度大於3毫米㈣。此外， 一工支撐藝片76甚至可為如第9圖至第1()圖所示之由二弧形或 二弧形的磁性材料所構成。值得注意的是中空支料片％之妒 ^以為上述形狀之混合構成，但中空支_ %之形受 上述所列職之限f本發财蚊雜片柯為—環 片，但其上設有與晶圓74之邊界非完整晶粒區相接觸之至少 1292383 • Λ起接觸部分。 由於本發明利用中空支撐墊片76來分隔各晶圓74，且中空支 撐墊片76並沒有和晶圓74之完整晶粒區相接觸，因此不會因中 空支撐墊片76與晶圓74相接觸而造成污染或刮傷晶圓74表面之 危險產生，另外因為本發明之晶圓包裝70採用晶圓74堆疊之方 式放置，且利用匣盒72之内壁來固定並抵擋晶圓74之滑動，所 I 以中空支撐塾片76之大小與晶圓74之大小相同，可以使用現有 設計之匣盒72並不需要增加匣盒之寬度或高度，可以有效減少一 批晶圓包裝70之體積，並可使一批批晶圓放入紙箱之數量不變或 增加，進一步降低空運成本。 相較於習知技術之晶圓包裝，本發明採用中空支撐藝片於晶圓 包裝内可良好應用於12吋晶圓及薄晶圓之運送，不但可以避免靜 電紙直接接觸晶圓而造成晶圓污染或刮傷晶圓表面，另外，因為 1直接採用中空支撐墊片來隔開各晶圓故可以減少習知F〇SB之晶 圓包裝體積龐大問題，也能避免習知晶圓包裝之墊片使用，不但 沒有減少體積龐大問題，也沒有解決晶圓污染、磨損等問題，本 發明之堆疊晶圓包裝不但改善上述問題，更進一步降低空運成 本，減少晶圓碰撞產生不良率。 以上所述僅為本發明之較佳實補，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 1292383 • 1【圖式簡單說明】 第1圖至第3圖為習知晶圓包裝之示意圖。 第4圖為本發明晶圓包裝之示意圖。 第5圖至第10圖為中空支撐墊片之形狀示意圖。5 to 1G, FIGS. 5 to (1) are schematic views showing the shape of the spacer 76 according to the present invention. The hollow support spacer 76 of the present invention may be composed of a ring, such as a ring-shaped ring (9), a C-piece, a circular ring or at least two curved spacers. As shown in Fig. 7 and Fig. 7, the annular hollow support spacer 76 may be one of the inner and outer circumferences having a tooth-like structure, the inner and outer circumferences being two-shaped four or two inner and outer circumferences. Smooth structure. Alternatively, as shown in Fig. 8, the spacer 76 is a -C-shaped spacer', and the c-shaped hollow spacer spacer is eight: more than 180 degrees. The shape of the spacer 76 described above is such that the wafer weight is uniform/the shape of the blade is preferred. The present invention is merely illustrative of the present invention and is not limited thereto. In the basin, ΓΓ=6 is a tortoise, a guide, or a magnetic material, and its degree is greater than 1 mm (four), and the width is greater than 3 mm (four). Further, the work support piece 76 may even be composed of a two-arc or two-arc magnetic material as shown in Figs. 9 to 1(). It is worth noting that the hollow part of the hollow piece is composed of the above-mentioned shapes, but the shape of the hollow branch is limited by the above-mentioned list of duties, and the hair of the mosquito is a ring piece, but it is set up. There is at least 1292383 in contact with the non-complete grain region of the boundary of wafer 74. • Pick up the contact portion. Since the present invention utilizes the hollow support spacers 76 to separate the wafers 74, and the hollow support spacers 76 are not in contact with the complete die regions of the wafer 74, the hollow support spacers 76 are not aligned with the wafers 74. The risk of contamination or scratching the surface of the wafer 74 by contact, and because the wafer package 70 of the present invention is placed in a stack of wafers 74, and the inner wall of the cassette 72 is used to secure and resist the sliding of the wafer 74, The size of the hollow support cymbal 76 is the same as the size of the wafer 74, and the existing design of the cassette 72 can be used without increasing the width or height of the cassette, which can effectively reduce the volume of a batch of wafer packages 70, and The number of batches of wafers can be put into the carton unchanged or increased, further reducing the cost of air transportation. Compared with the wafer packaging of the prior art, the invention adopts a hollow supporting art piece to be well applied to the transport of 12-inch wafers and thin wafers in the wafer package, which can prevent the electrostatic paper from directly contacting the wafer and causing the crystal. Circular contamination or scratching of the wafer surface. In addition, because the hollow support spacers are used to separate the wafers, the conventional F〇SB wafer packaging volume can be reduced, and the conventional wafer packaging gasket can be avoided. The use of the package not only does not reduce the bulkiness problem, but also solves the problems of wafer contamination, wear and the like. The stacked wafer package of the present invention not only improves the above problems, but also further reduces the air transportation cost and reduces the defect rate of wafer collision. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. 1292383 • 1 [Simple description of the drawings] Figures 1 to 3 are schematic diagrams of conventional wafer packaging. Figure 4 is a schematic view of a wafer package of the present invention. Figures 5 to 10 are schematic views of the shape of the hollow support spacer.
【主要元件符號說明】 10、30、50、70 晶圓包裝 12、32、52、72 匣盒 14、34、54、74 晶圓 16 靜電紙 18、58、78 海綿 20、80 底層 22、82 上蓋 36 溝槽支柱 56 墊片 60 上表面 62 第一凹處 64 第二凹處 66 錫焊球 76 中空支撐墊片 90 内圓周 92 外圓周 94 角度 11[Major component symbol description] 10, 30, 50, 70 Wafer packaging 12, 32, 52, 72 14 box 14, 34, 54, 74 wafer 16 electrostatic paper 18, 58, 78 sponge 20, 80 bottom layer 22, 82 Upper cover 36 grooved post 56 spacer 60 upper surface 62 first recess 64 second recess 66 solder ball 76 hollow support spacer 90 inner circumference 92 outer circumference 94 angle 11