1281257 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種鰭式場效電晶體（Fin Field_effect 的油⑽；ΜΕΤ)，且特別是有關於—種類平面互補全 氧半導體，與-種具有加強驅動電流與抑制短通道效库特 性’並位於塊㈣材上之_式場效電晶體的電晶體元件 (被稱為塊狀H式場效電晶體或塊狀⑦材上覆_式場效電 晶體），及其製造方法。 【先前技術】 -般而言，不論是塊㈣材或絕緣層上㈣結構上的 電晶體’各個世代間之互補金氧半導體積體電路的效能強 化通常是藉由讓電晶體的閘極長度變短，並讓其閘極氧化 層的厚度變薄而達成。這通常被稱為金氧半導體電晶體的 縮放（Scaling)。 應用於積體電路元件之金氧半導體場效電晶體 (Metal-Oxide-Semiconductor-Field-Effect-transistors ; MOSFETs)-般具有源極、沒極及具有閘極氧化層之間極電 極。隨著閘極氧化層的厚度變薄，電晶體即可以較低的電 壓驅動，進而避免電崩潰及穿透閘極氧化層之漏電流。 此外，Ik著製造於塊狀石夕材上之互補金氧半導體電晶 體之通道長度已經縮小至l〇0nm以下，應用習知的互補金 氧半導體電晶體結構將使得通道區、接合區及閘介電層產 生漏電流，此將使電晶體的效能下降。特別是在於互補金 1281257 氧半導體元件之源極與汲極間的交互作用，這種交互作用 「般會導致臨界電壓下降，並造成不佳的次臨界電壓震 盈’進而讓電晶體無論在開啟或關閉狀態的閘極控制能力 下降。這種現象通常被稱為短通道效應。 為了克服製造互補金氧半導體於塊狀矽材上的缺點， 互補金氧半導體現在也可製造於絕緣層上覆矽結構上。 在產生佈局的過程中，金氧半導體場效電晶體通常會 定義出-個梦主動區，此石夕主動區中穿插有單—或多條由 ^晶石夕組成的線圖案。此外1主動區通常是_组成的 一維平面層。 於絕緣層上覆石夕結構上的金氧半導體場效電晶體，其 凡件主動區下方通常具有絕緣層（通常是氧切，並被稱為 埋入氧化物層）；此與習知的塊狀金氧半導體場效電晶體不 同，習知的塊狀金氧半導體場效電晶體係直接製造於石夕基 口此，、主動區下方係為梦材質。由於在絕緣層上覆 夕、、σ構上的金乳半導體場效電晶體具有較於塊狀梦材上的 互補金氧半導體更小的次臨界電壓震|(換言之，較佳關閉 1 丈能）’因此在絕緣層上㈣結構上的金氧半導體場效電晶 體將具有較快的元件速度。此外，由於通道區及源/汲極下 之埋入氧化物層的阻擔，因此在絕緣層上覆石夕結構上的全 乳半導體場效電晶體的源極與汲極間之電轉合將降低。铁 而隨著70件尺寸的縮小，這種理想情況也變得日益艱難； 由於源極與祕間的尺寸料，源/祕與料區的作用將 會增加，因此使得控㈣極的能力下降，並使短通道效應 1281257 增強。 如第1圖及第2圖所繪示之位於絕緣層上覆矽結構 上的鰭式場效電晶體，其具有薄通道區或鰭狀區域於絕緣 =上覆矽結構上。鰭12係由矽所製成，並形成於絕緣層上 覆矽結構10上，此絕緣層上覆矽結構1〇具有埋入氧化物 層16及矽基材14，上述之鰭12係垂直地延展於基材的平 面上。鰭沿著垂直方向的兩端（連同頂平面部分）係可應用來 形成％效電晶體的通道區。這些具有鰭狀結構的場效電晶 體也被稱為鰭式場效電晶體（通常也被稱為雙閘鰭式場效 電晶體或三閘電晶體）。許多有關於在絕緣層上覆矽結構上 製k 式％效電晶體的貫施例被揭露在美國專利6 j 13 8〇2 B 1號，請參閱之。 位於絕緣層上覆矽結構10上之鰭式場效電晶體具有至 少一垂直走向之鰭12以及包裹或覆蓋鰭兩側及頂面之自動 對準閘極18。此垂直走向的薄鰭可導致眾所周知的薄體效 應（thin-body effect)，例如增強遷移率及反轉體積。由於閘 極18係完全或幾乎完全包裹著鰭12或通道區，其將提供 絕佳之閘極開關控制能力，並同時具有已知薄體效應所具 備的優點。此外，短通道效應也將因元件主動區下之埋入 氧化物層削除了源極與汲極間的靜電耦合效應而改善。 如第3圖所繪示，較理想的狀況為藉由多個彼此平行 之縛21與單一共同閘極23來構成具有較寬通道區之電晶 體19。 不論是第1圖、第2A_2E圖或第3圖所繪示之互補金 1281257 氧半導體場效電晶體及絕緣層上㈣結構上㈣式場效電 曰曰體均已e λ其具有較於塊狀;^材上的平面互補金氧半導 體更好的效能’特別是在於抑制短通道效應及降低漏電流 方面的功效。 於、、、巴緣層上覆石夕結構上製造籍式場效電晶體的習知方 法與在塊狀矽材上製造平面互補金氧半導體的方法類似。 第1圖料示位於絕緣層上覆秒結構上的鰭式場效電晶 體，其具有由石夕製成的鰭。此續12的厚度（或寬度）界係約 0 nm並可藉由些已知的技術来製造，例如電子束曝光。 身又而a，每一個由矽所製成之鰭的厚度w係介於⑺ 廳4〇㈣之間。此外，鰭的高度Η係介於3(M00 nm 之間。㈣的高寬比值或外觀比值係介於W之間，此數 值係咼於一般平面互補金氧半導體。 -般來說’所有鰭的高度及厚度（或寬度）均應一致。而 較寬的電晶體可藉由多個彼此平行之韓與單-共同閘極來 構成（如第3圖所纷示）。 如第2A-2E所纷示，於絕緣層上覆發結構上製造趙式 場效電晶體之方法與習知在塊㈣材上製造平面互補金氧 半導體的方法類似。 第2A-2E圖係纷示於絕緣層上覆石夕結構上製造轉式 效電晶體的流程。 第2A圖係繪不製造鰭的部分步驟，其包含圖案化、蝕 ，及臨界電壓摻雜製程而形成。由碎所製成的，鰭12係首先 错由良好的曝光（例如電子束曝光），然後再對石夕進行姓刻， 1281257 並選擇性地實施臨界電壓摻雜製程。如第2a圖所繪示，於 =胃夕進行蝕刻後可選擇性地實施臨界電壓植入24，此臨界 電I植入24係可根據組成閘極的材料來調整臨界電壓。 與在塊狀石夕材上製造平面互補金氧半導體不同的是， 由…巴緣層上覆石夕結構中之埋入氧化物層已經提供了良好 的絕緣，故形成淺溝隔離（Shallow Trench Is〇lati〇n ; 的製程也就不再需要。 如第2B圖所繪示’於圖案化製程後，鰭㈣表面將 成間極氧化層。接著在問極氧化層形成 ==積於…，並圖案化為閘極18，此間極 =體4㈣材料較佳包含多晶石夕、織氮化鈦其中至少一 。閘極最好是利用㈣製程來形成對準良好 鰭的兩側壁之閘極。藉由上 、 7丄於 約為每一鰭之靜纟壬士 之通道區的寬度 S回兩倍，其中鰭咼係恰為於絕緣層上覆 …構上之鰭式場效電晶體的矽層厚度。 兀件的臨界電壓可藉由使用不同 =用耐火材料、化合物(如氮化鈦)或合金 的載=二界電壓係可由閘極材料及開啟狀態物 =體，、度來決定，其中的機制為公知的知識，在此不再 的植1二圖示用以形成輕換雜淡極之具有選擇能力 的植入m針對基材之選定表面實 2二以提供均勾的輕換雜沒極。於第2C圖中所4= 10 1281257 :弟2D圖所繪示，間隙壁3〇係利用沉積及化 衣知(如回钮技巧)而形成於閘極18的側壁及韓 於 閘極）上。此間隙壁的材料一般為二氧化石夕或氮化/、。 於間隙壁形成後，籍的含石夕部分將暴露出來，以利用 罩幕來進行重劑量之N型或P型摻雜物的植人，進而 源極及汲極(如第i圖所繪示之源極22與汲極25)。’ 如第2E圖所緣示，薄薄的一層金屬石夕化物32將 習知的自動對準金屬魏技術來形成。此金屬魏製㈣ :源極及汲極消耗少量的矽。可行的金屬矽化物包含矽化 、、及石夕化把，然在此並不限於習知常用的金屬#化物 如矽化鈦及矽化鈷。 。或者製造者亦可實施另外一種具選擇性的導體沉積製 :::以取代第2E圖所繪示之金屬矽化物32，此導體沉積 衣程係可為具選擇性的金屬沉積、多晶矽沉積或單晶矽沉 絕緣層上覆石夕技術進一步地改善電路的速度，並降低 電路的操作電壓。埋人氧化物層不_是降㈣/汲極接合 品人電#卩加速其操作速度，㈤日夺也消除源/汲極間的電 一在塊狀矽材上的互補金氧半導體中，源/汲極間的電 麵口將使得電晶體的效能降低（例如導致臨界電壓下降、次 臣品界電壓震|較差及漏電流變高的短通道效應）。 於、、巴緣層上覆石夕結構上製造鰭式場效電晶體的技術一 1281257 :,疋彳支於平面互補金氧半導體，然於絕緣層上覆石夕結構上 衣仏具有類平面表面之鰭式場效電晶體將遭遇以下數個嚴 峻的挑硪，包含：如何提供一個適合的絕緣層上覆矽基材； 如何實施-個良好的微影製程；如何實施—個具高度土外觀 比：的蝕刻製程；如何利用大傾角植入製程來產生一個均 勻摻雜的源/汲極及輕摻雜汲極。事實上，鰭式場效電晶體 之，極與;及極均位於通道區的最低處上方，因此鰭式場效1281257 IX. Description of the Invention: [Technical Field] The present invention relates to a fin field effect transistor (Fin Field_effect oil (10); ΜΕΤ), and in particular to a type-plane complementary oxy-semiconductor, A transistor element with a reinforced field-effect transistor that enhances the drive current and suppresses the short-channel effect library characteristics and is located on the block (four) material (referred to as a block-shaped H-type field effect transistor or a block-shaped 7-material overlying _ field effect battery) Crystal), and its method of manufacture. [Prior Art] - Generally speaking, whether it is a block (four) material or an insulating layer (four) structure of the transistor 'the performance enhancement of the complementary MOS semiconductor integrated circuit between generations is usually by letting the gate length of the transistor It is shortened and achieved by thinning the thickness of the gate oxide layer. This is commonly referred to as Scaling of MOS transistors. Metal-Oxide-Semiconductor-Field-Effect-transistors (MOSFETs) applied to integrated circuit components generally have a source, a finite electrode, and a gate electrode having a gate oxide layer. As the thickness of the gate oxide layer becomes thinner, the transistor can be driven with a lower voltage, thereby avoiding electrical breakdown and leakage current through the gate oxide layer. In addition, the channel length of the complementary MOS semiconductor transistor fabricated on the block-shaped stone material has been reduced to below 10 nm, and the conventional complementary MOS transistor crystal structure will be used to make the channel region, the junction region and the gate. The dielectric layer generates a leakage current which will degrade the performance of the transistor. In particular, it is the interaction between the source and the drain of the complementary gold 1281257 oxygen semiconductor device. This interaction "will cause the threshold voltage to drop and cause a sub-critical voltage shock", which in turn allows the transistor to be turned on. The gate control capability of the off state is reduced. This phenomenon is often referred to as the short channel effect. To overcome the shortcomings of manufacturing complementary MOS on bulk rams, complementary MOS can now also be fabricated over the insulating layer. In the process of generating the layout, the MOS field effect transistor usually defines a dream active area, and the stone eve active area is interspersed with a single-or multiple line pattern composed of crystallization. In addition, the active region is usually a one-dimensional planar layer composed of _. The MOS field-effect transistor on the overlying structure of the insulating layer usually has an insulating layer under the active region (usually oxygen-cut, and It is called buried oxide layer; this is different from the conventional bulk MOS field effect transistor, and the conventional bulk MOS field effect crystal system is directly manufactured in Shixijikou. , below the active area is a dream material. Because the gold-emulsion semiconductor field-effect transistor on the insulating layer and the σ structure has a smaller sub-threshold voltage than the complementary MOS semiconductor on the block-like material. (In other words, it is better to turn off 1 ft.) 'Therefore, the MOS field effect transistor on the (4) structure on the insulating layer will have a faster component speed. In addition, due to the channel region and the source/drain buried The resistance of the oxide layer, so the electrical connection between the source and the drain of the all-emulsion semiconductor field effect transistor on the overlying structure of the insulating layer will be reduced. Iron is reduced with the size of 70 pieces. The ideal situation has also become increasingly difficult; due to the size of the source and the secret, the role of the source/secret and the material zone will increase, thus reducing the ability of the control (four) pole and enhancing the short channel effect of 1281257. FIG. 2 and the fin field effect transistor on the insulating layer on the insulating layer, which has a thin channel region or a fin region on the insulation=overlying structure. The fin 12 is made of tantalum. And formed on the insulating layer on the overlying structure 10, The edge layer overlying structure 1 has a buried oxide layer 16 and a germanium substrate 14, and the fins 12 are vertically extended on the plane of the substrate. Both ends of the fins along the vertical direction (along with the top planar portion) It can be applied to form the channel region of the % effect transistor. These field-effect transistors with fin structure are also called fin field effect transistors (also commonly referred to as double-gate field effect transistors or triple gate transistors). A number of examples of a k-type %-effect transistor on a germanium-on-insulator structure are disclosed in U.S. Patent No. 6 j 13 8〇2 B1, which is incorporated herein by reference. The upper fin field effect transistor has at least one vertically oriented fin 12 and an auto-aligned gate 18 enclosing or covering both sides and a top surface of the fin. This vertically oriented thin fin can lead to a well-known thin body effect (thin-body) Effect), such as enhanced mobility and reversed volume. Since the gate 18 completely or almost completely wraps the fin 12 or channel region, it will provide excellent gate switch control and at the same time have the advantages of known thin body effects. In addition, the short channel effect will also be improved by the electrostatic coupling effect between the source and the drain due to the buried oxide layer under the active region of the device. As shown in Fig. 3, it is desirable to form the electromorph 19 having a wider channel region by a plurality of parallel junctions 21 and a single common gate 23. Whether it is the complementary gold 1281257 oxy-semiconductor field effect transistor and the insulating layer on the first picture, the 2A_2E picture or the 3rd picture, the (4) field effect electric raft body has e λ which is more than the block shape. The better performance of the planar complementary MOS on the material 'is especially the effect of suppressing the short channel effect and reducing the leakage current. The conventional method of fabricating a field-effect field-effect transistor on the slab-on-the-ear structure of the glutinous layer is similar to the method of fabricating a planar complementary MOS on a bulk slab. Figure 1 shows a fin field effect transistor on the overlying structure of the insulating layer with fins made of Shi Xi. The thickness (or width) of this continuation 12 is about 0 nm and can be fabricated by known techniques, such as electron beam exposure. The body and the a, each of the fins made of enamel thickness w is between (7) Hall 4 (four). In addition, the height of the fins is between 3 (M00 nm. (4) The aspect ratio or appearance ratio is between W, which is equivalent to a general planar complementary MOS. - Generally speaking, all fins The height and thickness (or width) should be the same. A wider transistor can be formed by a plurality of parallel and single-common gates (as shown in Figure 3). For example, 2A-2E It has been shown that the method of fabricating a Zhao-type field effect transistor on the overlying structure of the insulating layer is similar to the conventional method of fabricating a planar complementary MOS on a block (four) material. The 2A-2E pattern is shown on the insulating layer. The process of manufacturing a transflective transistor on a rock-covered structure. Figure 2A depicts a partial step of not forming a fin, which is formed by patterning, etching, and a threshold voltage doping process. The 12 series is first mistakenly exposed by a good exposure (such as electron beam exposure), and then the stone is etched, 1281257 and selectively implemented a threshold voltage doping process. As shown in Fig. 2a, etching is performed on = stomach The threshold voltage implant 24 can be selectively implemented, and the critical electric I implant The 24 series can adjust the threshold voltage according to the material constituting the gate. Unlike the fabrication of the planar complementary MOS on the block stone, the buried oxide layer in the slab structure has been covered by the slab layer. Provides good insulation, so the formation of shallow trench isolation (Shallow Trench Is〇lati〇n ; process is no longer needed. As shown in Figure 2B 'after the patterning process, the surface of the fin (four) will be inter-polar oxidation Then, the formation of the extreme oxide layer is formed == and is patterned into the gate 18, and the material of the interlayer 4 is preferably composed of at least one of polycrystalline sia and titanium nitride. The gate is preferably The (4) process is used to form the gates of the two sidewalls of the well-aligned fins. The width S of the channel region of the quiet gentleman of each fin is twice as large as that of the upper fin, and the fins are exactly The thickness of the 矽 layer of the Fin-type field effect transistor is covered by the insulating layer. The threshold voltage of the element can be changed by using different = refractory material, compound (such as titanium nitride) or alloy load = two boundary voltage system Gate material and open state object = body, degree to determine the mechanism For the well-known knowledge, it is no longer necessary to form a light-changing dipole with a selective ability to implant m to select the surface of the substrate to provide a light-for-money 4= 10 1281257 in Figure 2C: The 2D diagram shows that the spacer 3 is formed on the sidewall of the gate 18 and the gate of the gate by means of deposition and chemical coating (such as the button technique). The material of the spacer is generally sulphur dioxide or nitriding /. After the formation of the spacer, the portion containing the lithium will be exposed to use the mask for the heavy dose of N-type or P-type doping. The implant of debris, and then the source and the drain (as shown in Figure i, source 22 and drain 25). As shown in Figure 2E, a thin layer of metal lithium 32 will be used. Know the automatic alignment of metal Wei technology to form. This metal system (4): the source and the bungee consume a small amount of bismuth. Feasible metal halides include deuterated, and shihuahua, but are not limited to conventionally used metals such as titanium telluride and cobalt telluride. . Alternatively, the manufacturer may implement another selective conductor deposition system:: in place of the metal halide 32 depicted in FIG. 2E, the conductor deposition coating system may be selective metal deposition, polycrystalline germanium deposition, or The overlying silicon-on-insulation insulating layer further improves the speed of the circuit and reduces the operating voltage of the circuit. The buried oxide layer is not _ is the (four) / 汲 接合 品 人 人 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩 卩The electrical interface between the source and the drain will reduce the efficiency of the transistor (for example, a short channel effect that causes a drop in the threshold voltage, a worse voltage drop in the secondary product, and a higher leakage current). A technique for fabricating a fin field effect transistor on the shoal layer of the yam and the shoal layer is 1281257: the yttrium is supported by a planar complementary MOS semiconductor, but the overlying slab of the insulating layer has a planar surface. Fin-type field-effect transistors will encounter several serious challenges, including: how to provide a suitable insulating layer on the substrate; how to implement a good lithography process; how to implement - a high soil appearance ratio: Etching process; how to use a large tilt implant process to produce a uniformly doped source/drain and lightly doped drain. In fact, the fin field effect transistor, the pole and the pole are located at the lowest point of the channel region, so the fin field effect
電曰B體之源極與汲極是屬於升高的源極與汲極，升高的源 極與汲極具有一些公知的優點，如降低源/汲之間穿透通道 區的電耦合。 卜士同其他金氧半導體電晶體一般，當鰭式場效 電晶體製造H緣層上覆石夕結構時將遭受浮體效應的影 響。當電晶體啟動或關閉時’浮動通道區將可依電壓的不 同而π有電荷’浮體效應也就因此而發生。浮體效應將使 電晶體行為的再現性較差。反之，由於塊狀碎材上的金氧The source and drain of the B-body are the elevated source and drain, and the raised source and drain have some known advantages, such as reducing the electrical coupling between the source/turn through the channel region. Generally, in the case of other MOS transistors, the fin field effect transistor will suffer from the effect of the floating body when it is fabricated on the H-edge layer. When the transistor is turned on or off, the floating channel region will vary depending on the voltage and the π-charged floating body effect will occur. The floating body effect will make the reproducibility of the transistor behavior poor. Conversely, due to the gold oxide on the blocky pieces
半導體電晶體，其通道區係電性連接基材，故浮體效 不會發生。 …因此’本發明之一方面就在於克服製造平面互補金氧 +導體及H式場效電晶體於絕緣層上㈣結構上所遭遇的 缺點。 【發明内容】 〃因此本發明-方面就是在提供—種結合類平面互補金 乳半導體及類鰭式場效電晶體之電晶體㈣的技術，並使 12 1281257 其製造於塊狀矽材上，用以克服目前平面互補金氧半導體 在元件尺寸縮小時所遭遇的短通道效應的問題，以及未來 於絕緣層上覆矽結構上製造鰭式場效電晶體所遭遇的浮體 效應的問題。 依照本發明之一較佳實施例，本發明之元件係提供具 有頂表面或頂壁，及至少一凹陷區(通常被稱為淺溝隔離區) 的半導體基材，其中凹陷區具有側壁及底部；部分之絕緣 層係形成於凹陷區（或淺溝隔離區）的底部中；以及位於凹陷 區之側壁的摻雜區。 依照本發明之另一較佳實施例，用以製造類平面電晶 體之電晶體元件的方法包含：首先提供一半導體基材丨以 及於邛刀深度之淺溝隔離區中填充氧化物（被稱為淺溝隔 離氧化物），如此即暴露出淺溝隔離區中含矽的側壁，並定 義了電晶體的通道區，此通道區將具有適當的臨界電壓摻 雜物。 或者在形成淺溝隔離區並填充氧化物後，接著係可 對半導體基材實施化學移除製程（例如反應離子蝕刻或化 學性的濕式蝕刻），以於主動區的兩邊上形成小型的含矽間 隙壁，以及蝕刻部分深度之位於淺溝隔離區中的氧化物， 以暴露出含矽的側壁，其中側壁及含矽間隙壁將定義出電 晶體的通道區，並將接受臨界電壓植入製程。 在本發明之另一實施例中，類平面電晶體之電晶體元 件其通道區係形成於兩淺溝隔離區間狹窄且未摻雜的含 矽區，如此將讓類平面電晶體的電晶體元件如同鰭式場2 13 1281257 電晶體-般具有薄體效應。升高的源極 的優點包含降低祕與汲 ^〜。構所提供 極通在塊”材的路徑上仍具有額外的 ^ 說，應用本發明將不會如絕緣層上 椹’L <疋 電晶體-般發生浮體效應。 夕-構上的鯖式場效 此外，若有需要得話，在本發明的又—實施例中，額In a semiconductor transistor, the channel region is electrically connected to the substrate, so that the floating body effect does not occur. Thus, one aspect of the present invention resides in overcoming the shortcomings encountered in fabricating planar complementary gold oxide + conductors and H-type field effect transistors on the insulating layer. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to providing a technique for combining a planar complementary gold-based semiconductor and a fin-like field effect transistor (4), and manufacturing 12 1281257 on a block-shaped coffin. In order to overcome the problem of the short channel effect encountered by the current planar complementary MOS semiconductor when the component size is reduced, and the floating body effect encountered in the fabrication of the fin field effect transistor on the overlying insulating structure on the insulating layer. In accordance with a preferred embodiment of the present invention, an element of the present invention provides a semiconductor substrate having a top or top wall and at least one recessed region (generally referred to as a shallow trench isolation region), wherein the recessed region has sidewalls and a bottom portion A portion of the insulating layer is formed in the bottom of the recessed region (or shallow trench isolation region); and a doped region on the sidewall of the recessed region. In accordance with another preferred embodiment of the present invention, a method for fabricating a planar transistor-like transistor component includes first providing a semiconductor substrate germanium and filling an oxide in a shallow trench isolation region of a boring depth (referred to as The shallow trench isolation oxide) thus exposes the germanium-containing sidewalls in the shallow trench isolation region and defines the channel region of the transistor that will have the appropriate threshold voltage dopant. Alternatively, after forming the shallow trench isolation region and filling the oxide, a chemical removal process (eg, reactive ion etching or chemical wet etching) may be performed on the semiconductor substrate to form a small inclusion on both sides of the active region. a barrier spacer, and an oxide etched in the shallow trench isolation region to expose the sidewall containing the germanium, wherein the sidewall and the germanium-containing spacer define a channel region of the transistor and are implanted with a threshold voltage Process. In another embodiment of the present invention, the transistor component of the planar-like transistor has a channel region formed in a narrow and undoped germanium-containing region in the shallow trench isolation region, such that the transistor component of the planar-like transistor is allowed. Like the fin field 2 13 1281257, the transistor has a thin body effect. The advantages of raising the source include reducing the secret and 汲 ^ ~. The structure provided by the structure still has an extra point on the path of the block material. The application of the present invention will not cause a floating body effect as in the case of the insulating layer on the insulating layer. In addition, if necessary, in another embodiment of the present invention,
亦可應用來讓傳統的電晶體與㈣式場效電晶體 的電曰曰體元件一同製造於塊狀矽材上。 本^月提供了多種類平面電晶體的電晶體元件，直呈 t加寬的摻雜通道寬度’且不會增加接合漏電流。跨坐二 邊轉及淺溝隔_之㈣上的閘極料提供絕佳的通道控 另外由於本發明之電晶體的源極與沒極較淺溝隔離 品之側壁（換言之’通道區）高’故可讓於源極與汲極穿透塊 夕材的電1¾合效應減弱’進而有效地改善短通道效應。It can also be applied to make a conventional transistor together with an electric body element of a (four) field effect transistor on a block coffin. This month provides a variety of planar transistor-like transistor elements that directly t widen the doped channel width' without increasing the junction leakage current. The gate material on the two-side turn and the shallow trench isolation (4) provides excellent channel control. In addition, the source of the transistor of the present invention and the sidewall of the shallow trench isolation (in other words, the channel region) are high. 'Therefore, the effect of the electric source and the bungee penetrating through the block will be weakened' and the short channel effect will be effectively improved.
【實施方式】 言_本發明一方面就是在提供一種結合類平面互補金氧半 、、_及-9式％效電晶體之電晶體元件的技術，並令其製造 :，狀矽材上’用以一併改善平面互補金氧半導體，以及 、、、巴緣層上覆石夕肖構上之鰭式場效電晶體的特十生與效能。 〃般而a ’首先需提供半導體基材。此半導體基材的 才料軏佺為矽。基材具有至少一凹陷區或淺溝隔離區，而 凹陷區或淺溝隔離區的數量較佳為二；其中每一凹陷區或 久溝隔離區具有侧壁及底部，而每一凹陷區或淺溝隔離區 14 1281257 之底部具有底部。兩淺溝隔離區之間係藉由半導體基材的 頂表面（或頂壁）來區隔，其中半導體基材的頂表面及每一淺 溝隔離區的兩側壁將定義出主動區之通道區，其中每一淺 溝隔離區的兩側壁係並列於電晶體之主動區的一邊。 電晶體元件之源極與汲極係位於半導體基材的頂表面 上，且位於兩淺溝隔離區之間。閘極導體層係沿著半導體 基材的頂表面形成’並蚊義出通道區之每—淺溝隔離區 部分重疊。淺溝隔離區之㈣的形成方法與在金氧半導體 電晶體技術領域中所使用的形成方法相同。 此外，具有間隙壁或鰭之含矽凹陷區亦可選擇性地沉 積於兩淺溝隔離區之間。 另外在本發明之一實施例中，本發明之類平面電晶 體的電晶體元件所提供之源極與㈣係凸起於淺溝隔離區 的側壁上方。 參知第4圖’其繪示本發明之一較佳實施例。更具體 地說，第4圖所繪示之類平面電晶體的電晶體元件34包含： 塊狀石夕基材36 ’其具有定義出電晶體元件的主動區之 頂表面38 ;定義出淺溝隔離區4〇之第一凹陷區，其具有至 J側壁44及底部48，如此側壁44即座落在矽基材36 之頂表面38之間，並自頂表面38延伸至底部48，其中淺 溝隔離區40之側壁44將定義出電晶體之通道區。 較佳的情況是再提供一個具有側壁46及底部50之淺 溝離區42(也稱為第二凹陷區），此第二凹陷區係可距第 一凹陷區一預定距離。 15 1281257 如苐4圖所繪示’於本發明之一實施例中，類平面電 晶體的電晶體元件係可藉由以下步驟形成： k供一塊狀半導體基材，形成具有側壁之至少一凹陷 區或淺溝隔離區；以及於部分深度之淺溝隔離區中填入淺 溝隔離氧化物，如此淺溝隔離區之含矽側壁將定義出電晶 體的通道區，其中電晶體的通道區具有適當的臨界電壓摻 雜物。 第4圖所繪示之類平面互補金氧半導體的電晶體元件 具有摻雜通道區，且此摻雜通道區係由淺溝隔離區之側壁 所組成。 參照第4圖，首先形成至少一淺溝隔離區，其使用的 方法包含：首先形成氧化物襯墊層（未繪示），此氧化物襯墊 層的較佳厚度係介於約50 A〜150 A ;接著於基材表面上形 成圖案化的光阻；之後再蝕穿氧化物襯墊層並進入到基材 的表面裡。 於每一淺溝隔離區中形成絕緣層58，此絕緣層僅位於 每一淺溝隔離區40、42的底部，因此每一淺溝隔離區4〇、 42。之頂部的側壁將暴露出來。此絕緣層可填滿淺溝隔離區 80%的深度。^，在本發明之—較佳實施例中，絕緣層僅 填滿淺溝隔離1 2G%的深度。或者在本發明的另—較佳實 施例中，絕緣層將填滿淺溝隔離區1〇%〜3〇%的深度；此外 在。本發明的再_較佳實施财，絕緣層將填滿淺溝隔離區 j〇%〜50%的深度、絕緣層的材料較佳為氧化物。由氧化物 組成之絕緣層係可藉由熱成長製程或沉積製程以形成，其 16 1281257 中熱成長製程儀可A # μ 、為…、爐官或快速熱製程（Rapid Thermal Process ； RTP) » l · 〇 •應用現場蒸汽產生技術之快速熱製 牙王或快連熱氧化赞鞋π 、# (Rapid Thermal Oxidation ; RTO)，而 可為化學氣相沉積或次大氣壓化學氣相沉積。 展=^木填充技術如高密度電漿亦可應用來形成絕緣 :。白/技蟄者當知，高密度電漿沉積製程的填溝能力較 二：k供具有厚度較均勾之絕緣層。在高密度電漿沉 積製程後可利用渴式鈾方，丨十 ..+ ”、、弋蝕刻來回蝕。若利用高密度電漿沉積 一 久溝^離區中，將使得氧化物於淺溝 隔離區之底部48、sn ραλ、丄 一 上的沉積速度較側壁44、46快，因 此於側壁44、46上的ϋ几仏π丄 氧匕物可在隨後完全清除，且不會因 此而耗盡垂直方向的氧化物。 如弟4圖所1會示，絕緣層58係填滿淺溝隔離區約50〇/〇 的深度。而通道區之臨界電壓係可藉由大傾角的植入製程 來調整以植入適當的摻雜物。 淺溝隔離區4〇、42之側壁44、46及頂表面將構成電 錢過的通道區。因此，本發明之金氧半導體電晶體的通 道覓度係為兩侧壁的诵i曾嘗痒& i + 旧通迢冕度外加頂表面的通道寬度（在 某些文獻中也被稱為三閘電晶體）。而傳統平面金氧半導體 電晶體的通道寬度僅為頂表面的通道寬度。填充於淺溝隔 離區中之氧化物的量將決定側壁的通道寬度。沿著頂表面 及兩側壁形成之閘極將對電晶體通道具有絕佳的間極控 制，在相關文獻中已將類似的控制方法應用於絕緣層上覆 矽結構上之雙閘電晶體。 17 !281257 參照第4圖及第8A-8F圖，根據本發明之一較佳實施 例、’互補金氧半導體電晶體係可利用結點尺寸為9〇 nm之 互補金氧半導體佈局的製程技術來形成。對於結點尺寸為 90 nm之互補金氧半導體而言’淺溝隔離區的深度約為犯 U m田絶緣層填滿淺溝隔離區50%的深度時，與兩側壁相 關的通道寬度亦約等於〇.35 。因此，假設應用本發明 :結構製作頂表面之通道寬度為0.35…靜態隨機存 。己隐體’其d憶體單元的通道寬度可較應用習知結構之 ㈣體單元的通道寬度寬三倍。具有相同閘極長度但通道 見度更寬的電晶體將可導通更多的電流，且這樣的電 將較其他電晶體的反應速度更快。 B曰體 本發明之一較佳實施例所揭露之製造方法將在 :，請-併參照第8圖。第^圖係緣示於淺溝隔離田 相剖面圖。殘留的氮化物及氧化物襯塾層（切示1 盍於由石夕組成的主動區上。如第8β圖所纷示 议 區形成後，製造者可選擇性地加入場接雜物1〇8二冓陣離 緣。如第8C圖所繪示，淺溝隔離氧化物係可填σ強絕 區内，較佳地係填滿淺溝隔離區·的深度，、此、=搞離 氧化物係可利用自對準氧化物沉積或利用氮化物开二）離 式罩幕層1G4來填充至淺溝隔離區内。氮化物所形之硬 式罩幕層104的厚度係介於1〇〇入〜5〇〇 a。如第之硬 示，於淺溝隔離區的側壁上係可實施大傾角 圖所纷 此大傾角的植人製程將定義通道區，以允 ^， 行調整。 、界電壓進 18 I28l257 雜物製造f可選擇性地於淺溝隔離區之側壁上植入含氣摻 ” 以抑制氧化物於側壁上的峰具$, 續π 的生長速率，如此即可讓後 、戈於成溝隔離區的側壁及石夕基 呈 /丞材的頂表面沉積之閘介電層 κ、有相同的厚度，其中含氮摻雜物的植入能量係約10 α ’而植^劑量係介於咖·1El5ai⑽s/cm2。 萨丈Ϊ者’氮化物所形成之硬式罩幕層較佳地係藉由渴磷 =二除：緊:著將氧化物概塾層移除，然後再對半導體 層，此私’以具體地在主動區上形成氧化物犧牲 Γ 物犧牲層的厚度係介㈣50 A〜1GG Α。上述之 虱化製程通常在植入製程前實施。 在氧化物犧牲層形成後， 雜製程形成。在p刑此Β Μ 主才力财猎由摻 / Ν型井形成後，氧化物犧牲層將 被私除。接者开》成閘介電；， "此閘η電層之介電常數係約 ；，且/、厚度係介於約10 Α〜70 Α。 A的if:圖所緣不，緊接著沉積一層厚度約彻A〜800 極声）ιΓ今層⑽如：推雜多晶石夕層或金屬石夕化物間極電 極層）或金屬矽化物層6〇,分，_ . 減〉、對淺溝隔離區之側壁的消 耗。對於金氧半導體而言，多曰 ^自 — 口夕日日矽疋理想的閘極電極材料。 U L所綠不’接著將沉積—層厚度約伽 的第二切層62(例如未摻雜之多晶料）。 然後閘極電極56(多晶石夕）將藉由圖案化罩幕及電裝敍 以形成。在此亦將定義出源極5 4及汲極5 2。 ^照第，7、圖’在本發明之另一實施例中，一個較窄且 未心雜的碎通道將传麵求 使類千面電晶體的電晶體元件如同類鰭 19 1281257 弋昜效電sa體的電晶體元件一般具有薄體效應的優點。此 外，升南的源極與汲極將使額外的漏電流自源極與汲極流 向鬼狀石夕材，故本發明將沒有絕緣層上覆石夕結構上的鰭式 ' 場效電晶體所具有的浮體效應。 ' 第7圖所繪示的元件結構上與第4圖所繪示的元件結 構犬員似，惟第7圖所綠示的石夕通道較窄且未換雜。此外， 第7圖所繪示之源極54與汲極52係升高至淺溝隔離區之 • 側壁44與46上方（與第4圖類似），且第7圖所緣示的元 件結f包含應用金屬矽化製程所形成之金屬矽化物層96。 隨著元件尺寸不斷地縮小，在結點尺寸65⑽的互補 錢半導體技術中，主動區的最小寬度可能縮小至8〇nm， 這樣的尺寸已纪足以產生薄體效應來強化遷移率及反轉體 積第7圖係繪不於塊狀石夕材上製造之類籍式場效電晶體 的電晶體元件，其淺溝隔離區具有未接雜的側壁，以及最 小寬度时通道區（在結點尺寸65nm的互補金氧半導體技 • 術中，矽通道區的寬度可小至約80 nm)，如此即可享有薄 體效應的優點及其他類平面電晶體的電晶體元件所擁有的 、優點（例如減少短通道效應，以及肇因於良好閘極控制能力 的絕佳開關特性）。 第7圖係繪示在金屬石夕化製程後之_式場效電晶體 的電晶體儿件，其係位於塊狀石夕材上。如第7圖所緣示， 金屬石夕化後的源極與没極（第7圖所綠示之金屬石夕化物層 96)係位於側壁上方，以減少源極與汲極間穿透塊狀石夕材的 電_馬合效應。 20 1281257 從概念上來說，本發明於塊狀石夕材上之類鰭式場效電 晶體的電晶體70件係可由絕緣層上覆碎結構上的鰭式場效 電晶體推知，只要將其埋人氧化物層的厚度降為零即/。 然而本發明所揭示的結構仍具有自源極舆汲極接合區通往 塊狀矽材的漏電流，但此漏電流的量遠小於習知平面互補 金氧半導體中的漏電流。漏電流會減少的主因為閘極引發 的/及極漏電流較少，而閘極引發的没極漏電流較少的原因 為最佳化臨界電_t r〇u_〇ff)所需的口袋摻雜物較 少〇 此外，大部分之源極與汲極係高於淺溝隔離區之側壁 (換口之’通運區）’也就是說部分之源極與汲極係升高以 抑制源極與汲極間穿透塊㈣材的電轉合效應，進而抑制 了紐通道效應。本發明所揭示之類鰭式場效電晶體的電晶 體由於其位於塊狀石夕材上，故不像位於絕緣層上覆石夕結 構上的鰭式場效電晶體—般具有浮體效應，這是因為本^ 明之類鰭式場效電晶體的電晶體元件，其通道區或主體係 電性連接矽基材。 _本發明之另一實施例所揭示之類平面電晶體的電晶體 元件係緣示於第5-6圖。 、參妝第5-6圖，其繪不應用本發明所揭露的方法而形 成的另一類平面電晶體的電晶體元件，此方法包含··首先 、'十# σ卩刀的石夕基材貫施非等向性钱刻以於主動區的邊界上 ^成由石夕構成之間隙壁，並接著填充淺溝隔離氧化物。窄 或者說是薄的間隙壁係類似絕緣層上覆矽結構上之鰭式場 21 l28l257 效電晶體的鰭，其功能係提供一個導體通道。依照本實施 例所製造的類平面電晶體的電晶體元件可增強窄電晶體的 驅動電流，但不會增加接合漏電流。窄電晶體技術常用來 製造靜態記憶體之記憶單元，用以最小化記憶單元的尺寸。 更具體地说’弟5圖係繪示本發明之一類平面電晶體 的電晶體元件66,其具有塊狀矽基材67;定義出電晶體之 主動區的頂表面69 ;定義出淺溝隔離區74之第一凹陷區， 此淺溝隔離區74具有至少一側壁80及底部84，如此側壁 80即可座落於矽基材67的頂表面之間，並自頂表面 延伸至底部84，其中淺溝隔離區74之侧壁80將定義出電 晶體元件66之通道區。 較佳的情況是再提供一個具有側壁82及底部86之淺 溝隔離區76 (也稱為第二凹陷區），此第二凹陷區係可距第 一凹陷區一預定距離。 此外，電晶體具有由矽所組成的間隔凹陷區7〇，此間 隔凹陷區70係座落於淺溝隔離區74與淺溝隔離區76之 間。間隔凹陷區具有至少兩邊鰭77、78，且此二邊鰭口、 78的間隔距離係可至少小於丨〇〇 nm、8〇 nm、6〇 、利_、 20 rnn或1〇 nm。每一邊鰭77、78具有狹窄的寬幅，並與 元件主動區的邊界68、72對齊。 根據本發明之一較佳實施例，類平面電晶體的電晶體 元件係可藉由在部分深度之淺溝隔離區中填充淺溝隔：： 化物來形成，如此淺溝隔離區中由矽組成的側壁即可扮演 導體通道的角色。 ” 22 1281257 66 / 4閘極係可沿著切組成的頂表面及淺溝 -…貝'壁形成，以讓電晶體之通道區具有絕佳的控制 似的機制也在絕緣層上㈣結構上之鰭式場效電晶 體發生。 隨著元件尺寸不斷地縮小，應用本發明所揭示的類平 面電晶體的電晶體亓徠监1 —抑 十 一 电曰曰體70件將可在單一基材上結合更多數量的 可同4具備絕緣層上覆秒結構上之鰭式場效電晶[Embodiment] In one aspect of the present invention, there is provided a technique for combining a transistor element of a planar-like complementary MOS, _, and -9 type efficacies, and fabricating the same: It is used to improve the speciality and efficiency of the plane-complementary MOS, and the fin-type field effect transistor on the ridge layer. In general, a semiconductor substrate is required first. The semiconductor substrate is the best. The substrate has at least one recessed area or shallow trench isolation area, and the number of recessed areas or shallow trench isolation areas is preferably two; wherein each recessed area or long trench isolation area has sidewalls and a bottom, and each recessed area or The bottom of the shallow trench isolation zone 14 1281257 has a bottom. The two shallow trench isolation regions are separated by a top surface (or a top wall) of the semiconductor substrate, wherein the top surface of the semiconductor substrate and the two sidewalls of each shallow trench isolation region define a channel region of the active region The two side walls of each shallow trench isolation region are juxtaposed on one side of the active region of the transistor. The source and drain of the transistor component are on the top surface of the semiconductor substrate and are located between the two shallow trench isolation regions. The gate conductor layer is formed along the top surface of the semiconductor substrate and the shallow trench isolation regions are partially overlapped. The formation method of the shallow trench isolation region (4) is the same as that used in the field of metal oxide semiconductor transistor technology. In addition, the sag-containing recessed regions having spacers or fins may also be selectively deposited between the two shallow trench isolation regions. Further in an embodiment of the invention, the source and (4) of the planar transistor of the planar electro-optic body of the present invention are raised above the sidewall of the shallow trench isolation region. Referring to Figure 4, there is shown a preferred embodiment of the present invention. More specifically, the transistor element 34 of the planar transistor illustrated in FIG. 4 comprises: a bulk-like substrate 36' having a top surface 38 defining an active region of the transistor element; defining a shallow trench The first recessed region of the isolation region has a side wall 44 and a bottom portion 48 such that the sidewall 44 is seated between the top surface 38 of the crucible substrate 36 and extends from the top surface 38 to the bottom portion 48, wherein the shallow trench The sidewall 44 of the isolation region 40 will define the channel region of the transistor. Preferably, a shallow trench isolation region 42 (also referred to as a second recess region) having sidewalls 46 and a bottom portion 50 is provided, the second recess region being a predetermined distance from the first recess region. 15 1281257 As shown in FIG. 4, in one embodiment of the present invention, a transistor element of a planar-like transistor can be formed by the following steps: k for a block-shaped semiconductor substrate to form at least one of sidewalls a recessed region or a shallow trench isolation region; and a shallow trench isolation oxide filled in a shallow trench isolation region of a partial depth, such that the germanium-containing sidewall of the shallow trench isolation region defines a channel region of the transistor, wherein the channel region of the transistor With appropriate threshold voltage dopants. The transistor component of the planar complementary MOS semiconductor illustrated in Fig. 4 has a doped channel region, and the doped channel region is composed of sidewalls of the shallow trench isolation region. Referring to FIG. 4, at least one shallow trench isolation region is first formed, the method comprising: first forming an oxide liner layer (not shown), and the preferred thickness of the oxide liner layer is about 50 A~ 150 A; a patterned photoresist is then formed on the surface of the substrate; the oxide liner layer is then etched through and into the surface of the substrate. An insulating layer 58 is formed in each of the shallow trench isolation regions, the insulating layer being located only at the bottom of each of the shallow trench isolation regions 40, 42, thus each shallow trench isolation region 4, 42. The side walls at the top will be exposed. This insulating layer fills 80% of the shallow trench isolation area. ^ In the preferred embodiment of the invention, the insulating layer fills only shallow trenches to isolate a depth of 12 G%. Alternatively, in another preferred embodiment of the invention, the insulating layer will fill the depth of the shallow trench isolation region by 1% to 3%; According to still another aspect of the present invention, the insulating layer fills the shallow trench isolation region by a depth of from 〇% to 50%, and the material of the insulating layer is preferably an oxide. The insulating layer composed of oxide can be formed by a thermal growth process or a deposition process, and the 16 1281257 medium thermal growth process can be A #μ, for..., furnace or Rapid Thermal Process (RTP) » l · 〇 • Apply on-site steam generation technology to rapidly heat the tooth or rapper π, # (Rapid Thermal Oxidation; RTO), which can be chemical vapor deposition or sub-atmospheric chemical vapor deposition. Exhibition = ^ wood filling technology such as high density plasma can also be applied to form insulation: White/technicians know that the high-density plasma deposition process has a more filling ability than the second: k for an insulating layer with a thicker thickness. After the high-density plasma deposition process, the thirst-type uranium can be used, and the 丨10..+ ”, 弋 etch back etch. If the high-density plasma is used for deposition, the oxide will be isolated in the shallow trench. The deposition rate of the bottom portion 48, sn ραλ, and 丄1 of the region is faster than that of the sidewalls 44, 46, so that the 仏 丄 丄 丄 于 on the sidewalls 44, 46 can be completely removed later and will not be exhausted. The oxide in the vertical direction. As shown in Figure 1, the insulating layer 58 fills the shallow trench isolation region at a depth of about 50 〇 / 。. The threshold voltage of the channel region can be obtained by a large tilt implantation process. Adjusting to implant appropriate dopants. The shallow trench isolation regions 4, 42 sidewalls 44, 46 and the top surface will constitute the channel region for the electricity money. Therefore, the channel mobility system of the MOS transistor of the present invention For the two sidewalls, 诵i has tasted the itch & i + the old enthalpy plus the channel width of the top surface (also known as the tri-gate transistor in some literature). The traditional planar MOS transistor The channel width is only the channel width of the top surface. The oxide filled in the shallow trench isolation region The amount will determine the channel width of the sidewall. The gate formed along the top surface and the two sidewalls will have excellent inter-electrode control for the transistor channel. Similar control methods have been applied to the overlying structure of the insulating layer in the related literature. Double gate transistor. 17 !281257 Referring to Figure 4 and Figures 8A-8F, in accordance with a preferred embodiment of the present invention, a 'complementary gold oxide semiconductor crystal system can utilize a junction size of 9 〇 nm complementary The process technology of the MOS layout is formed. For a complementary MOS semiconductor with a 90 nm junction size, the depth of the shallow trench isolation region is about 50% of the depth of the shallow trench isolation region. The width of the channel associated with the two sidewalls is also approximately equal to 〇.35. Therefore, it is assumed that the invention is applied: the width of the channel for the top surface of the structure is 0.35... static random storage. The channel width of the hidden body can be compared The channel width of the (4) body unit of the conventional structure is three times wider. A transistor with the same gate length but wider channel visibility will conduct more current, and such electricity will be more reactive than other transistors. fast B. The manufacturing method disclosed in a preferred embodiment of the present invention will be: - Please refer to Fig. 8. The figure is shown in the shallow trench isolation field phase profile. Residual nitride and oxidation The lining layer of the material (showing 1 盍 on the active area composed of Shi Xi. After the formation of the discussion area in the 8th figure, the manufacturer can selectively join the field connection debris 1 〇 8 冓 离 离As shown in Fig. 8C, the shallow trench isolation oxide can be filled in the σ strong region, preferably filled with the depth of the shallow trench isolation region, and the = oxide system can be utilized The quasi-oxide deposition or the nitride mask layer 1G4 is used to fill the shallow trench isolation region. The thickness of the hard mask layer 104 in the form of nitride is between 1 and 5 〇〇a. As shown in the first section, on the side wall of the shallow trench isolation zone, the implanting process that can implement the large dip angle of the large dip angle will define the channel zone to allow adjustment. The boundary voltage enters 18 I28l257. The impurity manufacturing f can selectively implant the gas-containing dopant on the sidewall of the shallow trench isolation region to suppress the peak of the oxide on the sidewall, and continue the growth rate of π, so that After the sidewall of the Geyucheng isolation zone and the gate dielectric layer κ deposited on the top surface of the Shiyueji/Coffin, the same thickness is applied, wherein the implanted energy of the nitrogen-containing dopant is about 10α' The planting dose is between 1 El5ai (10) s/cm2. The hard mask layer formed by the sapphire 'nitride is preferably divided by thirst phosphorus = two: tight: remove the oxide layer Then, for the semiconductor layer, the thickness of the sacrificial layer of the oxide sacrificial material is specifically formed on the active region by (4) 50 A to 1 GG Α. The above-mentioned deuteration process is usually performed before the implantation process. After the formation of the sacrificial layer, the miscellaneous process is formed. After the formation of the 才 Μ Μ Μ Μ Μ Μ 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物The dielectric constant of the gate η electrical layer is about; and /, the thickness is between about 10 Α and 70 Α. , followed by deposition of a layer of thickness about A ~ 800 extreme sound) ιΓ current layer (10) such as: push polycrystalline stone layer or metal lithium interelectrode layer) or metal telluride layer 6 〇, minutes, _. 〉, the consumption of the sidewall of the shallow trench isolation zone. For the MOS semiconductor, the ideal gate electrode material of the 口 曰 自 UL UL 。 。 UL UL UL UL UL UL UL UL UL UL UL UL UL UL UL UL a second dicing layer 62 (eg, an undoped polycrystalline material). The gate electrode 56 (polycrystalline slab) will then be formed by patterning the mask and electrical assembly. The source 5 will also be defined herein. 4 and bungee 5 2. ^Photograph, 7, Figure 'In another embodiment of the present invention, a narrow and unambiguous broken channel will be used to make a crystal element of a thousand-faced transistor such as Similar fins 19 1281257 电 电 sa 的 的 的 电 电 一般 一般 一般 一般 一般 sa sa sa sa 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, the present invention will have no floating body effect of the fin type field effect transistor on the overlying structure of the insulating layer. The components shown in the figure are similar in structure to the component structure dog shown in Fig. 4. However, the Shixi channel shown in Fig. 7 is narrow and not replaced. In addition, the source shown in Fig. 7 The pole 54 and the drain 52 are raised to the shallow trench isolation region • above the sidewalls 44 and 46 (similar to Fig. 4), and the component junction f shown in Fig. 7 contains the metal germanium formed by the metal germanium process. The layer 96. As the component size continues to shrink, in the complementary semiconductor technology with a junction size of 65 (10), the minimum width of the active region may be reduced to 8 〇 nm, which is sufficient to produce a thin body effect to enhance mobility. And the reverse volume is shown in Fig. 7 as a transistor element of a class field-effect transistor fabricated on a block-shaped stone material, the shallow trench isolation region having an unsurpassed sidewall, and the channel region at a minimum width (in Complementary MOS technology with a junction size of 65 nm, the width of the 矽 channel region can be as small as about 80 nm), so that the advantages of the thin body effect and the advantages of other transistor components of planar transistors can be enjoyed. (eg reducing short channel effects, and Good to excellent gate control electrode of the switching characteristics). Figure 7 is a diagram showing the crystal device of the field effect transistor after the metal-stone process, which is located on the block stone. As shown in Fig. 7, the source and the eclipse (the metal lithium layer 96 shown in Fig. 7) are located above the sidewall to reduce the penetration between the source and the drain. The electric _ horse combined effect of the stone. 20 1281257 Conceptually, the 70-piece transistor of the fin field effect transistor of the present invention can be inferred from the fin field effect transistor on the insulating layer, as long as it is buried. The thickness of the oxide layer drops to zero. However, the disclosed structure still has leakage current from the source drain junction to the bulk coffin, but the amount of leakage current is much smaller than the leakage current in conventional planar complementary MOS. Leakage current is reduced mainly because the gate induces / and the leakage current is less, and the reason why the gate has less leakage current is to optimize the critical electric _tr〇u_〇ff) Less dopants. In addition, most of the source and drain are higher than the sidewalls of the shallow trench isolation (transportation 'transportation zone'', that is, part of the source and drain are raised to suppress the source. The electrical coupling effect between the pole and the bungee penetrates the block (four) material, thereby suppressing the New Channel effect. The transistor of the fin field effect transistor disclosed in the present invention has a floating body effect instead of a fin field effect transistor which is located on the overlying structure of the insulating layer because it is located on the block-shaped stone material. It is because the transistor element of the fin field effect transistor of the present invention has its channel region or main system electrically connected to the substrate. The edge of the transistor element of a planar transistor disclosed in another embodiment of the present invention is shown in Figures 5-6. Figure 5-6 shows another type of planar transistor crystal element formed by applying the method disclosed by the present invention. The method comprises: · First, the '10# σ 卩 的 石 基材 substrate The non-isotropic energy is applied to the boundary of the active region to form a spacer formed by Shi Xi, and then fills the shallow trench isolation oxide. The narrow or thin spacer is similar to the fin field on the insulating layer. The fin of the effect transistor provides a conductor path. The transistor element of the planar-like transistor fabricated in accordance with this embodiment enhances the drive current of the narrow transistor without increasing the junction leakage current. Narrow transistor technology is commonly used to create memory cells for static memory to minimize the size of the memory cells. More specifically, the figure 5 shows a transistor element 66 of a planar transistor of the present invention having a bulk germanium substrate 67; defining a top surface 69 of the active region of the transistor; defining shallow trench isolation The first recessed region of the region 74 has at least one sidewall 80 and a bottom portion 84 such that the sidewall 80 can be seated between the top surface of the crucible substrate 67 and extend from the top surface to the bottom portion 84. The sidewall 80 of the shallow trench isolation region 74 will define the channel region of the transistor element 66. Preferably, a shallow trench isolation region 76 (also referred to as a second recess region) having sidewalls 82 and a bottom portion 86 is provided, the second recess region being a predetermined distance from the first recess region. Further, the transistor has a spacer recessed region 7〇 composed of tantalum, and the spacer recessed region 70 is located between the shallow trench isolation region 74 and the shallow trench isolation region 76. The spacer recess has at least two fins 77, 78, and the distance between the two fins, 78 can be at least less than 丨〇〇 nm, 8 〇 nm, 6 〇, _, 20 rnn or 1 〇 nm. Each of the fins 77, 78 has a narrow width and is aligned with the boundaries 68, 72 of the active area of the component. According to a preferred embodiment of the present invention, the transistor element of the planar-like transistor can be formed by filling a shallow trench isolation region in a shallow trench isolation region of a partial depth, such that the shallow trench isolation region is composed of germanium. The side walls act as conductor channels. 22 1281257 66 / 4 gate system can be formed along the top surface of the cut and the shallow groove - ... shell wall, so that the channel area of the transistor has an excellent control mechanism also on the insulation layer (four) structure Fin-type field effect transistor occurs. As the size of components continues to shrink, the application of the planar planar transistor-like transistor of the present invention can be combined on a single substrate. A large number of fin-type field-effect transistors with the same on-layer structure
體:擁有的優點；此外，本發明所揭示的類平面電晶體的 電曰曰體7L件亦可具有薄體效應及升高之源汲極結 的優點。 两 〜另外，由本發明所揭示的類平面電晶體的電晶體元件 系又置於塊狀秒材上，故源/没極與塊狀砍材間將具有漏電 流，因此於絕緣層上覆石夕結構上之鰭式場效電晶體中所發 生的洋體效應將不會在本發明所揭示的類平面電晶體的電 晶體元件中發生。 第6圖所緣示之類平面電晶體的電晶體元件具有一個 未摻雜且狹窄的通道；在結點尺寸為9〇 nm的互補金氧半 導體技術領域中，此通道的寬度係約12Qnm(如第5圖所綠 ㈤；而在結點尺寸為65 nm的互補金氧半導體技術領域 中，此通道的寬度係約80 nm(如第5圖所繪示）。此狹窄的 通道具有邊,鰭及㈣。邊‘_於簡單且小㈣㈣隔凹陷 區。在結點尺寸為9G nra的互補金氧半導體技術領域中， 未摻雜之邊鰭的寬度為40mn，而在結,點尺寸為65nm的互 補金氧半導體技術領域中，未摻雜之邊韓的寬度為3 。 23 I28l257 所有的鰭最好都具有一樣的寬度。製造者可藉由設置複數 個彼此平行的鰭，並於鰭上設置一個共通閘極來製造通道 見度更見的電晶體。製造第5 - 6圖所繪示之電晶體的方法 類似於第4圖及第8A-8F圖所繪示的方法，惟第5-6圖所 繪示之通道區並未摻雜。因此，在本實施例中並不需要實 施臨界電壓摻雜製程。 製造第6圖所繪示之電晶體的方法類似於第4圖及第 8A - 8F圖所繪示的方法，惟在第6圖所繪示的電晶體具有未 摻雜之間隔凹陷區及淺溝隔離區74、76。如第6圖所繪示， 於淺溝隔離區74、76形成後，矽基材將些微凹陷，凹陷的 深度約為淺溝隔離區深度之25%。這些凹陷的矽基材將最好 形成兩間隙壁78、77,其分別代表電晶體主動區的兩個邊 界68、72。接著，部分深度之淺溝隔離區將填充淺溝隔離 氧化物，較佳係填滿淺溝隔離區1〇%〜5〇%的深度。由矽組 成之間隙壁或邊鰭係沿著電晶體主動區的兩邊形成。狹窄 的邊鰭，可用以做為電晶體的通道區。此電晶體之通道區 的通道寬度較佳為0.4 ，其可能藉由複數個狹窄的邊鰭 組成’而每一邊鰭的寬度小於〇. 2 # m。 理想的間隙壁係為窄或者薄的，其類似絕緣層上覆矽 結構上之鰭式場效電晶體_，如此電晶體即可擁有薄體 效應的優點。 ^ β多晶矽金屬閘極係與邊鰭與淺溝隔離區的側壁部分重 a:以對電晶體的通道區提供絕佳的控制，此機制類似於 絕緣層上覆石夕結構上之雙閘電晶體所提供的控制。而源極 24 1281257 與沒極亦高於每-淺溝隔離區之側壁，如此即可改善短通 T效應’這是因為源極與汲極間透過塊狀石夕材的電柄合效 應減弱的緣故。 第9A-9F係綠示第卜6圖所繪示之電晶體的製造流程 ，其具有含邊與側壁之類平面通道。f Μ,圖所緣 係與弟8A_8F所繪示的製程類似，首先形成淺溝 :離區’然後在其中填充氧化物。如第9a圖所緣示，在淺 溝Pp?3離區形成德，制、生. 衣^者可迖擇性地加入場摻雜物以加強 乡巴緣0 接著1除於石夕基材之主動區上的氮化物與氧化物觀 :化物,墊層移除後，矽基材將凹陷以形成間隔 區。如弟Μ圖所繪示，凹陷的深度係約淺溝隔離 /a又另外，製造者可額外實施熱回火製程（如快 ^與=製程^以修復間隙壁凹陷區域及淺溝隨 ㈣ί者如第9D圖所繪示，淺溝隔離氧化物88將藉由乾 声二供^於域隔離區卜淺溝隔離氧化物⑽的凹陷深 度旱父仏為淺溝隔離區 度的5〇^。但此並不限制本發明，淺 20% 80:化物的凹陷深度係可介於淺溝隔離區深度的 的1^之間。接著，於基材上藉由熱成長製程來形成薄薄 所、^聽物犧牲層’用以去除由電漿乾钱刻氧化物及矽 所造成的缺陷。 在氧化物犧牲層形成後，Ρ型井及Ν型井亦將，由摻 雜製程形成。纟ρ丄牙疋财猎由^ i井及N型井形成後，氧化物犧牲層將 25 1281257 被私除接著形成閘介電層（例如氧化矽），此閘介電層之厚 度係介於約ίο A〜70 A。 曰 ^口第9E圖所纷示，緊接著沉積一層厚度❸400 A〜800 ，、第夕曰曰矽層100 ’此多晶矽層係預先摻雜過，以減少 溝隔離區之側壁的多晶矽。對於金氧半導體而言， 夕日日石夕疋理想的閘極電極材料。 如第9F圖所％不，接著將依照最小化設一 層厚度約彻A〜_A的第二多晶㈣m，以填滿每，淺 溝隔離區。 羔後閘極電極94(多晶矽)將藉由圖案化罩幕及電漿蝕 刻製程來形成（如第9F圖所綠示）。緊接著將進行-此習知 =補金氧半導體製程，例㈣義源極9Q及汲極I植入 衣私、金屬矽化製程及其他製程。 另外，在本發明之另一實施例中，額外的罩幕亦可應 丁開部分類鰭式場效電晶體的電晶體元件，進而讓以 的製程結合至類鰭式場效電晶體的電晶體元件，例如淺 溝隔離氧化物的餘刻萝裎 ,口上L 衣私及用以形成間隙壁的石夕钱刻製 於 纟傳統的電晶體與類‘鰭式場效電晶體的電晶 體70件係可一同製造於塊狀矽材上。 元件m卜r罩幕亦可應用來保護類續式電晶體之電晶體 nr 使其免受後續對石夕基材進行之㈣製 =衫曰。同樣地，此將使得源極與汲極相對於通道區的 回度進一步地抬高，進而壤弁古 的優點更佳地顯著。料κ源極與㈣結構所擁有 26 1281257 如以上所述，本發明已揭露數個類平面並類鰭式場效 電晶體的元件及其製造方法。 - $然本發明已以一較佳實施例揭露如上，然其並非用 、卩限定本發明，任何熟習此技藝者，在不脫離本發明之於 神和範圍内，當可作各種之更動與潤飾，因此本發明之: 護範圍當視後附之申請專利範圍所界定者為準。 ’、 • 【圖式簡單說明】 =明之上述和其他目的、特徵、優點與 月匕更明顯易懂，所附圖式之詳細說明如下·· 第1圖係緣示位於絕緣層上覆石夕結構上 效U體，其具有切製成之I#。 ，式场 弟2A圖係緣示習知技術鍵 植入製程。 丁之，圖木化、姓刻及臨界電麼 !2β圖係繪示習知技術之閘極圖案化製程。 於J 2C圖係緣示習知技術之大傾角的植入製程，直用以 、’二(：N型通道或？型通道)形成輕摻雜汲。、 第2:，知技術之形成間隙壁的製程。 屬欲二 在習知技術令，於源極與汲極上，今 屬石夕化製程或導體層沉積製程。 枉上貝細金 :3圖係緣示習知技術之 式知效電晶體，其具有一：夕：構上之錯 電晶體的材上― 透視圖，其令電晶體具有接雜的通 27 1281257 道區。 第5圖係繪示依照本發明之類鰭式場效電晶體的電晶 體的部分透視圖，其中電晶體具有摻雜的通道區及邊鰭。 第ό圖係繪示依照本發明之類鰭式場效電晶體的電晶 體的部分透視圖，其中電晶體具有未摻雜的通道區及邊鰭。 第7圖係繪示依照本發明之類鰭式場效電晶體的電晶 體的部分透視圖，纟中電晶體具有未摻雜的通道區，以及 頂層為金屬矽化物之升高的源極與汲極。 第8Α圖係繪示於矽基材上形成淺溝隔離區。 第8Β圖係繪示選擇性場摻雜製程，其目的在於加強絕 緣。 第8C圖係繪示凹陷的淺溝隔離氧化物。 第8D圖係繪示於淺溝隔離區的側壁上實施大傾角的 植入製程。 第8Ε圖係繪示第一含矽層的沉積製程。 第8F圖係繪示第二含矽層的沉積製程。 第9Α圖係繪示在淺溝隔離區形成並填充氧化物後可 選擇性地加入場摻雜物以加強絕緣。 第9Β圖係缘示移除於石夕基材之主動區上的氮化物與 氧化物襯墊層。 第9C圖係繪不形成含矽的間隔凹陷區及邊鰭。 第9D圖係緣不令淺溝隔離氧化物凹陷以暴露出淺溝 隔離區的側壁。 第9Ε圖係繪示第一多晶矽層的沉積製程。 28 1281257 第9F圖係繪示第二多晶矽層的沉積製程。 【主要元件符號說明】 W :厚度 , Η :高度 10 :絕緣層上覆矽結構 12 :鰭 14 :矽基材 ® 16 :埋入氧化物層 18 :閘極 19 :電晶體 20 :光阻圖案 21 :鰭 22 :源極 23 :閘極 24 :臨界電壓植入 ® 25 :汲極 28 :大傾角的植入 ： 30 :間隙壁 • 32 ··金屬矽化物 34 :類平面電晶體的電晶體元件 36 :矽基材 38 :頂表面 40 :淺溝隔離區 29 1281257 :淺溝隔離區 :侧壁 :侧壁 :底部 :底部 :汲極 :源極 :閘極電極 :絕緣層 :金屬^夕化物層 :第二含矽層 :電晶體 :$夕基材 :邊界 :頂表面 :間隔凹陷區 :邊界 :淺溝隔離區 :淺溝隔離區 :邊鰭 :邊鰭 :側壁 :側壁 :底部 30 1281257Body: Advantages possessed; in addition, the electroporation body 7L of the planar-like transistor disclosed in the present invention may also have the advantages of a thin body effect and an elevated source-drain junction. In addition, the transistor component of the planar-like transistor disclosed by the present invention is placed on the block-shaped second material, so that there will be leakage current between the source/no-pole and the block-cut material, so the coated stone is covered on the insulating layer. The oceanic effect occurring in the fin field effect transistor on the icy structure will not occur in the transistor element of the planar-like transistor disclosed in the present invention. The transistor element of a planar transistor such as that shown in Fig. 6 has an undoped and narrow channel; in the field of complementary MOS technology having a junction size of 9 〇 nm, the width of this channel is about 12 Qnm ( As shown in Figure 5, green (5); in the field of complementary MOS technology with a junction size of 65 nm, the width of this channel is about 80 nm (as shown in Figure 5). This narrow channel has edges. Fins and (4). Edge '_ in a simple and small (four) (four) spacer recessed area. In the field of complementary MOS technology with a junction size of 9G nra, the width of the undoped side fin is 40mn, while at the junction, the point size is In the field of complementary MOS technology of 65 nm, the undoped Bianhan has a width of 3. 23 I28l257 All fins preferably have the same width. The manufacturer can set a plurality of fins parallel to each other and to the fins. A common gate is provided to fabricate a transistor with better visibility. The method of fabricating the transistor illustrated in Figures 5-6 is similar to the method illustrated in Figures 4 and 8A-8F, except The channel region depicted in Figures 5-6 is not doped. Therefore, in this embodiment There is no need to implement a threshold voltage doping process. The method of manufacturing the transistor shown in FIG. 6 is similar to the method illustrated in FIG. 4 and FIG. 8A - 8F, but the transistor shown in FIG. There are undoped spacer recessed regions and shallow trench isolation regions 74, 76. As shown in Fig. 6, after the shallow trench isolation regions 74, 76 are formed, the germanium substrate will be slightly recessed, and the depth of the recess is about shallow trench. The depth of the isolation region is 25%. These recessed germanium substrates will preferably form two spacer walls 78, 77, which respectively represent the two boundaries 68, 72 of the active region of the transistor. Then, the shallow trench isolation regions of the partial depth will fill The shallow trench isolation oxide preferably fills the depth of the shallow trench isolation region by 1% to 5〇%. The spacer or edge fin composed of tantalum is formed along both sides of the active region of the transistor. The narrow side fin, It can be used as a channel region of a transistor. The channel width of the channel region of the transistor is preferably 0.4, which may be composed of a plurality of narrow fins and the width of each fin is less than 〇. 2 # m. The gap is narrow or thin, similar to the fin on the insulating layer Field effect transistor _, such a transistor can have the advantage of thin body effect. ^ β polycrystalline yttrium metal gate system and side wall part of the side fin and shallow trench isolation area a: to provide excellent channel area for the transistor Control, this mechanism is similar to the control provided by the double-gate transistor on the overlying structure of the insulating layer. The source 24 1281257 and the immersion are also higher than the sidewall of each shallow trench isolation region, thus improving the short pass. The T effect' is due to the weakening of the electric shank effect between the source and the drain through the block-shaped stone material. The manufacturing process of the transistor shown in Fig. 9A-9F is shown in Fig. 6 A planar channel, such as a side wall and a side wall. f Μ, the picture is similar to the process illustrated by the brother 8A_8F, first forming a shallow trench: the leaving region 'and then filling the oxide therein. As shown in Fig. 9a, in the shallow groove Pp?3, the formation of the German, the system, the clothing can selectively add field dopants to strengthen the rural edge 0 followed by 1 in addition to the stone substrate Nitride and oxide on the active region: After the pad is removed, the germanium substrate will be recessed to form a spacer. As shown by the younger brother, the depth of the depression is about shallow trench isolation/a. In addition, the manufacturer can additionally implement a thermal tempering process (such as fast ^ and = process ^ to repair the recessed area of the gap and shallow trench with (four) ί As shown in Fig. 9D, the shallow trench isolation oxide 88 will be provided by the dry sound two in the domain isolation region, the shallow trench isolation oxide (10), the depression depth of the dry father is the shallow trench isolation region of 5 〇 ^. However, this does not limit the invention, and the shallow depth of 20% 80: the depth of the recess may be between 1 and 2 of the depth of the shallow trench isolation region. Then, a thin film is formed on the substrate by a thermal growth process. ^The listener sacrificial layer' is used to remove the defects caused by the plasma oxide and the ruthenium. After the oxide sacrificial layer is formed, the Ρ-type well and the Ν-type well will also be formed by the doping process. After the formation of the ^i well and the N-type well, the oxide sacrificial layer is privately separated by 25 1281257 and then forms a gate dielectric layer (such as yttrium oxide). The thickness of the gate dielectric layer is about ίο. A~70 A. 曰^口, shown in Figure 9E, followed by deposition of a layer thickness of A400 A~800, and the first 曰曰矽 layer 100' The polysilicon layer is pre-doped to reduce polysilicon in the sidewalls of the trench isolation region. For MOS, the ideal gate electrode material for the day and night, as shown in Figure 9F, will be minimized. A second polycrystalline (four) m having a thickness of about A~_A is formed to fill each of the shallow trench isolation regions. The rear gate electrode 94 (polysilicon) will be formed by a patterned mask and plasma etching process (eg, Figure 9F is shown in green). This will be followed - this is the process of supplementing the MOS process, the case of (4) the source 9Q and the bungee I implant, the metal smelting process and other processes. In another embodiment, the additional mask may also open the transistor component of the fin-like field effect transistor, thereby allowing the process to be bonded to the transistor component of the fin-like field effect transistor, such as shallow trench isolation. The ruthenium of the oxide, the L-cloth on the mouth, and the Shi Xiqian, which is used to form the spacer, are fabricated in a block of the traditional crystal and the crystal of the fin-like field-effect transistor. On the coffin. The component m r screen can also be applied to protect The transistor nr of the continuum-type transistor is protected from the subsequent (4) system. Therefore, this will further increase the recovery of the source and the drain with respect to the channel region. Further, the advantages of the soil are more remarkable. The material of the κ source and the (4) structure is 26 1281257. As described above, the present invention has disclosed several elements of a planar-like fin-like field effect transistor and a method of manufacturing the same. The present invention has been disclosed in a preferred embodiment as described above, but it is not intended to limit the invention, and any skilled person skilled in the art can make various changes and modifications without departing from the scope of the invention. Therefore, the scope of the invention is as defined in the scope of the patent application attached to the following. ', • [Simple description of the schema] = The above and other purposes, features, advantages and futures of the Ming Dynasty are more obvious and understandable. The detailed description of the drawings is as follows: Fig. 1 shows a U-shaped body on the insulating layer, which has a cut-off I#. , the field 2A picture shows the technology key implant process. Ding Zhi, figure wood, surname and critical electric! 2β map shows the gate patterning process of the conventional technology. The implantation process of the large dip angle of the conventional technique of the J 2C pattern is used to form a lightly doped germanium directly for the second (N-channel or ?-channel). 2nd, know the technology to form the process of the gap. Dependent 2 In the conventional technical order, on the source and the bungee, this is a Shi Xihua process or a conductor layer deposition process.枉上贝细金: 3 Figure shows the known technology of the known technology, which has a: 夕: The structure of the wrong crystal on the material - perspective, which makes the transistor have a hybrid pass 27 1281257 Road area. Figure 5 is a partial perspective view of an electromorph of a fin field effect transistor in accordance with the present invention, wherein the transistor has doped channel regions and side fins. The figure is a partial perspective view of an electromorph of a fin field effect transistor in accordance with the present invention, wherein the transistor has an undoped channel region and edge fins. Figure 7 is a partial perspective view of a transistor of a fin field effect transistor in accordance with the present invention, wherein the germanium transistor has an undoped channel region and the top layer is a raised source of germanium metal telluride pole. Figure 8 is a diagram showing the formation of shallow trench isolation regions on a substrate. The eighth figure shows the selective field doping process, which aims to enhance the insulation. Figure 8C shows the shallow trench isolation oxide of the depression. Fig. 8D is an illustration of an implantation process for performing a large dip on the sidewall of the shallow trench isolation region. Figure 8 is a diagram showing the deposition process of the first germanium-containing layer. Figure 8F shows the deposition process of the second germanium-containing layer. Figure 9 is a diagram showing that field dopants can be selectively added to enhance insulation after the shallow trench isolation regions are formed and filled with oxide. Figure 9 is a diagram showing the nitride and oxide liner layer removed from the active region of the Shixi substrate. Figure 9C depicts the formation of interstitial depressions and side fins containing niobium. The 9D pattern is not edged by the shallow trench isolation oxide to expose the sidewalls of the shallow trench isolation region. Figure 9 is a diagram showing the deposition process of the first polysilicon layer. 28 1281257 Figure 9F shows the deposition process of the second polysilicon layer. [Description of main component symbols] W: Thickness, Η: Height 10: Overlay on insulator layer 12: Fin 14: Tantalum substrate® 16: Buried oxide layer 18: Gate 19: Transistor 20: Resistive pattern 21: Fin 22: Source 23: Gate 24: Threshold Voltage Implantation® 25: Deuterium 28: Implantation at Large Dip Angle: 30: Clearance • 32 · Metal Telluride 34: Planar Transistor Crystal Component 36: tantalum substrate 38: top surface 40: shallow trench isolation region 29 1281257: shallow trench isolation region: sidewall: sidewall: bottom: bottom: drain: source: gate electrode: insulating layer: metal Compound layer: second germanium layer: transistor: $ 夕 substrate: boundary: top surface: interval recessed area: boundary: shallow trench isolation area: shallow trench isolation area: side fin: side fin: side wall: side wall: bottom 30 1281257
底部 淺溝隔離氧化物 源極 汲極 閘極電極 金屬矽化物層 :第一多晶矽層 :第二多晶矽層 :硬式罩幕層 :場摻雜物 31Bottom shallow trench isolation oxide source drain gate electrode metal germanide layer: first polysilicon layer: second polysilicon layer: hard mask layer: field dopant 31